diff options
| author | Daiqian Hu <[email protected]> | 2016-11-21 08:54:24 +0800 |
|---|---|---|
| committer | Daiqian Hu <[email protected]> | 2016-11-21 08:54:24 +0800 |
| commit | a95eaad088f61aa55da9d73015cf1ed86e64a67e (patch) | |
| tree | 15b498a08a4aee4b7f8b1627d39c965b3aa3ba98 /network/wlan/WDI/HAL | |
| parent | 1aa0338ec5418345ea0c383e92b4fa19f7c98425 (diff) | |
Re-submit for WDI sample driver to GitHub
Submit WDI sample driver to GitHub for RS1.
Diffstat (limited to 'network/wlan/WDI/HAL')
93 files changed, 32588 insertions, 0 deletions
diff --git a/network/wlan/WDI/HAL/DIRS.WlanS b/network/wlan/WDI/HAL/DIRS.WlanS new file mode 100644 index 00000000..09660bac --- /dev/null +++ b/network/wlan/WDI/HAL/DIRS.WlanS @@ -0,0 +1,3 @@ +DIRS=\ + EFUSE \ + HALSOURCE diff --git a/network/wlan/WDI/HAL/HAL.mk b/network/wlan/WDI/HAL/HAL.mk new file mode 100644 index 00000000..e1176d3b --- /dev/null +++ b/network/wlan/WDI/HAL/HAL.mk @@ -0,0 +1,143 @@ +$(MODULE_NAME)-objs += HAL/HalEEPROM.o +$(MODULE_NAME)-objs += HAL/HalCommon.o +$(MODULE_NAME)-objs += HAL/halDbgCmd.o +$(MODULE_NAME)-objs += HAL/HalCam.o +$(MODULE_NAME)-objs += HAL/HalSIC.o +$(MODULE_NAME)-objs += HAL/HalBT.o +$(MODULE_NAME)-objs += HAL/HalFw.o +$(MODULE_NAME)-objs += HAL/HalPwrSeqCmd.o +$(MODULE_NAME)-objs += HAL/HalPhy.o +$(MODULE_NAME)-objs += HAL/HalDM.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalEfuse.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192SEfuse.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CEfuse.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192DEfuse.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EEfuse.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AEfuse.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/MPT_HelperFunc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/MPT_Main.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/MPT_Phy.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/MPT_Req.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/MPT_RF.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/MPT_Bt.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalBtCoexist.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalBtcCsr1Ant.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalBtcCsr2Ant.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalBtc8723.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalBtc87231Ant.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalBtc87232Ant.o + +ifeq ("$(USE_INTERFACE)", "RT_USB_INTERFACE") +$(MODULE_NAME)-objs += HAL/HalUsb.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CUHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192DUHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8723UHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8723UMPHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EUHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AUHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CUsbTxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CUsbRxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EUsbTxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EUsbRxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AUsbTxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AUsbRxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalUSBLed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AUsbLed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CUsbLed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EUsbLed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CUsbGen.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EUsbGen.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AUsbGen.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CUsbDM.o +endif + +ifeq ("$(USE_INTERFACE)", "RT_PCI_INTERFACE") +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CEHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192DEHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8723EHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EEHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AEHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8723EMPHWImg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CETxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CERxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EETxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EERxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192EETxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192EERxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812ETxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812ERxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalPCIELed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AELed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CELed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EELed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812AELed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CEGen.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EEGen.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812EGen.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192EEGen.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CEIsr.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EEIsr.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812EIsr.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192EEIsr.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CEDM.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EEDM.o +endif + +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CHWImgForWoWLAN.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EHWImgForWoWLAN.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalComTxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalComRxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CTxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CRxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188ETxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188ERxDesc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812Desc.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalComLed.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalComPhyCfg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CPhyCfg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192DPhyCfg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EPhyCfg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812PhyCfg.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CCom.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188ECom.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812Com.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CFirmware.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EFirmware.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812Firmware.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CRf8225.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CPhy8256.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CRf6052.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8192CRf6052_92D.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188ERf6052.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812Rf6052.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8723PwrSeq.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188EPwrSeq.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8812PwrSeq.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8821APwrSeq.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_interface.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_debug.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_HWConfig.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_RTL8192C.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_RTL8192D.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_RTL8188E.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_RegConfig8723A.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8723A_MAC.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8723A_FW.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8723A_RF.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8723A_BB.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalPhyRf.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalPhyRf_8188e.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8188ERateAdaptive.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8188E_MAC.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8188E_RF.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8188E_BB.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8188E_TestChip_MAC.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8188E_TestChip_RF.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8188E_TestChip_BB.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_RegConfig8188E.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/Hal8723AHWImgForWoWLAN.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8812A_MAC.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8812A_RF.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/HalHWImg8812A_BB.o +$(MODULE_NAME)-objs += HAL/HALSOURCE/odm_RegConfig8812A.o diff --git a/network/wlan/WDI/HAL/HALSOURCE/Mp_Precomp.h b/network/wlan/WDI/HAL/HALSOURCE/Mp_Precomp.h new file mode 100644 index 00000000..4215bf67 --- /dev/null +++ b/network/wlan/WDI/HAL/HALSOURCE/Mp_Precomp.h @@ -0,0 +1,2 @@ +#include <Precomp.h> + diff --git a/network/wlan/WDI/HAL/HALSOURCE/hal.vcxproj b/network/wlan/WDI/HAL/HALSOURCE/hal.vcxproj new file mode 100644 index 00000000..7fe68165 --- /dev/null +++ b/network/wlan/WDI/HAL/HALSOURCE/hal.vcxproj @@ -0,0 +1,274 @@ +<?xml version="1.0" encoding="utf-8"?> +<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003"> + <ItemGroup Label="ProjectConfigurations"> + <ProjectConfiguration Include="Win10 Debug|Arm"> + <Configuration>Win10 Debug</Configuration> + <Platform>Arm</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="Win10 Debug|Win32"> + <Configuration>Win10 Debug</Configuration> + <Platform>Win32</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="Win10 Debug|x64"> + <Configuration>Win10 Debug</Configuration> + <Platform>x64</Platform> + </ProjectConfiguration> + <ProjectConfiguration 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<Platform>Arm</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="WinBlue Debug|Win32"> + <Configuration>WinBlue Debug</Configuration> + <Platform>Win32</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="Win8 Debug|Win32"> + <Configuration>Win8 Debug</Configuration> + <Platform>Win32</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="Win7 Debug|Win32"> + <Configuration>Win7 Debug</Configuration> + <Platform>Win32</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="Vista Debug|Win32"> + <Configuration>Vista Debug</Configuration> + <Platform>Win32</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="WinBlue Release|Win32"> + <Configuration>WinBlue Release</Configuration> + <Platform>Win32</Platform> + </ProjectConfiguration> + <ProjectConfiguration Include="Win8 Release|Win32"> + <Configuration>Win8 Release</Configuration> + <Platform>Win32</Platform> + </ProjectConfiguration> + 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Include="*.h;*.hpp;*.hxx;*.hm;*.inl;*.xsd" /> + </ItemGroup> + <!-- /Necessary to pick up propper files from local directory when in the IDE--> + <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" /> +</Project>
\ No newline at end of file diff --git a/network/wlan/WDI/HAL/HalADCSampling.h b/network/wlan/WDI/HAL/HalADCSampling.h new file mode 100644 index 00000000..e08088e6 --- /dev/null +++ b/network/wlan/WDI/HAL/HalADCSampling.h @@ -0,0 +1,105 @@ +#ifndef __INC_ADCSMP_H +#define __INC_ADCSMP_H + +typedef struct _RT_ADCSMP_STRING{ + pu4Byte Octet; + u4Byte Length; + u4Byte buffer_size; + u4Byte start_pos; +}RT_ADCSMP_STRING, *PRT_ADCSMP_STRING; + + +typedef enum _RT_ADCSMP_TRIG_SEL +{ + ADCSMP_BB_TRIG, + ADCSMP_MAC_TRIG, +}RT_ADCSMP_TRIG_SEL, *PRT_ADCSMP_TRIG_SEL; + + +typedef enum _RT_ADCSMP_TRIG_SIG_SEL +{ + ADCSMP_TRIG_CRCOK, + ADCSMP_TRIG_CRCFAIL, + ADCSMP_TRIG_CCA, + ADCSMP_TRIG_REG, +}RT_ADCSMP_TRIG_SIG_SEL, *PRT_ADCSMP_TRIG_SIG_SEL; + + +typedef enum _RT_ADCSMP_STATE +{ + ADCSMP_STATE_IDLE, + ADCSMP_STATE_SET, + ADCSMP_STATE_QUERY, +}RT_ADCSMP_STATE, *PRT_ADCSMP_STATE; + + +typedef struct _RT_ADCSMP +{ + RT_ADCSMP_STRING ADCSmpBuf; + RT_ADCSMP_STATE ADCSmpState; + RT_ADCSMP_TRIG_SEL ADCSmpTrigSel; + RT_ADCSMP_TRIG_SIG_SEL ADCSmpTrigSigSel; + u1Byte ADCSmpDmaDataSigSel; + u1Byte ADCSmpTriggerTime; + u2Byte ADCSmpPollingTime; +}RT_ADCSMP, *PRT_ADCSMP; + + +VOID +ADCSmpWorkItemCallback( + IN PVOID pContext + ); + + +VOID +ADCSmp_Set( + IN PADAPTER Adapter, + IN RT_ADCSMP_TRIG_SEL TrigSel, + IN RT_ADCSMP_TRIG_SIG_SEL TrigSigSel, + IN u1Byte DmaDataSigSel, + IN u1Byte TriggerTime, + IN u2Byte PollingTime + ); + + +RT_STATUS +ADCSmp_Query( + IN PADAPTER Adapter, + IN ULONG InformationBufferLength, + OUT PVOID InformationBuffer, + OUT PULONG BytesWritten + ); + +VOID +ADCSmp_Stop( + IN PADAPTER Adapter + ); + +VOID +ADCSmp_Init( + PADAPTER Adapter + ); + + +VOID +ADCSmp_DeInit( + PADAPTER Adapter + ); + +VOID +Dump_MAC( + PADAPTER Adapter + ); + +VOID +Dump_BB( + PADAPTER Adapter + ); + +VOID +Dump_RF( + PADAPTER Adapter + ); + +#endif + diff --git a/network/wlan/WDI/HAL/HalCam.h b/network/wlan/WDI/HAL/HalCam.h new file mode 100644 index 00000000..70069cac --- /dev/null +++ b/network/wlan/WDI/HAL/HalCam.h @@ -0,0 +1,169 @@ +#include "Mp_Precomp.h" + + +#define CAM_CONTENT_COUNT 8 +#define CAM_PAIRWISE_KEY_POSITION 4 + +// 0~3 : Default Key +// 4 : Default Port Station Key ( Pairwise key ) +// 5~HALF_CAM_ENTRY - MAX_BT_ASOC_ENTRY_NUM : TDSL +// HALF_CAM_ENTRY ~ TOTAL_CAM_ENTRY-1 : ExtAP( VWifi , XP-ExtAP and Win7/8 ExtAP ) +// CAM_EXTSTA_PAIRWISE_KEY_POSITION : ExtSta key ( Pairwise key ) +#define CAM_TDSL_START_INDEX 5 + +#define CFG_DEFAULT_KEY BIT5 +#define CFG_VALID BIT15 + + +//add for AP HW , CCW + +u1Byte AP_CamAddOneEntry( + PADAPTER Adapter, + u1Byte *pucMacAddr, + u4Byte ulKeyId, + u4Byte ulEncAlg, + u4Byte ulUseDK, + u1Byte *pucKey +); + +u1Byte AP_Setkey( + PADAPTER Adapter, + u1Byte *pucMacAddr, + u4Byte ulKeyId, + u4Byte ulEncAlg, + u4Byte ulUseDK, + u1Byte *pucKey); + + +u4Byte AP_FindFreeEntry( + PADAPTER Adapter, + pu1Byte Macaddr + ); + +void AP_ClearAllKey( + PADAPTER Adapter); + + +void AP_RemoveKey( + PADAPTER Adapter, + PRT_WLAN_STA pSTA); + +//Add for AP enc ,CCW +//====================== +u1Byte CamAddOneEntry( + PADAPTER Adapter, + u1Byte *pucMacAddr, + u4Byte ulKeyId, + u4Byte ulEntryId, + u4Byte ulEncAlg, + u4Byte ulUseDK, + u1Byte *pucKey +); +int CamDeleteOneEntry( + PADAPTER Adapter, + u1Byte *pucMacAddr, + u4Byte ulKeyId +); + +void CAMtest( + PADAPTER Adapter, + u1Byte ucTestItem); + +void test_cam( + PADAPTER Adapter); + +//---------------------------------------- +//Function declartion for internal usage of CAM.c +//---------------------------------------- + +u1Byte CAM_find_usable( + PADAPTER Adapter); + +void CAM_program_entry( + PADAPTER Adapter, + u4Byte iIndex, + u1Byte *pucMacad, + u1Byte *pucKey128, + u2Byte usConfig); + +void CAM_read_entry( + PADAPTER Adapter, + u4Byte iIndex, + u1Byte *pucMacad, + u1Byte *pucKey128, + u2Byte *usConfig); + +void CAM_read_mac_config( + PADAPTER Adapter, + u1Byte ucIndex, + u1Byte *pucMacad, + u2Byte *pusTempConfig); + +void CAM_mark_invalid( + PADAPTER Adapter, + u1Byte ucIndex); + +void CAM_empty_entry( + PADAPTER Adapter, + u1Byte ucIndex); + +void CAM_read_entry( + PADAPTER Adapter, + u4Byte index, + u1Byte *macad, + u1Byte *key128, + u2Byte *config); + +void CAM_debug_print( + u1Byte *pucMac, + u1Byte *pucKey, + u2Byte usConfig); +VOID +CamDumpAll( PADAPTER Adapter); + +VOID +CamDumpAllCallbackWorkItem( + IN PVOID pContext); + +VOID +CamResetAllEntry(PADAPTER Adapter); + + +VOID +AP_CamRestoreAllEntry( + PADAPTER Adapter); + + +VOID +CamRestoreAllEntry(PADAPTER Adapter); + + +void build_cam( + PADAPTER Adapter); + +void loopcam( + PADAPTER Adapter +); +void SingleCam( + PADAPTER Adapter); + +void build_16_cam( + PADAPTER Adapter); + +void BurstTxCAM(void); +//----IF Emily +void CAM_Policy_Verify(void); + + +//vivi added for new cam search flow, 20091028. +u4Byte Sta_FindFreeEntry( + PADAPTER Adapter, + pu1Byte pMacAddr, + u4Byte KeyIndex, + u4Byte ulEncAlg, + u1Byte *pucKey +); + + + + diff --git a/network/wlan/WDI/HAL/HalComDef.h b/network/wlan/WDI/HAL/HalComDef.h new file mode 100644 index 00000000..7d014196 --- /dev/null +++ b/network/wlan/WDI/HAL/HalComDef.h @@ -0,0 +1,575 @@ +#ifndef __INC_HALDEFCOM_H +#define __INC_HALDEFCOM_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalComDef.h + +Abstract: + Defined 92C/88E common data structure. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-12-13 Isaiah Create. +--*/ + +/*--------------------------Define Parameters-------------------------------*/ + + + +//#pragma mark -- Chip specific. -- +extern const char *const GLBwSrc[]; + +//------------------------------------------------------------------------- +// Chip specific +//------------------------------------------------------------------------- + +#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) +#define CHIP_BONDING_92C_1T2R 0x1 +#define CHIP_BONDING_88C_USB_MCARD 0x2 +#define CHIP_BONDING_88C_USB_HP 0x1 + +// +// 2011.01.06. Define new structure of chip version for RTL8723A and so on. Added by tynli. +// Modify Manufacture and ROM version field, revised by Roger, 2012.11.01. +// +/* + | BIT15:12 | BIT11:9 | BIT 8:7 | BIT6:4 | BIT3 | BIT 2:0 | + |-----------------+--------------+----------------+----------+------------+---------| + | IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Name | + | | | TSMC/UMC/SMIC | | TEST/NORMAL| | + | | | | | | | +*/ +// [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 +// [11:9] ROM version +// [8:7] Manufacturer: TSMC=0, UMC=1, SMIC=2 +// [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2, 3T3R=3 +// [3] Chip type: TEST=0, NORMAL=1 +// [2:0] IC name: 81xxC=0, 8723A=1, 8192D=2, 8188E=3, 8812=4, 8821=5, 8723B=6, 8814A=7, +// +// Since 2014.06.18, we use another new format(v2), which defined below this block. + +// IC Name +#define CHIP_8723A BIT(0) +#define CHIP_92D BIT(1) +#define CHIP_8812 BIT(2) +#define CHIP_8188E (BIT(0)|BIT(1)) +#define CHIP_8821 (BIT(0)|BIT(2)) +#define CHIP_8723B (BIT(1)|BIT(2)) +#define CHIP_8814A (BIT(0)|BIT(1)|BIT(2)) + +// Chip type +#define NORMAL_CHIP BIT(3) + +//RF type +#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) +#define RF_TYPE_1T2R BIT(4) +#define RF_TYPE_2T2R BIT(5) +#define RF_TYPE_3T3R (BIT(4)|BIT(5)) + +//Manufacture +#define CHIP_VENDOR_UMC BIT(7) +#define CHIP_VENDOR_SMIC BIT(8) +//Cut version +#define A_CUT_VERSION 0 +#define B_CUT_VERSION BIT(12) +#define C_CUT_VERSION BIT(13) +#define D_CUT_VERSION ((BIT(12)|BIT(13))) +#define E_CUT_VERSION BIT(14) +#define I_CUT_VERSION BIT(15) +#define J_CUT_VERSION ((BIT(15)|BIT(12))) +#define K_CUT_VERSION ((BIT(15)|BIT(13))) + +// MASK +#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) +#define CHIP_TYPE_MASK BIT(3) +#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) +#define MANUFACTUER_MASK (BIT(7)|BIT(8)) +#define ROM_VERSION_MASK (BIT(9)|BIT(10)|BIT(11)) +#define CUT_VERSION_MASK (BIT(12)|BIT(13)|BIT(14)|BIT(15)) + +// Get element +#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) +#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK) +#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK) +#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) +#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK) +#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) + +// -------------------------------- +// ChipVersion V2 +// -------------------------------- +// 2014.06.18 Define new structure of chip version for RTL8703B and so on. Added by TzuHang. +/* + + | BIT 31:28 | BIT 27:24 | BIT 23:20 | BIT 19:17 | BIT16 | BIT 15 | BIT14 | BIT 13:12 | BIT11:8 | BIT 7:0 | + |-----------+-------------+-----------+-------------+-------------+----------------+---------+---------------+---------+---------| + | RESERVE | CUT VERSION | RESERVE | ROM VERSION | CHIP TYPE | BT EXIST IN IC | RESERVE | MANUFACTURE | RF TYPE | IC NAME | + | | | | | TEST/NORMAL | | | TSMC/UMC/SMIC | | | + +*/ +// Remaining the meaning corresponding to those value in each column we used before. +// And below is those be added newly +// [27:24] CUT VERSION: A-cut=0 +// [19:17] ROM VERSION +// [16] CHIP TYPE: +// [15] BT exist: No=0, Yes=1 +// [13:12] MANUFACTURE: TSMC=0, UMC=1, SMIC=2 +// [11:8] RF TYPE: 1T1R=0, 1T2R=1, 2T2R=2, 3T3R=3 +// [7:0] IC name: 8703B=0x0B + +// IC Name +#define CHIP_8821B 0x09 +#define CHIP_8822B 0x0A +#define CHIP_8703B 0x0B +#define CHIP_8188F 0x0C +#define CHIP_8723D 0x0F + +// RF Type +#define RF_TYPE_1T1R_v2 0 +#define RF_TYPE_1T2R_v2 0x1 +#define RF_TYPE_2T2R_v2 0x2 +#define RF_TYPE_3T3R_v2 0x3 + +// Manufacture +#define CHIP_VENDOR_UMC_v2 0x1 +#define CHIP_VENDOR_SMIC_v2 0x2 + +// BT exist or not +#define BT_NOT_EXIST_IN_CHIP 0 +#define BT_EXIST_IN_CHIP 0x1 + +// Chip type +#define NORMAL_CHIP_v2 0x1 + +// Cut Version +#define A_CUT_VERSION_v2 0 +#define B_CUT_VERSION_v2 0x1 +#define C_CUT_VERSION_v2 0x2 +#define D_CUT_VERSION_v2 0x3 +#define E_CUT_VERSION_v2 0x4 +#define I_CUT_VERSION_v2 0x8 + +// GET element +#define SFT_AND_GET_FROM_CHIPVER(VERSION, MASK, SFT) ((VERSION>>SFT) & MASK) + +#define GET_CVID_IC_TYPE_v2(VERSION) SFT_AND_GET_FROM_CHIPVER(VERSION, 0xFF, 0) +#define GET_CVID_RF_TYPE_v2(VERSION) SFT_AND_GET_FROM_CHIPVER(VERSION, 0xF, 8) +#define GET_CVID_MANUFACTUER_v2(VERSION) SFT_AND_GET_FROM_CHIPVER(VERSION, 0x3, 12) +#define GET_CVID_BT_EXIST_v2(VERSION) SFT_AND_GET_FROM_CHIPVER(VERSION, 0x1, 15) +#define GET_CVID_CHIP_TYPE_v2(VERSION) SFT_AND_GET_FROM_CHIPVER(VERSION, 0x1, 16) +#define GET_CVID_ROM_VERSION_v2(VERSION) SFT_AND_GET_FROM_CHIPVER(VERSION, 0x7, 17) +#define GET_CVID_CUT_VERSION_v2(VERSION) SFT_AND_GET_FROM_CHIPVER(VERSION, 0xF, 24) + +// MASK for fetching info ***From MAC*** (NOT FROM ChipVersion) +#define MK_CHIP_NAME 0xFF +#define MK_RF_TYPE 0xF << 27 // 0x8000000 +#define MK_MANU 0x3 << 18 // 0x00C0000 +#define MK_BT_EXIST 0x1 << 16 // 0x0010000 +#define MK_CHIP_TYPE 0x1 << 23 // 0x0800000 +#define MK_CUT_VER 0xF << 12 // 0x000F000 + +// The value of each info, which be aligned to head of the byte. +#define VAL_CHIP_NAME(BYTE4) ((BYTE4 & MK_CHIP_NAME)) +#define VAL_RF_TYPE(BYTE4) ((BYTE4 & MK_RF_TYPE) >> 27) +#define VAL_MANU(BYTE4) ((BYTE4 & MK_MANU) >> 18) +#define VAL_BT_EXIST(BYTE4) ((BYTE4 & MK_BT_EXIST) >> 16) +#define VAL_CHIP_TYPE(BYTE4) ((BYTE4 & MK_CHIP_TYPE) >> 23) +#define VAL_CUT_VER(BYTE4) ((BYTE4 & MK_CUT_VER) >> 12) + +// SET into Chip_Version +#define SFT_AND_SET_IN_CHIPVER(BUFFER, INPUT, SFT) { BUFFER = (VERSION_8192C)(BUFFER | (INPUT<<SFT)); } + +#define SET_CVID_CHIP_NAME(BUFFER, INPUT) SFT_AND_SET_IN_CHIPVER(BUFFER, INPUT, 0) +#define SET_CVID_RF_TYPE(BUFFER, INPUT) SFT_AND_SET_IN_CHIPVER(BUFFER, INPUT, 8) +#define SET_CVID_MANU(BUFFER, INPUT) SFT_AND_SET_IN_CHIPVER(BUFFER, INPUT, 12) +#define SET_CVID_BT_EXIST(BUFFER, INPUT) SFT_AND_SET_IN_CHIPVER(BUFFER, INPUT, 15) +#define SET_CVID_CHIP_TYPE(BUFFER, INPUT) SFT_AND_SET_IN_CHIPVER(BUFFER, INPUT, 16) +#define SET_CVID_CUT_VER(BUFFER, INPUT) SFT_AND_SET_IN_CHIPVER(BUFFER, INPUT, 24) + +/*------------------------------ Chip/EFUSE Macro ----------------------------*/ +//#pragma mark -- Chip/EFUSE Macro. -- +//---------------------------------------------------------------------------- +#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? TRUE : FALSE) +#define IS_8188E_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E)? TRUE : FALSE) +#define IS_8723A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A)? TRUE : FALSE) +#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? TRUE : FALSE) +#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812)? TRUE : FALSE) +#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821)? TRUE : FALSE) +#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B)? TRUE : FALSE) +#define IS_8188F_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F)? TRUE : FALSE) +#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A)? TRUE : FALSE) + +#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version))? TRUE: FALSE) + +#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? FALSE : TRUE) +#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? TRUE : FALSE) +#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? TRUE : FALSE) +#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R)? TRUE : FALSE) + +#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) ==0)? TRUE: FALSE) +#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? TRUE: FALSE) +#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC)? TRUE: FALSE) + +#define IS_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == B_CUT_VERSION) ? TRUE : FALSE) +#define IS_C_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == C_CUT_VERSION) ? TRUE : FALSE) +#define IS_C_CUT_AFTER(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= C_CUT_VERSION) ? TRUE : FALSE) + + +#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE) +#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version)?((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? FALSE : TRUE) : FALSE):FALSE) +#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE):FALSE): FALSE) + +#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE: FALSE) : FALSE) +#define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) +#define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE) : FALSE) +#define IS_92D_E_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8723A_A_CUT(_Adapter) ((IS_8723A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8723A_B_CUT(_Adapter) ((IS_8723A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == B_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8188F_A_CUT(_Adapter) ((IS_8188F_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8188F_B_CUT(_Adapter) ((IS_8188F_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == B_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8188E_SMIC_C_CUT(_Adapter) ((IS_8188E_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == K_CUT_VERSION) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8188E_SMIC_SERIES(_Adapter) ((IS_8188E_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8821A_B_CUT(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == B_CUT_VERSION) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8821A_C_CUT(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) + + +#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8723B_A_CUT(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >> 12 == 0) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8723B_B_CUT(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >> 12 == 1) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8723B_C_CUT(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >> 12 == 1) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8723B_D_CUT(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >> 12 == 3) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8723B_D_CUT_BEFORE(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >> 12 <= 3) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8723B_AFTER_F_CUT(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >> 12 >= 4) ? TRUE : FALSE) : FALSE) + + + +#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) + + +#define GET_RF_TYPE(_Adapter) ((u1Byte)(((PHAL_DATA_TYPE)(_Adapter->HalData))->RF_Type)) +#define IS_BOOT_FROM_EEPROM(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->EepromOrEfuse) +#define IS_BOOT_FROM_EEPROM_93C46(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->EEType == EEPROM_93C46) +#define IS_BOOT_FROM_EEPROM_93C56(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->EEType == EEPROM_93C56) +#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? TRUE : FALSE) +#define IS_POLARITY_HIGH_ACTIVE(_Adapter) ((((PHAL_DATA_TYPE)(_Adapter->HalData))->PolarityCtl) ? TRUE : FALSE) + +// -------------------------------- +// ChipVersion V2 +// -------------------------------- +#define IS_NORMAL_CHIP_v2(version) ((GET_CVID_CHIP_TYPE_v2(version))? TRUE: FALSE) + +#define IS_1T1R_v2(version) ((GET_CVID_RF_TYPE_v2(version))? FALSE : TRUE) +#define IS_1T2R_v2(version) ((GET_CVID_RF_TYPE_v2(version) == RF_TYPE_1T2R_v2)? TRUE : FALSE) +#define IS_2T2R_v2(version) ((GET_CVID_RF_TYPE_v2(version) == RF_TYPE_2T2R_v2)? TRUE : FALSE) +#define IS_3T3R_v2(version) ((GET_CVID_RF_TYPE_v2(version) == RF_TYPE_3T3R_v2)? TRUE : FALSE) + +#define IS_CHIP_VENDOR_TSMC_v2(version) ((GET_CVID_MANUFACTUER_v2(version) ==0)? TRUE: FALSE) +#define IS_CHIP_VENDOR_UMC_v2(version) ((GET_CVID_MANUFACTUER_v2(version) == CHIP_VENDOR_UMC_v2)? TRUE: FALSE) +#define IS_CHIP_VENDOR_SMIC_v2(version) ((GET_CVID_MANUFACTUER_v2(version) == CHIP_VENDOR_SMIC_v2)? TRUE: FALSE) + +#define IS_88E_SERIES(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bIs88eSeries) +#define IS_NIC_EXIST_BT(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bIsNicExistBt) +#define IS_NIC_SUPPORT_WAPI(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bNicSupportWapi) +#define ENABLE_SINGLE_AMPDU(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bEnableSingleAmpdu) +#define IS_NEED_EXT_IQK(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bNeedExtIQK) +#define CHECK_HIDDEN_SSID(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bCheckHiddenSsid) +#define DISABLE_RTS_ON_AMPDU(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bDisableRtsOnAmpdu) +#define IS_SUP_CLK_ON_EXCEP_RESN(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bSupClkOnExcepResn) +#define IS_REMOVE_ZERO_LEN_BUF(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bRemoveZeroLenBuf) +#define IS_LEAVE_PS_BF_EN_NIC(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bLeavePsBeforeEnNic) + + +#define WLAN_802_11N 0 +#define WLAN_802_11AC 1 + +#define IS_DOT_11N_SERIES(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bNicWirelessMode == WLAN_802_11N) +#define IS_DOT_11AC_SERIES(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->bNicWirelessMode == WLAN_802_11AC) + +#define GET_CHIP_ID(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->ChipID) +#define GET_CHIP_VERSION(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->ChipVer) +#define GET_MAX_RX_DMA_BUFFER_SIZE(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->MaxRxDmaBufferSize) +#define GET_MAX_TX_BUFFER_SIZE(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->MaxTxBufSize) +#define GET_TCB_NUM_OF_MEM_SIZE_0(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->TcbNumOfMemSize0) +#define GET_TCB_NUM_OF_MEM_SIZE_1(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->TcbNumOfMemSize1) +#define GET_TX_DESC_NUM(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->TxDescNum) +#define GET_TX_DESC_NUM_BE_Q(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->TxDescNumBeQ) +#define GET_TX_DESC_NUM_MP(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->TxDescNumMp) +#define GET_TX_DESC_NUM_BE_Q_MP(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->TxDescNumBeQMp) + +#define GET_MAX_RX_BUFFER_SIZE(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->MaxRxBufSize) +#define GET_MAX_SUBFRAME_CNT_MM_SIZE0(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->MaxSubframeCntMmSize0) +#define GET_MAX_SUBFRAME_CNT_MM_SIZE1(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->MaxSubframeCntMmSize1) +#define GET_RFD_NUM_OF_MM_SIZE_0(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->RfdNumMmSize0) +#define GET_RFD_DESC_NUM_OF_MM_SIZE_0(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->RxDescNumMmSize0) +#define GET_RFD_NUM_OF_MM_SIZE_1(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->RfdNumMmSize1) +#define GET_RFD_DESC_NUM_OF_MM_SIZE_1(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->RxDescNumMmSize1) + +#define IS_PCI_INERFACE(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->ChipVer == 0x1) +#define IS_USB_INERFACE(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->ChipVer == 0x2) +#define IS_SDIO_INERFACE(_Adapter) (((PHAL_DATA_TYPE)(_Adapter->HalData))->ChipVer == 0x3) + + + + +/*------------------------------ RTL81xxxDefCom.h Definiction -----------------------*/ +//Move 8192CDefCom.h/8188EDefCom.h to here. + +#define HAL_DM_DIG_DISABLE BIT0 // Disable Dig +#define HAL_DM_HIPWR_DISABLE BIT1 // Disable High Power + +#define PHY_RSSI_SLID_WIN_MAX 100 +#define PHY_LINKQUALITY_SLID_WIN_MAX 20 + + +//----------------------------------------------------------- +// +// Queue mapping +// +//----------------------------------------------------------- +#define BK_QUEUE 0 +#define BE_QUEUE 1 +#define VI_QUEUE 2 +#define VO_QUEUE 3 +#define BEACON_QUEUE 4 +#define TXCMD_QUEUE 5 +#define MGNT_QUEUE 6 +#define HIGH_QUEUE 7 +#define HCCA_QUEUE 8 + +#define HIGH0_QUEUE HIGH_QUEUE +#define HIGH1_QUEUE 9 +#define HIGH2_QUEUE 10 +#define HIGH3_QUEUE 11 +#define HIGH4_QUEUE 12 +#define HIGH5_QUEUE 13 +#define HIGH6_QUEUE 14 +#define HIGH7_QUEUE 15 + +#define LOW_QUEUE BE_QUEUE +#define NORMAL_QUEUE MGNT_QUEUE +#if (NEW_EARLY_MODE_ENABLE==1) +#define NEW_EARLY_MODE_QUEUE BE_QUEUE //add by ylb 20130409 +#endif + +#define IS_DATA_QUEUE(_queueIdx) (((BK_QUEUE == _queueIdx) || (BE_QUEUE == _queueIdx) || (VI_QUEUE == _queueIdx) || (VO_QUEUE == _queueIdx))? TRUE: FALSE) +// +// Queue Select Value in TxDesc +// +#define QSLT_BK 0x2//0x01 +#define QSLT_BE 0x0 +#define QSLT_VI 0x5//0x4 +#define QSLT_VO 0x7//0x6 +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +#define RX_MPDU_QUEUE 0 +#define RX_CMD_QUEUE 1 +#define RX_MAX_QUEUE 2 + + + +#define RX_DESC_SIZE 32 + +#define HAL_DEFAULT_BEACON_TYPE BEACON_SEND_AUTO_HW + +//----------------------------------------------------------- +// MAC/BB/RF +//----------------------------------------------------------- + +#define MAX_LINES_HWCONFIG_TXT 2000 +#define MAX_BYTES_LINE_HWCONFIG_TXT 256 + + +// Rx smooth factor +#define Rx_Smooth_Factor 20 + + +//H2C related +typedef enum _H2C_STATUS{ + H2C_STATUS_SUCCESS, + H2C_STATUS_FAIL_ANOTHER_H2C_UNDER_PROGRESS, + H2C_STATUS_FAIL_RF_OFF, + H2C_STATUS_FAIL_FW_READ_CLEAR_TIMEOUT, + H2C_STATUS_MAX +}H2C_STATUS,*PH2C_STATUS; + +#define MAX_H2C_QUEUE_NUM 64 + +/*------------------------------ end of RTL81xxxDefCom.h Definiction -----------------------*/ + + +// For store intial value of BB register +typedef struct _BB_INIT_REGISTER{ + u2Byte offset; + + u4Byte value; + +}BB_INIT_REGISTER, *PBB_INIT_REGISTER; + + + +// SDIO Tx FIFO related +#define SDIO_TX_FREE_PG_QUEUE 5 // The number of Tx FIFO free page, 8821B: HIQ/MIQ/LOQ/PUBQ/EXTQ. +#define SDIO_TX_FREE_PG_QUEUE_8814A 5 //20130422 KaiYuan add for 8814 Extra Queue + +//#define SDIO_TX_FIFO_PAGE_SZ 128 // For RTL8723A/RTL8723B 32K Tx FIFO Size +//#define SDIO_TX_FIFO_PAGE_SZ_8821 256 + +#define SDIO_TX_FIFO_PAGE_SIZE(_Adapter) \ + ((IS_HARDWARE_TYPE_8812A(_Adapter) || IS_HARDWARE_TYPE_8821A(_Adapter) \ + || IS_HARDWARE_TYPE_8192E(_Adapter))? \ + 256 : 128) + + + +typedef struct _QUEUE_INDEX_LIST +{ + u1Byte QueueIdxArray[32]; + u1Byte Len; +}QUEUE_INDEX_LIST, *PQUEUE_INDEX_LIST; + +#if RX_AGGREGATION +typedef enum _RX_AGG_MODE{ + RX_AGG_DISABLE, + RX_AGG_DMA, + RX_AGG_USB, + RX_AGG_DMA_USB +}RX_AGG_MODE, *PRX_AGG_MODE; +#endif + +typedef struct _LOG_SYS_INTERRUPT +{ + u4Byte nISR_GPIO9; + u4Byte nISR_GPIO12_0; + u4Byte nISR_SPS_OCP; + u4Byte nISR_RON; + u4Byte nISR_PDN; + +} LOG_SYS_INTERRUPT, *PLOG_SYS_INTERRUPT; + + + +//should be renamed and moved to another file +typedef enum _INTERFACE_SELECT_8192CUSB{ + INTF_SEL0_USB = 0, // USB + INTF_SEL1_USB_High_Power = 1, // USB with high power PA + INTF_SEL2_MINICARD = 2, // Minicard + INTF_SEL3_USB_Solo = 3, // USB solo-Slim module + INTF_SEL4_USB_Combo = 4, // USB Combo-Slim module + INTF_SEL5_USB_Combo_MF = 5, // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card +} INTERFACE_SELECT_8192CUSB, *PINTERFACE_SELECT_8192CUSB; + +typedef INTERFACE_SELECT_8192CUSB INTERFACE_SELECT_USB; + +typedef struct _LOG_INTERRUPT +{ + u4Byte nISR_RX_REQUEST; + u4Byte nISR_AVAL; + u4Byte nISR_TXERR; + u4Byte nISR_RXERR; + u4Byte nISR_TXFOVW; + u4Byte nISR_RXFOVW; + u4Byte nISR_TXBCNOK; + u4Byte nISR_TXBCNERR; + u4Byte nISR_BCNERLY_INT; + u4Byte nISR_C2HCMD; + u4Byte nISR_CPWM1; + u4Byte nISR_CPWM2; + u4Byte nISR_HSISR_IND; + u4Byte nISR_GTINT3_IND; + u4Byte nISR_GTINT4_IND; + u4Byte nISR_PSTIMEOUT; + u4Byte nISR_OCPINT; + u4Byte nISR_ATIMEND; + u4Byte nISR_ATIMEND_E; + u4Byte nISR_CTWEND; + u4Byte nISR_MCU_ERR; // For 8188ES only + u4Byte nISR_BIT32_TOGGLE; // For 8188ES only + u4Byte nIMR_C2HCMD; +} LOG_INTERRUPT, *PLOG_INTERRUPT; + + +u4Byte +HAL_GetCutVersion( + IN PADAPTER pAdapter + ); +VOID +HAL_SetBcnCtrlReg( + IN PADAPTER Adapter, + IN u1Byte SetBits, + IN u1Byte ClearBits + ); +VOID +HAL_UpdateDefaultSetting( + IN PADAPTER pAdapter + ); + +BOOLEAN +HAL_ChipSupport80MHz( + IN PADAPTER Adapter + ); + +BOOLEAN +HAL_WorkAroundForLowTxRaise( + IN PADAPTER Adapter + ); + +BOOLEAN +HAL_DisableEdcaTurbo( + IN PADAPTER Adapter + ); + +BOOLEAN +HAL_EnableBeQTxOpLimit( + IN PADAPTER Adapter + ); + +BOOLEAN +HAL_ActBcmRxFailRelink( + IN PADAPTER Adapter, + IN PRT_WLAN_BSS pBssDesc + ); + +BOOLEAN +HAL_IsEdcaBiasRx( + IN PADAPTER Adapter, + IN PRT_WLAN_BSS pBssDesc + ); + +BOOLEAN +HAL_SkipMcsRates( + IN PADAPTER Adapter + ); + +VOID +HalSetFcsAdjustTsf( + IN PADAPTER Adapter + ); + +VOID +HAL_DownloadRSVD_PreCfg( + IN PADAPTER Adapter +); +RT_STATUS +HAL_DownloadRSVD_PostCfg( + IN PADAPTER Adapter +); +BOOLEAN IS_HAL_MAC_INIT( + IN PADAPTER Adapter +); + +#endif diff --git a/network/wlan/WDI/HAL/HalComDesc.h b/network/wlan/WDI/HAL/HalComDesc.h new file mode 100644 index 00000000..3bfbc70d --- /dev/null +++ b/network/wlan/WDI/HAL/HalComDesc.h @@ -0,0 +1,445 @@ +#ifndef __INC_HALCOMDESC_H +#define __INC_HALCOMDESC_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalComDesc.h + +Abstract: + Defined 92C/88E common Descriptor structure. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-12-14 Isaiah Create. +--*/ + +/*--------------------------Define Parameters-------------------------------*/ + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------------ Tx Desc definition Macro ------------------------*/ +//#pragma mark -- Tx Desc related definition. -- +//---------------------------------------------------------------------------- +//----------------------------------------------------------- +// Rate +//----------------------------------------------------------- +#define DESC92C_RATEMCS15_SG 0x1c +#define DESC92C_RATEMCS32 0x20 + +#if 0 +// CCK Rates, TxHT = 0 +#define DESC_RATE1M 0x00 +#define DESC_RATE2M 0x01 +#define DESC_RATE5_5M 0x02 +#define DESC_RATE11M 0x03 +// OFDM Rates, TxHT = 0 +#define DESC_RATE6M 0x04 +#define DESC_RATE9M 0x05 +#define DESC_RATE12M 0x06 +#define DESC_RATE18M 0x07 +#define DESC_RATE24M 0x08 +#define DESC_RATE36M 0x09 +#define DESC_RATE48M 0x0A +#define DESC_RATE54M 0x0B +// MCS Rates, TxHT = 1 +#define DESC_RATEMCS0 0x0C +#define DESC_RATEMCS1 0x0D +#define DESC_RATEMCS2 0x0E +#define DESC_RATEMCS3 0x0F +#define DESC_RATEMCS4 0x10 +#define DESC_RATEMCS5 0x11 +#define DESC_RATEMCS6 0x12 +#define DESC_RATEMCS7 0x13 +#define DESC_RATEMCS8 0x14 +#define DESC_RATEMCS9 0x15 +#define DESC_RATEMCS10 0x16 +#define DESC_RATEMCS11 0x17 +#define DESC_RATEMCS12 0x18 +#define DESC_RATEMCS13 0x19 +#define DESC_RATEMCS14 0x1A +#define DESC_RATEMCS15 0x1B +#define DESC_RATEMCS16 0x1C +#define DESC_RATEMCS17 0x1D +#define DESC_RATEMCS18 0x1E +#define DESC_RATEMCS19 0x1F +#define DESC_RATEMCS20 0x20 +#define DESC_RATEMCS21 0x21 +#define DESC_RATEMCS22 0x22 +#define DESC_RATEMCS23 0x23 +#define DESC_RATEMCS24 0x24 +#define DESC_RATEMCS25 0x25 +#define DESC_RATEMCS26 0x26 +#define DESC_RATEMCS27 0x27 +#define DESC_RATEMCS28 0x28 +#define DESC_RATEMCS29 0x29 +#define DESC_RATEMCS30 0x2A +#define DESC_RATEMCS31 0x2B +#define DESC_RATEVHTSS1MCS0 0x2C +#define DESC_RATEVHTSS1MCS1 0x2D +#define DESC_RATEVHTSS1MCS2 0x2E +#define DESC_RATEVHTSS1MCS3 0x2F +#define DESC_RATEVHTSS1MCS4 0x30 +#define DESC_RATEVHTSS1MCS5 0x31 +#define DESC_RATEVHTSS1MCS6 0x32 +#define DESC_RATEVHTSS1MCS7 0x33 +#define DESC_RATEVHTSS1MCS8 0x34 +#define DESC_RATEVHTSS1MCS9 0x35 +#define DESC_RATEVHTSS2MCS0 0x36 +#define DESC_RATEVHTSS2MCS1 0x37 +#define DESC_RATEVHTSS2MCS2 0x38 +#define DESC_RATEVHTSS2MCS3 0x39 +#define DESC_RATEVHTSS2MCS4 0x3A +#define DESC_RATEVHTSS2MCS5 0x3B +#define DESC_RATEVHTSS2MCS6 0x3C +#define DESC_RATEVHTSS2MCS7 0x3D +#define DESC_RATEVHTSS2MCS8 0x3E +#define DESC_RATEVHTSS2MCS9 0x3F +#define DESC_RATEVHTSS3MCS0 0x40 +#define DESC_RATEVHTSS3MCS1 0x41 +#define DESC_RATEVHTSS3MCS2 0x42 +#define DESC_RATEVHTSS3MCS3 0x43 +#define DESC_RATEVHTSS3MCS4 0x44 +#define DESC_RATEVHTSS3MCS5 0x45 +#define DESC_RATEVHTSS3MCS6 0x46 +#define DESC_RATEVHTSS3MCS7 0x47 +#define DESC_RATEVHTSS3MCS8 0x48 +#define DESC_RATEVHTSS3MCS9 0x49 +#define DESC_RATEVHTSS4MCS0 0x4A +#define DESC_RATEVHTSS4MCS1 0x4B +#define DESC_RATEVHTSS4MCS2 0x4C +#define DESC_RATEVHTSS4MCS3 0x4D +#define DESC_RATEVHTSS4MCS4 0x4E +#define DESC_RATEVHTSS4MCS5 0x4F +#define DESC_RATEVHTSS4MCS6 0x50 +#define DESC_RATEVHTSS4MCS7 0x51 +#define DESC_RATEVHTSS4MCS8 0x52 +#define DESC_RATEVHTSS4MCS9 0x53 +#endif +typedef enum _DESC_RATE_{ + // CCK Rates, TxHT = 0 + DESC_RATE1M = 0x00, + DESC_RATE2M = 0x01, + DESC_RATE5_5M = 0x02, + DESC_RATE11M = 0x03, + // OFDM Rates, TxHT = 0 + DESC_RATE6M = 0x04, + DESC_RATE9M = 0x05, + DESC_RATE12M = 0x06, + DESC_RATE18M = 0x07, + DESC_RATE24M = 0x08, + DESC_RATE36M = 0x09, + DESC_RATE48M = 0x0A, + DESC_RATE54M = 0x0B, + // MCS Rates, TxHT = 1 + DESC_RATEMCS0 = 0x0C, + DESC_RATEMCS1 = 0x0D, + DESC_RATEMCS2 = 0x0E, + DESC_RATEMCS3 = 0x0F, + DESC_RATEMCS4 = 0x10, + DESC_RATEMCS5 = 0x11, + DESC_RATEMCS6 = 0x12, + DESC_RATEMCS7 = 0x13, + DESC_RATEMCS8 = 0x14, + DESC_RATEMCS9 = 0x15, + DESC_RATEMCS10 = 0x16, + DESC_RATEMCS11 = 0x17, + DESC_RATEMCS12 = 0x18, + DESC_RATEMCS13 = 0x19, + DESC_RATEMCS14 = 0x1A, + DESC_RATEMCS15 = 0x1B, + DESC_RATEMCS16 = 0x1C, + DESC_RATEMCS17 = 0x1D, + DESC_RATEMCS18 = 0x1E, + DESC_RATEMCS19 = 0x1F, + DESC_RATEMCS20 = 0x20, + DESC_RATEMCS21 = 0x21, + DESC_RATEMCS22 = 0x22, + DESC_RATEMCS23 = 0x23, + DESC_RATEMCS24 = 0x24, + DESC_RATEMCS25 = 0x25, + DESC_RATEMCS26 = 0x26, + DESC_RATEMCS27 = 0x27, + DESC_RATEMCS28 = 0x28, + DESC_RATEMCS29 = 0x29, + DESC_RATEMCS30 = 0x2A, + DESC_RATEMCS31 = 0x2B, + // VHT MCS Rates, + DESC_RATEVHTSS1MCS0 = 0x2C, + DESC_RATEVHTSS1MCS1 = 0x2D, + DESC_RATEVHTSS1MCS2 = 0x2E, + DESC_RATEVHTSS1MCS3 = 0x2F, + DESC_RATEVHTSS1MCS4 = 0x30, + DESC_RATEVHTSS1MCS5 = 0x31, + DESC_RATEVHTSS1MCS6 = 0x32, + DESC_RATEVHTSS1MCS7 = 0x33, + DESC_RATEVHTSS1MCS8 = 0x34, + DESC_RATEVHTSS1MCS9 = 0x35, + DESC_RATEVHTSS2MCS0 = 0x36, + DESC_RATEVHTSS2MCS1 = 0x37, + DESC_RATEVHTSS2MCS2 = 0x38, + DESC_RATEVHTSS2MCS3 = 0x39, + DESC_RATEVHTSS2MCS4 = 0x3A, + DESC_RATEVHTSS2MCS5 = 0x3B, + DESC_RATEVHTSS2MCS6 = 0x3C, + DESC_RATEVHTSS2MCS7 = 0x3D, + DESC_RATEVHTSS2MCS8 = 0x3E, + DESC_RATEVHTSS2MCS9 = 0x3F, + DESC_RATEVHTSS3MCS0 = 0x40, + DESC_RATEVHTSS3MCS1 = 0x41, + DESC_RATEVHTSS3MCS2 = 0x42, + DESC_RATEVHTSS3MCS3 = 0x43, + DESC_RATEVHTSS3MCS4 = 0x44, + DESC_RATEVHTSS3MCS5 = 0x45, + DESC_RATEVHTSS3MCS6 = 0x46, + DESC_RATEVHTSS3MCS7 = 0x47, + DESC_RATEVHTSS3MCS8 = 0x48, + DESC_RATEVHTSS3MCS9 = 0x49, + DESC_RATEVHTSS4MCS0 = 0x4A, + DESC_RATEVHTSS4MCS1 = 0x4B, + DESC_RATEVHTSS4MCS2 = 0x4C, + DESC_RATEVHTSS4MCS3 = 0x4D, + DESC_RATEVHTSS4MCS4 = 0x4E, + DESC_RATEVHTSS4MCS5 = 0x4F, + DESC_RATEVHTSS4MCS6 = 0x50, + DESC_RATEVHTSS4MCS7 = 0x51, + DESC_RATEVHTSS4MCS8 = 0x52, + DESC_RATEVHTSS4MCS9 = 0x53, + DESC_RATEMAX +}DESC_RATE_E, *PDESC_RATE_E; + +#define RX_DRV_INFO_SIZE_UNIT 8 + +#define TX_DESC_SIZE_8192ES 40 +#define TX_DESC_SIZE_8723DS 40 +#define TX_DESC_SIZE_8814AS 40 +#define TX_DESC_SIZE_8812 40 +#define TX_DESC_SIZE_8723B 40 +#define TX_DESC_SIZE_8703B 40 +#define TX_DESC_SIZE_8188F 40 +#define TX_DESC_SIZE 32 +#define TX_DESC_SIZE_8821BS 40 +#define TX_DESC_SIZE_8822BS 48 +#define TX_INFO_SIZE_8822B TX_DESC_SIZE_8822BS + +/*------------------------------ Tx Desc field Macro ----------------------------*/ +//#pragma mark -- Tx Desc field. -- +//---------------------------------------------------------------------------- + +//Early mode +#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) +#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) +#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) +#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) +#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) +#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) +#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) + + +#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16) +#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) + + + +/*------------------------------Tx Desc definition----------------------------*/ +#pragma pack (1) +typedef struct _Phy_CCK_Rx_Status_Report +{ + /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend + 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ + u1Byte adc_pwdb_X[4]; + u1Byte SQ_rpt; + u1Byte cck_agc_rpt; + u1Byte cck_bb_pwr; +}PHY_STS_CCK_T; +#pragma pack () + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Tx Descriptor related function---------------------*/ + +u1Byte +MTxBFPacketTypeToSNDPktSel( + IN u1Byte Type + ); + + +u1Byte +HwRateToMRate( + IN u1Byte rate +); + +u1Byte +MRateToHwRate( + IN u1Byte rate +); + +u1Byte +HwRateToMRate_2( + IN u1Byte rate + ); + +u1Byte +MRateToRateIndex( + IN u1Byte rate + ); + + +u1Byte +QueryIsShort( + IN PADAPTER Adapter, + IN u1Byte TxHT, + IN u1Byte TxRate, + IN PRT_TCB pTcb +); + +u1Byte +MapHwQueueToFirmwareQueue( + IN PRT_TCB pTcb, + IN u1Byte QueueID +); + + + +u1Byte +QueueMapping( + u1Byte QueueID + ); + +#if TX_AGGREGATION +VOID +TxSdioAggregation( + IN PADAPTER Adapter, + IN u1Byte queueId + ); +#endif + + + +/*--------------------------Rx Descriptor related function---------------------*/ + + + +#define RX_HAL_IS_CCK_RATE(_Adapter, _pDesc) \ + IS_HARDWARE_TYPE_8188E(_Adapter) ? RX_HAL_IS_CCK_RATE_88E(_pDesc) : RX_HAL_IS_CCK_RATE_88E(_pDesc) + +#define MAX_RX_PKT_HW_VALID_SIZE(_Adapter) (_Adapter->MAX_RECEIVE_BUFFER_SIZE) + + +u1Byte +QueryRxPwrPercentage( + IN s1Byte AntPower +); + +VOID +UpdateRxSignalStatistics( + IN PADAPTER Adapter, + IN OUT PRT_RFD pRfd +); + +s4Byte +TranslateToDbm( + IN PADAPTER Adapter, + IN u1Byte SignalStrengthIndex // 0-100 index. +); + +u1Byte +GetSignalQuality( + IN PADAPTER Adapter +); + +s4Byte +SignalScaleMapping( + IN PADAPTER Adapter, + IN s4Byte CurrSig +); + +u1Byte +SignalScaleProc( + IN PADAPTER Adapter, + IN s4Byte CurrSig, + IN BOOLEAN Is11n, + IN BOOLEAN IsCCK +); + +VOID +RxDesc_BackupScanList( + IN PADAPTER Adapter +); + +VOID +RxDesc_FlushScanList( + IN PADAPTER Adapter +); + +u1Byte +EVMdbToPercentage( + IN s1Byte Value +); + +VOID +Process_UI_RSSI( + IN PADAPTER Adapter, + IN PRT_RFD pRfd +); + +VOID +Process_PWDB( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN PRT_WLAN_STA pEntry +); + +VOID +Process_UiLinkQuality( + IN PADAPTER Adapter, + IN PRT_RFD pRfd +); + +void +ProcessPhyInfo( + IN PADAPTER Adapter, + IN OCTET_STRING pduOS, + IN PRT_RFD pRfd, + IN PRT_WLAN_STA pEntry +); + +VOID +UpdateRxAMPDUHistogramStatistics( + IN OUT PADAPTER Adapter, + IN PRT_RFD pRfd +); + +VOID +UpdateRxPktTimeStamp( + IN PADAPTER Adapter, + IN OUT PRT_RFD pRfd +); + +VOID +UpdateRxdRateHistogramStatistics( + IN OUT PADAPTER Adapter, + IN PRT_RFD pRfd, + IN u1Byte mgnRate + ); + +VOID +CheckRxPacketValidLength( + IN PADAPTER Adapter, + IN OUT PRT_RFD pRfd + ); + +#endif //__INC_HALCOMDESC_H diff --git a/network/wlan/WDI/HAL/HalComFirmware.h b/network/wlan/WDI/HAL/HalComFirmware.h new file mode 100644 index 00000000..545f1c6c --- /dev/null +++ b/network/wlan/WDI/HAL/HalComFirmware.h @@ -0,0 +1,465 @@ +#ifndef __INC_COMFIRMWARE_H__ +#define __INC_COMFIRMWARE_H__ + +#define PageNum_128(_Len) (u4Byte)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) +#define PageNum_256(_Len) (u4Byte)(((_Len)>>8) + ((_Len)&0xFF ? 1:0)) +#define PageNum_512(_Len) (u4Byte)(((_Len)>>9) + ((_Len)&0x1FF ? 1:0)) + +// +// Check if FW header exists. We do not consider the lower 4 bits in this case. +// By tynli. 2009.12.04. +// Add new FW signature recognized ID 23xx for RTL8723. +// +// Signature header for RLE0380 Test chip: 0x2300, RTL8723A Normal Chip: 0x2301 +// Added by Roger, 2011.07.28. +// +#define IS_FW_HEADER_EXIST(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) & 0xFFF0) == 0x92C0 ||\ + ( GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) & 0xFFF0) == 0x88C0 ||\ + ( GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) & 0xFF00) == 0x2300 ||\ + ( GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) & 0xFF00) == 0x2301 ||\ + ( GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) & 0xFF00) == 0x2302 ||\ + (GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) &0xFFFF) == 0x92D0 ||\ + (GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) &0xFFFF) == 0x92D1 ||\ + (GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) &0xFFFF) == 0x92D2 ||\ + (GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) &0xFFFF) == 0x92D3) + + +#if(FW_QUEME_MECHANISM_NEW != 1) +#define IS_H2CQUEUE_EMPTY(_pHalData) (_pHalData->H2CQueueTail == _pHalData->H2CQueueHead) +#endif + +#define GET_FIRMWARE(_Adapter) ((PRT_FIRMWARE) (((HAL_DATA_TYPE*)(_Adapter->HalData))->pFirmware)) + + +//#define FillH2CCmd(_Adapter, _ElementID, _CmdLen,_pCmdBuffer) \ +// (IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_8723B(_Adapter))?FillH2CCmd8723B(_Adapter, _ElementID, _CmdLen,_pCmdBuffer): \ +// (IS_HARDWARE_TYPE_8192E(_Adapter))?FillH2CCmd8192E(_Adapter, _ElementID, _CmdLen,_pCmdBuffer): \ +// (IS_HARDWARE_TYPE_8188E(_Adapter) ? FillH2CCmd88E(_Adapter, _ElementID, _CmdLen,_pCmdBuffer) : FillH2CCmd92C(_Adapter, _ElementID, _CmdLen,_pCmdBuffer)) + + +#define FW_GTK_EXT_MEM_SIZE 256 // bytes + +// The value is define to check FW 32k calibration status in REG_MCUTST_WOWLAN(0x1c7). +// Modify to new value from 8723BS FW v15. +#define FW_DBG_32K_CALI_TIMEOUT 0xfd +#define FW_DBG_32K_CALI_LOCK 0xfe + +//-------------------------------------------------- +typedef enum _DESC_PACKET_TYPE{ + DESC_PACKET_TYPE_INIT = 0, + DESC_PACKET_TYPE_NORMAL = 1, + DESC_PACKET_TYPE_CMD +}DESC_PACKET_TYPE; + + +#define FW_SIZE 0x40000 // Compatible with RTL8723 Maximal RAM code size 24K. modified to 32k, TO compatible with 92d maximal fw size 32k +#define FW_START_ADDRESS 0x1000 + +#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes + +typedef enum _FIRMWARE_SOURCE{ + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, //from header file +}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; + +typedef struct _RT_FIRMWARE{ + FIRMWARE_SOURCE eFWSource; + u1Byte szFwBuffer[FW_SIZE]; + u4Byte ulFwLength; + u1Byte szWoWLANFwBuffer[FW_SIZE]; + u4Byte ulWoWLANFwLength; + u1Byte szBTFwBuffer[FW_SIZE]; + u4Byte ulBTFwLength; +}RT_FIRMWARE, *PRT_FIRMWARE; + +// +// This structure must be cared byte-ordering +// +// Added by tynli. 2009.12.04. + +//===================================================== +// Firmware Header(8-byte alinment required) +//===================================================== +//--- LONG WORD 0 ---- +#define GET_FIRMWARE_HDR_SIGNATURE(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut +#define GET_FIRMWARE_HDR_CATEGORY(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) // AP/NIC and USB/PCI +#define GET_FIRMWARE_HDR_FUNCTION(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions +#define GET_FIRMWARE_HDR_VERSION(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)// FW Version +#define GET_FIRMWARE_HDR_SUB_VER(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) // FW Subversion, default 0x00 +#define GET_FIRMWARE_HDR_RSVD1(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) + +//--- LONG WORD 1 ---- +#define GET_FIRMWARE_HDR_MONTH(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) // Release time Month field +#define GET_FIRMWARE_HDR_DATE(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) // Release time Date field +#define GET_FIRMWARE_HDR_HOUR(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)// Release time Hour field +#define GET_FIRMWARE_HDR_MINUTE(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)// Release time Minute field +#define GET_FIRMWARE_HDR_ROMCODE_SIZE(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)// The size of RAM code +#define GET_FIRMWARE_HDR_RSVD2(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16) + +//--- LONG WORD 2 ---- +#define GET_FIRMWARE_HDR_SVN_IDX(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)// The SVN entry index +#define GET_FIRMWARE_HDR_RSVD3(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32) + +//--- LONG WORD 3 ---- +#define GET_FIRMWARE_HDR_RSVD4(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32) +#define GET_FIRMWARE_HDR_RSVD5(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32) + +// +// This structure must be cared byte-ordering +// +// Added by ylb 20130814 + +//===================================================== +// New Firmware Header(8-byte alinment required) +//===================================================== +//--- LONG WORD 0 ---- +#define GET_FIRMWARE_HDR_SIGNATURE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) +#define GET_FIRMWARE_HDR_CATEGORY_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) // AP/NIC and USB/PCI +#define GET_FIRMWARE_HDR_FUNCTION_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions +#define GET_FIRMWARE_HDR_VERSION_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)// FW Version +#define GET_FIRMWARE_HDR_SUB_VER_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) // FW Subversion, default 0x00 +#define GET_FIRMWARE_HDR_SUB_IDX_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) // FW Subversion Index + +//--- LONG WORD 1 ---- +#define GET_FIRMWARE_HDR_SVN_IDX_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 32)// The SVN entry index +#define GET_FIRMWARE_HDR_RSVD1_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 32) + +//--- LONG WORD 2 ---- +#define GET_FIRMWARE_HDR_MONTH_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 8) // Release time Month field +#define GET_FIRMWARE_HDR_DATE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 8, 8) // Release time Date field +#define GET_FIRMWARE_HDR_HOUR_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 16, 8)// Release time Hour field +#define GET_FIRMWARE_HDR_MINUTE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 24, 8)// Release time Minute field +#define GET_FIRMWARE_HDR_YEAR_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 16)// Release time Year field +#define GET_FIRMWARE_HDR_FOUNDRY_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 16, 8)// Release time Foundry field +#define GET_FIRMWARE_HDR_RSVD2_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 24, 8) + +//--- LONG WORD 3 ---- +#define GET_FIRMWARE_HDR_MEM_UASGE_DL_FROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 1) +#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_FROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 1, 1) +#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_LOADER_3081(__FwHdr)LE_BITS_TO_4BYTE(__FwHdr+24, 2, 1) +#define GET_FIRMWARE_HDR_MEM_UASGE_IRAM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 3, 1) +#define GET_FIRMWARE_HDR_MEM_UASGE_ERAM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 4, 1) +#define GET_FIRMWARE_HDR_MEM_UASGE_RSVD4_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 5, 3) +#define GET_FIRMWARE_HDR_RSVD3_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 8, 8) +#define GET_FIRMWARE_HDR_BOOT_LOADER_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 16, 16) +#define GET_FIRMWARE_HDR_RSVD5_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32) + +//--- LONG WORD 4 ---- +#define GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 0, 32) +#define GET_FIRMWARE_HDR_FW_CFG_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 0, 16) +#define GET_FIRMWARE_HDR_FW_ATTR_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 16, 16) + +//--- LONG WORD 5 ---- +#define GET_FIRMWARE_HDR_IROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+40, 0, 32) +#define GET_FIRMWARE_HDR_EROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+44, 0, 32) + +//--- LONG WORD 6 ---- +#define GET_FIRMWARE_HDR_IRAM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+48, 0, 32) +#define GET_FIRMWARE_HDR_ERAM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+52, 0, 32) + +//--- LONG WORD 7 ---- +#define GET_FIRMWARE_HDR_RSVD6_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+56, 0, 32) +#define GET_FIRMWARE_HDR_RSVD7_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+60, 0, 32) + + +//===================================================== +// FW H2C / C2H CMD structure +//===================================================== + +#ifdef REMOVE_PACK +#pragma pack(1) +#endif + +//------------------------------------------------------- +// H2C Command length +// The defines should be seperated into 92C series and 88E series ICs +// because of the H2C Box length are different. 2012.04.18. Noted by tynli. +//------------------------------------------------------- + +//----------------------------------------- +// 92C Series +//----------------------------------------- +#define H2C_92C_PWEMODE_LENGTH 5 +#define H2C_92C_JOINBSSRPT_LENGTH 1 +#define H2C_92C_RSVDPAGE_LOC_LEN 5 +#define H2C_92C_RSVDPAGE_LOC_2_LEN 5 +#define H2C_92C_WLANINFO_LENGTH 3 +#define H2C_92C_AP_OFFLOAD_LENGTH 3 +#define H2C_92C_WOWLAN_LENGTH 4 +#define H2C_92C_KEEP_ALIVE_CTRL_LENGTH 3 +#define H2C_92C_BT_FW_PATCH_LEN 3 +#define H2C_92C_BT_RADIO_STATE_LEN 1 +#define H2C_92C_REALWOW_RSVDPAGE_LOC_LENGTH 4 +#if(USE_OLD_WOWLAN_DEBUG_FW == 0) +#define H2C_92C_REMOTE_WAKE_CTRL_LEN 1 +#else +#define H2C_92C_REMOTE_WAKE_CTRL_LEN 3 +#endif +#define H2C_92C_ARP_NDP_OFFLOAD_LENGTH 1 +#define H2C_92C_GTK_OFFLOAD_LENGTH 1 +#define H2C_92C_REMOTE_WAKEUP_SEC_INFO_LEN 3 +#define H2C_92C_FW_PATTERN_RSVDPAGE_LOC_LEN 4 +#define H2C_92C_DISCONNECT_DECISION_CTRL_LEN 3 + +//----------------------------------------- +// 88E Series +//----------------------------------------- +#define H2C_88E_RSVDPAGE_LOC_LEN 5 +#define H2C_88E_PWEMODE_LENGTH 5 +#define H2C_88E_JOINBSSRPT_LENGTH 1 +#define H2C_88E_AP_OFFLOAD_LENGTH 3 +#define H2C_88E_WOWLAN_LENGTH 4 +#define H2C_88E_KEEP_ALIVE_CTRL_LENGTH 3 +#if(USE_OLD_WOWLAN_DEBUG_FW == 0) +#define H2C_88E_REMOTE_WAKE_CTRL_LEN 1 +#else +#define H2C_88E_REMOTE_WAKE_CTRL_LEN 3 +#endif +#define H2C_88E_AOAC_GLOBAL_INFO_LEN 2 +#define H2C_88E_AOAC_RSVDPAGE_LOC_LEN 7 +#define H2C_88E_AOAC_RSVDPAGE2_LOC_LEN 7 +#define H2C_88E_SCAN_OFFLOAD_CTRL_LEN 4 +#define H2C_88E_BT_FW_PATCH_LEN 6 +#define H2C_88E_INACTIVE_PS_LEN 3 +#define H2C_88E_DISCONNECT_DECISION_CTRL_LEN 4 +#define H2C_88E_AOAC_RSVDPAGE3_LOC_LEN 7 + +//----------------------------------------- +// 8723B Series +//----------------------------------------- +#define H2C_8723B_WIFI_CALIBRATION_LEN 1 +#define H2C_8723B_FCS_INFO_LEN 7 +#define H2C_8723B_FCS_MACID_BITMAP_LEN 7 + +//----------------------------------------- +// 8703B Series +//----------------------------------------- +#define H2C_8703B_WIFI_CALIBRATION_LEN 1 + +//----------------------------------------- +// 8188F Series +//----------------------------------------- +#define H2C_8188F_WIFI_CALIBRATION_LEN 1 + + +//----------------------------------------- +// 8812 Series +//----------------------------------------- +#define H2C_8812_RSVDPAGE_FCS_LOC_LEN 3 +#define H2C_8812_FCS_INFO_LEN 7 + +//----------------------------------------- +// 8821 Series +//----------------------------------------- +#define H2C_8821A_RSVDPAGE_FCS_LOC_LEN 3 +#define H2C_8821A_FCS_INFO_LEN 7 +#define H2C_8821A_FCS_MACID_BITMAP_LEN 7 +#define H2C_8821B_FCS_INFO_LEN 7 +#define H2C_8821B_RSVDPAGE_FCS_LOC_LEN 3 + +//----------------------------------------- +// 8192E Series +//----------------------------------------- +#define H2C_8192E_RSVDPAGE_FCS_LOC_LEN 3 +#define H2C_8192E_FCS_INFO_LEN 7 +#define H2C_8192E_FCS_MACID_BITMAP_LEN 7 + +typedef struct _H2C_JOINBSSRPT_PARM{ + u1Byte OpMode; + u1Byte Ps_Qos_Info; + u1Byte Bssid[6]; + u2Byte BcnItv; + u2Byte Aid; +}H2C_JOINBSSRPT_PARM, *PH2C_JOINBSSRPT_PARM; + + +typedef struct _C2H_EVT_HDR{ + u1Byte CmdID: 4; + u1Byte CmdLen: 4; + u1Byte CmdSeq; +}C2H_EVT_HDR, *PC2H_EVT_HDR; + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +typedef struct _H2C_WPA_PTK { + u1Byte kck[16]; /* EAPOL-Key Key Confirmation Key (KCK) */ + u1Byte kek[16]; /* EAPOL-Key Key Encryption Key (KEK) */ + u1Byte tk1[16]; /* Temporal Key 1 (TK1) */ + union { + u1Byte tk2[16]; //Temporal Key 2 (TK2) + struct { + u1Byte tx_mic_key[8]; + u1Byte rx_mic_key[8]; + }Athu; + }U; +}H2C_WPA_PTK; + +// For old Hw security engine. Support on 92C/8723A/88E/8812A, otherwise just use H2C_WPA_PTK structure. +typedef struct _H2C_WPA_TWO_WAY_PARA{ + //algorithm TKIP or AES + u1Byte pairwise_en_alg; + u1Byte group_en_alg; + H2C_WPA_PTK wpa_ptk_value; +#if(USE_OLD_WOWLAN_DEBUG_FW == 1) + u8Byte IV; +#endif +}H2C_WPA_TWO_WAY_PARA, *PH2C_WPA_TWO_WAY_PARA; + +typedef struct _H2C_REMOTE_WAKE_CTRL_INFO{ + u1Byte IV[8]; +}H2C_REMOTE_WAKE_CTRL_INFO, *PH2C_REMOTE_WAKE_CTRL_INFO; + + +typedef struct _NDP_INFO_{ + u1Byte bEnable:1; + u1Byte bCheckRemoveIP:1; // Need to Check Sender IP or not + u1Byte Rsvd:6; // Need to Check Sender IP or not + u1Byte NumberOfTargetIP; // Number of Check IP which NA query IP + u1Byte TagetLinkAddress[6]; // Maybe support change MAC address !! + u1Byte RemoteIPv6Address[16]; // Just respond IP + u1Byte TargetIP[2][16]; // target IP +}NDP_INFO,*PNDP_INFO; + + +typedef struct _H2C_PROTOCOL_OFFLOAD_INFO{ + NDP_INFO NDPInfo[2]; +} H2C_PROTOCOL_OFFLOAD_INFO, *PH2C_PROTOCOL_OFFLOAD_INFO; + + + +#ifdef REMOVE_PACK +#pragma pack(1) +#endif + +typedef struct _HAL92C_P2P_PS_OFFLOAD +{ + u1Byte Offload_En:1; + u1Byte role:1; // 1: Owner, 0: Client + u1Byte CTWindow_En:1; + u1Byte NoA0_En:1; + u1Byte NoA1_En:1; + u1Byte AllStaSleep:1; + u1Byte discovery:1; +}HAL92C_P2P_PS_OFFLOAD, *PHAL92C_P2P_PS_OFFLOAD; + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +typedef struct _H2C_SS_DRV_CTRL{ + u1Byte ChnlListLen; // scan channel list length + u1Byte OriginalChl; // current client channel + u1Byte OriginalBW; // current client BW 20M/40M/80M + u1Byte Originalch40offset; // 40M second channel offset + u1Byte Originalch80offset; // 80M second channel offset + u1Byte bPriodScan; // Fw periodically scan. + u1Byte PriodScanTime; // Fw periodical scan time. unit: 1sec. + u1Byte bRFEEnable; // for 8812A switch band + u1Byte RFEType; + u1Byte Rsvd[7]; +}H2C_SS_DRV_CTRL, *PH2C_SS_DRV_CTRL; + + +typedef struct _H2C_NLO_HEADER_INFO{ + u1Byte NumOfEntry; + u1Byte Rsvd1[3]; + u1Byte FastScanPeriod[4]; + u1Byte FastScanIterations[4]; + u1Byte SlowScanPeriod[4]; + u1Byte SsidLen[16]; + u1Byte Cipher[16]; + u1Byte ChannelList[16]; +}H2C_NLO_HEADER_INFO, *PH2C_NLO_HEADER_INFO; + + +#define H2C_MAC_MODE_SEL 9 + +//#define MAX_RSVD_PAGE_BUF_LEN (128*9) // page size * the rsvd page packet number in Tx pkt buf + +// Description: Determine the types of C2H events that are the same in driver and Fw. +// Fisrt constructed by tynli. 2009.10.09. +typedef enum _RTL8192C_C2H_EVT +{ + C2H_DBG = 0, + C2H_TSF = 1, + C2H_AP_RPT_RSP = 2, + C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet. + C2H_BT_RSSI = 4, + C2H_BT_OP_MODE = 5, + C2H_EXT_RA_RPT = 6, + C2H_HW_INFO_EXCH = 10, + C2H_C2H_H2C_TEST = 11, + C2H_BT_INFO = 12, + C2H_BT_MP = 15, + MAX_C2HEVENT +}RTL8192C_C2H_EVT; + +typedef enum _FW_SCAN_OFFLOAD_TYPE{ + FW_SCAN_OFFLOAD_D0 = 0, + FW_SCAN_OFFLOAD_D3 = 1, +}FW_SCAN_OFFLOAD_TYPE; + +//========================================================== +//---------------------------------------------------------------------- +// Fw Initial Offload command +//---------------------------------------------------------------------- +#define INIT_OFFLOAD_ACTION_LLT BIT0 +#define INIT_OFFLOAD_ACTION_R_EFUSE BIT1 +#define INIT_OFFLOAD_ACTION_EFUSE_PATCH BIT2 + +typedef enum _INIT_OFFLOAD_CMD{ + INIT_OFFLOAD_CMD_LLT = 0x01, + INIT_OFFLOAD_CMD_R_EFUSE = 0x02, + INIT_OFFLOAD_CMD_EFUSE_PATCH = 0x03, + INIT_OFFLOAD_CMD_WB_REG = 0x04, + INIT_OFFLOAD_CMD_WW_REG = 0x05, + INIT_OFFLOAD_CMD_WD_REG = 0x06, + INIT_OFFLOAD_CMD_W_RF = 0x07, + INIT_OFFLOAD_CMD_DELAY_US = 0x10, + INIT_OFFLOAD_CMD_DELAY_MS = 0x11, + INIT_OFFLOAD_CMD_END = 0xff, +}INIT_OFFLOAD_CMD, *PINIT_OFFLOAD_CMD; + +//---------------------------------------------------------------------- +// Fw wake up reason code +//---------------------------------------------------------------------- +// V1 is for 88C and 8723A. +typedef enum _FW_WOW_REASON_V1{ + FW_WOW_V1_PTK_UPDATE_EVENT = 0x01, + FW_WOW_V1_GTK_UPDATE_EVENT = 0x02, + FW_WOW_V1_DISASSOC_EVENT = 0x04, + FW_WOW_V1_DEAUTH_EVENT = 0x08, + FW_WOW_V1_FW_DISCONNECT_EVENT = 0x10, + FW_WOW_V1_HW_WAKE_PKT_EVENT = 0x20, + FW_WOW_V1_APPL_QQ = 0x21, //Application + FW_WOW_V1_FWPATTERNMATCH0 = 0x40, + FW_WOW_V1_FWPATTERNMATCH1 = 0x41, + FW_WOW_V1_FWPATTERNMATCH2 = 0x42, + FW_WOW_V1_FWPATTERNMATCH3 = 0x43, + FW_WOW_V1_ONWAKEUPPKT = 0x80, // 128 + FW_WOW_V1_RSPKTTIMEOUT = 0x81, // 129 + FW_WOW_V1_DHCPTIMEOUT = 0x82, // 130 + FW_WOW_V1_NLMATCH = 0x83, // 131 + FW_WOW_V1_REASON_MAX = 0xff, +}FW_WOW_REASON_V1, *PFW_WOW_REASON_V1; + +// After 8188E, we use V2 reason define. 88C/8723A use V1 reason. +typedef enum _FW_WOW_REASON_V2{ + FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, + FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, + FW_WOW_V2_DISASSOC_EVENT = 0x04, + FW_WOW_V2_DEAUTH_EVENT = 0x08, + FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, + FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, + FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, + FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, + FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, + FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, + FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, + FW_WOW_V2_NLO_SSID_MATCH_EVENT = 0x55, + FW_WOW_V2_REASON_MAX = 0xff, +}FW_WOW_REASON, *PFW_WOW_REASON; + +#endif diff --git a/network/wlan/WDI/HAL/HalComLed.h b/network/wlan/WDI/HAL/HalComLed.h new file mode 100644 index 00000000..eaee5e77 --- /dev/null +++ b/network/wlan/WDI/HAL/HalComLed.h @@ -0,0 +1,284 @@ +#ifndef __INC_HALCOMLED_H +#define __INC_HALCOMLED_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalComLed.h + +Abstract: + LED related data structure and interface to manipulate LED. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-12-23 Isaiah Create. + +--*/ + +//================================================================================ +// LED Behavior Constant. +//================================================================================ +// Default LED behavior. +// +#define LED_BLINK_NORMAL_INTERVAL 100 +#define LED_BLINK_SLOWLY_INTERVAL 200 + +#define LED_BLINK_LONG_INTERVAL 400 +#define LED_INITIAL_INTERVAL 1800 + + +// LED Customerization + +//NETTRONIX +#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100 +#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000 + +//PORNET +#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000 +#define LED_BLINK_NORMAL_INTERVAL_PORNET 100 +#define LED_BLINK_FAST_INTERVAL_BITLAND 30 + +//AzWave. +#define LED_CM2_BLINK_ON_INTERVAL 250 +#define LED_CM2_BLINK_OFF_INTERVAL 4750 +#define LED_CM8_BLINK_OFF_INTERVAL 3750 //for QMI + +//RunTop +#define LED_RunTop_BLINK_INTERVAL 300 + +//ALPHA +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 //add by ylb 20121012 for customer led for alpha +#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500 +#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150 +#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 +#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 + +// 111122 by hpfan: Customized for Xavi +#define LED_CM11_BLINK_INTERVAL 300 +#define LED_CM11_LINK_ON_INTERVEL 3000 + +//Netgear +#define LED_BLINK_LINK_INTERVAL_NETGEAR 500 +#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR 1000 + +#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR 100 +#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR 500 + + +//Belkin AC950 +#define LED_BLINK_LINK_INTERVAL_ON_BELKIN 200 +#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN 100 +#define LED_BLINK_ERROR_INTERVAL_BELKIN 100 + +//by chiyokolin for Azurewave +#define LED_CM12_BLINK_INTERVAL_5Mbps 160 +#define LED_CM12_BLINK_INTERVAL_10Mbps 80 +#define LED_CM12_BLINK_INTERVAL_20Mbps 50 +#define LED_CM12_BLINK_INTERVAL_40Mbps 40 +#define LED_CM12_BLINK_INTERVAL_80Mbps 30 +#define LED_CM12_BLINK_INTERVAL_MAXMbps 25 + +//ECS +#define LED_BLINK_INTERVAL_OVER_2Mbps 500 +#define LED_BLINK_INTERVAL_OVER_1Mbps 1000 + +//Dlink +#define LED_BLINK_NO_LINK_INTERVAL 1000 +#define LED_BLINK_LINK_IDEL_INTERVAL 100 + +#define LED_BLINK_SCAN_ON_INTERVAL 30 +#define LED_BLINK_SCAN_OFF_INTERVAL 300 + +#define LED_WPS_BLINK_ON_INTERVAL_DLINK 30 +#define LED_WPS_BLINK_OFF_INTERVAL_DLINK 300 +#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK 5000 + +//Mitac +#define LED_BLINK_TRX_INYERVAL_MITAC 500 +#define LED_BLINK_ON_OFF_INYERVAL_MITAC 100 + +//ELECOM +#define LED_BLINK_WPS_INTERVAL_ELECOM 500 +#define LED_BLINK_TRX_INTERVAL_ELECOM 100 + + + + +//================================================================================ +// LED object. +//================================================================================ + +typedef enum _LED_STATE{ + LED_UNKNOWN = 0, + LED_ON = 1, + LED_OFF = 2, + LED_BLINK_NORMAL = 3, + LED_BLINK_SLOWLY = 4, + LED_POWER_ON_BLINK = 5, + LED_SCAN_BLINK = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning. + LED_NO_LINK_BLINK = 7, // LED is blinking during no link state. + LED_BLINK_StartToBlink = 8, // Customzied for Sercomm Printer Server case + LED_BLINK_TXRX = 9, + LED_BLINK_WPS = 10, // LED is blinkg during WPS communication + LED_BLINK_WPS_STOP = 11, //for ALPHA + LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN + LED_BLINK_RUNTOP = 13, // Customized for RunTop + LED_BLINK_CAMEO = 14, + LED_BLINK_XAVI = 15, + LED_BLINK_ALWAYS_ON = 16, + LED_BLINK_LINK_IN_PROCESS = 17, //Customized for Belkin AC950 + LED_BLINK_AUTH_ERROR = 18, //Customized for Belkin AC950 + LED_BLINK_Azurewave_5Mbps = 19, + LED_BLINK_Azurewave_10Mbps = 20, + LED_BLINK_Azurewave_20Mbps = 21, + LED_BLINK_Azurewave_40Mbps = 22, + LED_BLINK_Azurewave_80Mbps = 23, + LED_BLINK_Azurewave_MAXMbps = 24, + LED_BLINK_LINK_IDEL = 25, + LED_BLINK_WPS_LINKED = 26, + LED_BLINK_TIME_BY_REG = 27, + LED_BLINK_ECS_Below_1Mbps = 28, + LED_BLINK_ECS_Over_1Mbps = 29, + LED_BLINK_ECS_Over_2Mbps = 30, +}LED_STATE; + +typedef enum _LED_PIN{ + LED_PIN_GPIO0, + LED_PIN_LED0, + LED_PIN_LED1, + LED_PIN_LED2, + LED_PIN_LED3, + LED_PIN_LED_ALL +}LED_PIN; + + + + + +//================================================================================ +// SDIO LED Definition. +//================================================================================ + + +#define IS_LED_WPS_BLINKING(_LED_SDIO) (((PLED_SDIO)_LED_SDIO)->CurrLedState==LED_BLINK_WPS \ + || ((PLED_SDIO)_LED_SDIO)->CurrLedState==LED_BLINK_WPS_STOP \ + || ((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress) + +#define IS_LED_BLINKING(_LED_SDIO) (((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress \ + ||((PLED_SDIO)_LED_SDIO)->bLedScanBlinkInProgress) + + +typedef enum _LED_STRATEGY_SDIO{ + SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. + SW_LED_MODE1, // 2 LEDs, through LED0 and LED1. For ALPHA. + SW_LED_MODE2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. + SW_LED_MODE3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. + SW_LED_MODE4, //for Edimax / Belkin + SW_LED_MODE5, //for Sercomm / Belkin + SW_LED_MODE6, //for 88CU minicard, porting from ce SW_LED_MODE7 + SW_LED_MODE7, //for ECS + HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) +}LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO; + +typedef struct _LED_SDIO{ + PVOID pAdapter; + + LED_PIN LedPin; // Identify how to implement this SW led. + + LED_STATE CurrLedState; // Current LED state. + BOOLEAN bLedOn; // TRUE if LED is ON, FALSE if LED is OFF. + + BOOLEAN bSWLedCtrl; + + BOOLEAN bLedBlinkInProgress; // TRUE if it is blinking, FALSE o.w.. + // ALPHA, added by chiyoko, 20090106 + BOOLEAN bLedNoLinkBlinkInProgress; + BOOLEAN bLedLinkBlinkInProgress; + BOOLEAN bLedStartToLinkBlinkInProgress; + BOOLEAN bLedScanBlinkInProgress; + BOOLEAN bLedWPSBlinkInProgress; + + u4Byte BlinkTimes; // Number of times to toggle led state for blinking. + LED_STATE BlinkingLedState; // Next state for blinking, either LED_ON or LED_OFF are. + + RT_TIMER BlinkTimer; // Timer object for led blinking. + RT_WORK_ITEM BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED. +} LED_SDIO, *PLED_SDIO; + +VOID +LedControlSDIO( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction + ); + + +//================================================================================ +// Interface to manipulate LED objects. +//================================================================================ + +#define SwLedOn(_Adapter, _pLed) \ + if(IS_HARDWARE_TYPE_8814A(_Adapter)) \ + SwLedOn_8814A(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_JAGUAR(_Adapter)) \ + IS_HARDWARE_TYPE_8821(_Adapter) ? SwLedOn_8821A(_Adapter, _pLed) : SwLedOn_8812A(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8723B(_Adapter)||IS_HARDWARE_TYPE_8192E(_Adapter)) \ + IS_HARDWARE_TYPE_8192E(_Adapter) ? SwLedOn_8192E(_Adapter, _pLed) : SwLedOn_8723B(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8821B(_Adapter)) \ + SwLedOn_8821B(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8822B(_Adapter)) \ + SwLedOn_8822B(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8703B(_Adapter)) \ + SwLedOn_8703B(_Adapter,_pLed); \ + else if(IS_HARDWARE_TYPE_8188F(_Adapter)) \ + SwLedOn_8188F(_Adapter,_pLed); \ + else if(IS_HARDWARE_TYPE_8723D(_Adapter)) \ + SwLedOn_8723D(_Adapter,_pLed); \ + else \ + IS_HARDWARE_TYPE_8188E(_Adapter) ? SwLedOn_8188E(_Adapter, _pLed) : SwLedOn_Dummy(_Adapter, _pLed) + +#define SwLedOff(_Adapter, _pLed) \ + if(IS_HARDWARE_TYPE_8814A(_Adapter)) \ + SwLedOff_8814A(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_JAGUAR(_Adapter)) \ + IS_HARDWARE_TYPE_8821(_Adapter) ? SwLedOff_8821A(_Adapter, _pLed) : SwLedOff_8812A(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8723B(_Adapter)||IS_HARDWARE_TYPE_8192E(_Adapter)) \ + IS_HARDWARE_TYPE_8192E(_Adapter) ? SwLedOff_8192E(_Adapter, _pLed) : SwLedOff_8723B(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8821B(_Adapter)) \ + SwLedOff_8821B(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8822B(_Adapter)) \ + SwLedOff_8822B(_Adapter, _pLed); \ + else if(IS_HARDWARE_TYPE_8703B(_Adapter)) \ + SwLedOff_8703B(_Adapter,_pLed); \ + else if(IS_HARDWARE_TYPE_8188F(_Adapter)) \ + SwLedOff_8188F(_Adapter,_pLed); \ + else if(IS_HARDWARE_TYPE_8723D(_Adapter)) \ + SwLedOff_8723D(_Adapter,_pLed); \ + else \ + IS_HARDWARE_TYPE_8188E(_Adapter) ? SwLedOff_8188E(_Adapter, _pLed) : SwLedOff_Dummy(_Adapter, _pLed) + + +VOID +InitSwLeds( + IN PADAPTER Adapter + ); + +VOID +DeInitSwLeds( + IN PADAPTER Adapter + ); + +VOID +SwLedOn_Dummy( + IN PADAPTER Adapter, + IN PVOID pLed + ); + +VOID +SwLedOff_Dummy( + IN PADAPTER Adapter, + IN PVOID pLed + ); + +#endif /*__INC_HALCOMLED_H*/ diff --git a/network/wlan/WDI/HAL/HalComPhyCfg.h b/network/wlan/WDI/HAL/HalComPhyCfg.h new file mode 100644 index 00000000..0af6b8d5 --- /dev/null +++ b/network/wlan/WDI/HAL/HalComPhyCfg.h @@ -0,0 +1,341 @@ +/***************************************************************************** + * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HALCOMPHYCFG_H + * + * + * Note: + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * + *****************************************************************************/ + /* Check to see if the file has been included already. */ +#ifndef __INC_HALCOMPHYCFG_H +#define __INC_HALCOMPHYCFG_H + + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskLowNibble 0xf +#define bMaskHighNibble 0xf0 +#define bMaskByte2HighNibble 0x00f00000 +#define bMaskByte3LowNibble 0x0f000000 +#define bMaskL3Bytes 0x00ffffff +#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMask12Bits 0xfff +#define bMask7bits 0x7f +#define bMaskH4Bits 0xf0000000 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f + +#define bRFRegOffsetMask 0xfffff + + +typedef enum _RATE_SECTION { + CCK = 0, + OFDM, + HT_MCS0_MCS7, + HT_MCS8_MCS15, + HT_MCS16_MCS23, + HT_MCS24_MCS31, + VHT_1SSMCS0_1SSMCS9, + VHT_2SSMCS0_2SSMCS9, + VHT_3SSMCS0_3SSMCS9, + VHT_4SSMCS0_4SSMCS9, +} RATE_SECTION; + +typedef enum _RF_TX_NUM { + RF_1TX = 0, + RF_2TX, + RF_3TX, + RF_4TX, + RF_MAX_TX_NUM, + RF_TX_NUM_NONIMPLEMENT, +} RF_TX_NUM; + +/*--------------------------Define Parameters-------------------------------*/ + +#define MAX_DOZE_WAITING_TIMES_9x 64 + +#define MAX_TXPWR_IDX_NMODE 63 + +#define HP_THERMAL_NUM 8 + + + +/* Channel switch:The size of command tables for switch channel*/ +#define MAX_PRECMD_CNT 16 +#define MAX_RFDEPENDCMD_CNT 16 +#define MAX_POSTCMD_CNT 16 + + +// Tx Power Limit Table Size +#define MAX_REGULATION_NUM 4 +#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 +#define MAX_2_4G_BANDWITH_NUM 2 +#define MAX_RATE_SECTION_NUM 10 +#define MAX_5G_BANDWITH_NUM 4 +#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1, OFDM:1, HT:4, VHT:4 +#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4 + +/*------------------------------Define structure----------------------------*/ +typedef struct _BB_REGISTER_DEFINITION{ + u4Byte rfintfs; // set software control: + // 0x870~0x877[8 bytes] + + u4Byte rfintfo; // output data: + // 0x860~0x86f [16 bytes] + + u4Byte rfintfe; // output enable: + // 0x860~0x86f [16 bytes] + + u4Byte rf3wireOffset; // LSSI data: + // 0x840~0x84f [16 bytes] + + u4Byte rfHSSIPara2; // wire parameter control2 : + // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] + + u4Byte rfLSSIReadBack; //LSSI RF readback data SI mode + // 0x8a0~0x8af [16 bytes] + + u4Byte rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B + +}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; + +// +// <Roger_TODO> We should take RTL8723B into consideration, 2012.10.08 +// +#define phy_BB_Config_ParaFile(_Adapter) \ + (IS_HARDWARE_TYPE_8821B(_Adapter))?phy_BB8821B_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8814A(_Adapter))?phy_BB8814A_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8812A(_Adapter))?phy_BB8812A_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8821(_Adapter))?phy_BB8821A_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8723B(_Adapter))?phy_BB8723B_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8723D(_Adapter))?phy_BB8723D_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8703B(_Adapter))?phy_BB8703B_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8188F(_Adapter))?phy_BB8188F_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8188E(_Adapter)? phy_BB8188E_Config_ParaFile(_Adapter) :\ + (IS_HARDWARE_TYPE_8822B(_Adapter))?PHY_BB8822B_Config_ParaFile(_Adapter):\ + (IS_HARDWARE_TYPE_8192E(_Adapter)?phy_BB8192E_Config_ParaFile(_Adapter):\ + phy_BB8723B_Config_ParaFile(_Adapter))) + +#define PHY_GetTxPowerIndex( pAdapter, RFPath, Rate, BandWidth, Channel ) \ + (IS_HARDWARE_TYPE_8814A(pAdapter)) ? PHY_GetTxPowerIndex_8814A( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8821B(pAdapter)) ? PHY_GetTxPowerIndex_8821B( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8822B(pAdapter)) ? PHY_GetTxPowerIndex_8822B( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8812A(pAdapter)) ? PHY_GetTxPowerIndex_8812A( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8821A(pAdapter)) ? PHY_GetTxPowerIndex_8821A( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8723B(pAdapter)) ? PHY_GetTxPowerIndex_8723B( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8703B(pAdapter)) ? PHY_GetTxPowerIndex_8703B( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8188F(pAdapter)) ? PHY_GetTxPowerIndex_8188F( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8192E(pAdapter)) ? PHY_GetTxPowerIndex_8192E( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8723D(pAdapter)) ? PHY_GetTxPowerIndex_8723D( pAdapter, RFPath, Rate, BandWidth, Channel ):\ + (IS_HARDWARE_TYPE_8188E(pAdapter)) ? PHY_GetTxPowerIndex_8188E( pAdapter, RFPath, Rate, BandWidth, Channel ):0\ + +#define PHY_SetTxPowerIndex( pAdapter, PowerIndex, RFPath, Rate ) \ + do { \ + PHY_SetTxPowerIndexShadow( pAdapter, PowerIndex, RFPath, Rate );\ + if (IS_HARDWARE_TYPE_8814A(pAdapter)) PHY_SetTxPowerIndex_8814A( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8821B(pAdapter)) PHY_SetTxPowerIndex_8821B( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8822B(pAdapter)) PHY_SetTxPowerIndex_8822B( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8812A(pAdapter)) PHY_SetTxPowerIndex_8812A( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8821A(pAdapter)) PHY_SetTxPowerIndex_8821A( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8723B(pAdapter)) PHY_SetTxPowerIndex_8723B( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8703B(pAdapter)) PHY_SetTxPowerIndex_8703B( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8188F(pAdapter)) PHY_SetTxPowerIndex_8188F( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8192E(pAdapter)) PHY_SetTxPowerIndex_8192E( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8723D(pAdapter)) PHY_SetTxPowerIndex_8723D( pAdapter, PowerIndex, RFPath, Rate );\ + else if (IS_HARDWARE_TYPE_8188E(pAdapter)) PHY_SetTxPowerIndex_8188E( pAdapter, PowerIndex, RFPath, Rate );\ + }while(0) + +//---------------------------------------------------------------------- +// Initial MAC/BB/RF config by reading MAC/BB/RF txt. +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// Initial MAC/BB/RF config by reading Hard Code. +//---------------------------------------------------------------------- + +RT_STATUS +phy_ConfigBBWithHeaderFile( + IN PADAPTER Adapter, + IN u1Byte ConfigType +); + +RT_STATUS +PHY_ConfigRFWithHeaderFile( + IN PADAPTER Adapter, + IN RF_CONTENT Content, + IN u1Byte eRFPath +); + + +RT_STATUS +phy_ConfigBBWithPgParaFile( + IN PADAPTER Adapter, + IN ps1Byte pFileName +); + +RT_STATUS +PHY_ConfigRFWithPowerLimitTableParaFile( + IN PADAPTER Adapter, + IN ps1Byte pFileName +); + +RT_STATUS +PHY_ConfigRFWithCustomPowerLimitTableParaFile( + IN PADAPTER Adapter, + IN pu1Byte pFileName, + IN BOOLEAN checkInit +); + +RT_STATUS +PHY_ConfigBBWithCustomPgParaFile( + IN PADAPTER Adapter, + IN pu1Byte pFileName, + IN BOOLEAN checkInit +); + + + + +//---------------------------------------------------------------------- +// Initial MAC/BB config from File or Hard Code. +//---------------------------------------------------------------------- +RT_STATUS +PHY_MACConfig( + IN PADAPTER Adapter +); + +RT_STATUS +PHY_BBConfig( + IN PADAPTER Adapter +); + +//---------------------------------------------------------------------- +s4Byte +phy_TxPwrIdxToDbm( + IN PADAPTER Adapter, + IN WIRELESS_MODE WirelessMode, + IN u1Byte TxPwrIdx + ); + + +u1Byte +PHY_DbmToTxPwrIdx( + IN PADAPTER Adapter, + IN WIRELESS_MODE WirelessMode, + IN s4Byte PowerInDbm + ); + +RT_CHANNEL_DOMAIN +PHY_MapChannelPlan( + IN PADAPTER Adapter, + IN u2Byte HalChannelPlan + ); + +void +SINGLEMODULE_MAPFUN( + IN PADAPTER Adapter, + IN u2Byte Regchannelplane, + IN u1Byte RegEnableAdaptivity, + IN u2Byte RegHTMode + ); + +VOID +PHY_MapChnlPlanRegulatory( + IN PADAPTER Adapter + ); + +VOID +PHY_IQCalibrate( + IN PADAPTER Adapter, + IN BOOLEAN bReCovery + ); + + +VOID +PHY_SetTxPowerIndexShadow( + IN PADAPTER Adapter, + IN u4Byte PowerIndex, + IN u1Byte RFPath, + IN u1Byte Rate + ); + +u1Byte +PHY_GetTxPowerIndexShadow( + IN PADAPTER Adapter, + IN u1Byte RFPath, + IN u1Byte Rate + ); + +VOID +PHY_LCCalibrate_Dummy( + IN PDM_ODM_T pDM_Odm + ); + +#define PHY_LCCalibrate(pDM_Odm) \ + (pDM_Odm->SupportICType == ODM_RTL8723B) ? PHY_LCCalibrate_8723B(pDM_Odm) :\ + PHY_LCCalibrate_Dummy(pDM_Odm) + +#define PHY_SetRFPathSwitch(_Adapter,_bMain) \ + (IS_HARDWARE_TYPE_8814A(_Adapter)) ? PHY_SetRFPathSwitch_8814A(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8821B(_Adapter)) ? PHY_SetRFPathSwitch_8821B(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8822B(_Adapter)) ? PHY_SetRFPathSwitch_8822B(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8723B(_Adapter)) ? PHY_SetRFPathSwitch_8723B(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8703B(_Adapter)) ? PHY_SetRFPathSwitch_8703B(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8723D(_Adapter)) ? PHY_SetRFPathSwitch_8723D(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8192E(_Adapter)) ? PHY_SetRFPathSwitch_8192E(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_JAGUAR(_Adapter)) ? PHY_SetRFPathSwitch_8812A(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8188E(_Adapter)) ? PHY_SetRFPathSwitch_8188E(_Adapter,_bMain) :\ + (IS_HARDWARE_TYPE_8188F(_Adapter)) ? PHY_SetRFPathSwitch_8188F(_Adapter,_bMain) : 0 + +#define PHY_QueryRFPathSwitch(_Adapter) \ + (IS_HARDWARE_TYPE_8814A(_Adapter)) ? PHY_QueryRFPathSwitch_8814A(_Adapter) :\ + (IS_HARDWARE_TYPE_8821B(_Adapter)) ? PHY_QueryRFPathSwitch_8821B(_Adapter) :\ + (IS_HARDWARE_TYPE_8822B(_Adapter)) ? PHY_QueryRFPathSwitch_8822B(_Adapter) :\ + (IS_HARDWARE_TYPE_8723B(_Adapter)) ? PHY_QueryRFPathSwitch_8723B(_Adapter) :\ + (IS_HARDWARE_TYPE_8723D(_Adapter)) ? PHY_QueryRFPathSwitch_8723D(_Adapter) :\ + (IS_HARDWARE_TYPE_8703B(_Adapter)) ? PHY_QueryRFPathSwitch_8703B(_Adapter) :\ + (IS_HARDWARE_TYPE_8192E(_Adapter)) ? PHY_QueryRFPathSwitch_8192E(_Adapter) :\ + (IS_HARDWARE_TYPE_8812A(_Adapter)) ? PHY_QueryRFPathSwitch_8812(_Adapter) :\ + (IS_HARDWARE_TYPE_8821A(_Adapter)) ? PHY_QueryRFPathSwitch_8821A(_Adapter) :\ + (IS_HARDWARE_TYPE_8188E(_Adapter)) ? PHY_QueryRFPathSwitch_8188E(_Adapter) :\ + (IS_HARDWARE_TYPE_8188F(_Adapter)) ? PHY_QueryRFPathSwitch_8188F(_Adapter): 0 + + +typedef struct __RT_SINGLEMODULE_ENTRY +{ + u4Byte country_code; + u2Byte Regchannelplane; + u1Byte RegEnableAdaptivity; + u2Byte RegHTMode; + + void (*Func)( // The handler function + IN PADAPTER pAdapter, + IN u2Byte Regchannelplane, + IN u1Byte RegEnableAdaptivity, + IN u2Byte RegHTMode + ); + +}RT_SINGLEMODULE_ENTRY; + +extern RT_SINGLEMODULE_ENTRY RT_SUPPORT_COUNTRY[]; +extern u4Byte GLNumOfSupportCountry; +/*--------------------------Exported Function prototype---------------------*/ + +#endif // __INC_HALCOMPHYCFG_H + diff --git a/network/wlan/WDI/HAL/HalComReg.h b/network/wlan/WDI/HAL/HalComReg.h new file mode 100644 index 00000000..64577a97 --- /dev/null +++ b/network/wlan/WDI/HAL/HalComReg.h @@ -0,0 +1,1705 @@ +/***************************************************************************** + * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HALCOMREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * 2. CCX register + * 3. Backward compatible register with useless address. + * 4. Define 92CU required register address and definition. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HALCOMREG_H +#define __INC_HALCOMREG_H + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +//============================================================ +// 8192C Regsiter offset definition +//============================================================ + +#define HAL_92C_NAV_UPPER_UNIT 128 // micro-second + + +// 8188E PKT_BUFF_ACCESS_CTRL value +#define TXPKT_BUF_SELECT 0x69 +#define RXPKT_BUF_SELECT 0xA5 +#define DISABLE_TRXPKT_BUF_ACCESS 0x0 + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_APS_FSMCO 0x0004 +#define REG_SYS_CLKR 0x0008 +#define REG_9346CR 0x000A +#define REG_EE_VPD 0x000C +#define REG_AFE_MISC 0x0010 +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS0_CTRL_6 0x0016 +#define REG_POWER_OFF_IN_PROCESS 0x0017 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_RSV_CTRL 0x001C +#define REG_RF_CTRL 0x001F +#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOV12D_CTRL 0x0021 +#define REG_LDOHCI12_CTRL 0x0022 +#define REG_LPLDO_CTRL 0x0023 +#define REG_AFE_XTAL_CTRL 0x0024 +//#define REG_AFE_LDO_CTRL 0x0027 // 1.5v for 8188EE test chip, 1.4v for MP chip +#define REG_AFE_PLL_CTRL 0x0028 +#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define REG_PWR_DATA 0x0038 +#define REG_CAL_TIMER 0x003C +#define REG_ACLK_MON 0x003E +#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define REG_LEDCFG0 0x004C +#define REG_LEDCFG1 0x004D +#define REG_LEDCFG2 0x004E +#define REG_LEDCFG3 0x004F +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. +#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. +#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. +#define REG_GPIO_OUTPUT 0x006c +#define REG_AFE_XTAL_CTRL_EXT 0x0078 //RTL8188E +#define REG_XCK_OUT_CTRL 0x007c //RTL8188E +#define REG_MCUFWDL 0x0080 +#define REG_WOL_EVENT 0x0081 //RTL8192C, RTL8723A +#define REG_MCUTSTCFG 0x0084 +#define REG_HMEBOX_EXT_0 0x0088 +#define REG_FW_DBG_STATUS 0x0088 // Support on 8723B/8192E/8812A/8821A +#define REG_HMEBOX_EXT_1 0x008A +#define REG_HMEBOX_EXT_2 0x008C +#define REG_HMEBOX_EXT_3 0x008E +#define REG_HOST_SUSP_CNT 0x00BC // RTL8192C Host suspend counter on FPGA platform +#define REG_SYSTEM_ON_CTRL 0x00CC // For 8723AE Reset after S3 +#define REG_HIMR_88E 0x00B0 //RTL8188E +#define REG_HISR_88E 0x00B4 //RTL8188E +#define REG_HISR0 0x00B4 +#define REG_HIMRE_88E 0x00B8 //RTL8188E +#define REG_HISRE_88E 0x00BC //RTL8188E +#define REG_PMC_DBG_CTRL2 0x00CC +#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 +#define REG_BIST_SCAN 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_BIST_ROM_RPT 0x00D8 +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_HPON_FSM 0x00EC +#define REG_SYS_CFG 0x00F0 +#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. +#define REG_TYPE_ID 0x00FC + +// +// 2010/12/29 MH Add for 92D +// +#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 + +#define REG_MAC0 0x0081 +#define REG_MAC1 0x0053 +#define FW_MAC0_ready 0x18 +#define FW_MAC1_ready 0x1A +#define MAC0_ON BIT7 +#define MAC1_ON BIT0 +#define mac0_ready BIT0 +#define mac1_ready BIT0 + + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR 0x0100 +#define REG_PBP 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_TRXDMA_CTRL 0x010C +#define REG_TRXFF_BNDY 0x0114 +#define REG_TRXFF_STATUS 0x0118 +#define REG_RXFF_PTR 0x011C +#define REG_HIMR 0x0120 +#define REG_HISR 0x0124 +#define REG_HIMRE 0x0128 +#define REG_HISRE 0x012C +//#define REG_CPWM 0x012F +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_FTISR 0x013C //RTL8192C +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 + +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 +#define REG_MBIST_DONE 0x0178 +//#define REG_MBIST_FAIL 0x017C +#define REG_32K_CTRL 0x0194 //RTL8188E +#define REG_C2HEVT_MSG_NORMAL 0x01A0 +#define REG_C2HEVT_CLEAR 0x01AF +#define REG_MCUTST_1 0x01c0 +#define REG_MCUTST_WOWLAN 0x01C7 // Defined after 8188E series. +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX_0 0x01D0 +#define REG_HMEBOX_1 0x01D4 +#define REG_HMEBOX_2 0x01D8 +#define REG_HMEBOX_3 0x01DC +#define REG_LLT_INIT 0x01E0 +#define REG_LLT_ADDR 0x01E4//20130415 KaiYuan add for 8814 +#define REG_HMEBOX_EXT0 0x01F0 // For 8723B, 8192E, 8812, 8821 +#define REG_HMEBOX_EXT1 0x01F4 // For 8723B, 8192E, 8812, 8821 +#define REG_HMEBOX_EXT2 0x01F8 // For 8723B, 8192E, 8812, 8821 +#define REG_HMEBOX_EXT3 0x01FC // For 8723B, 8192E, 8812, 8821 + + +#define REG_HMEBOX_EXT_0_88E ((pHalData->bIsMPChip) ? 0x01F0 : 0x0088) +#define REG_HMEBOX_EXT_1_88E ((pHalData->bIsMPChip) ? 0x01F4 : 0x008A) +#define REG_HMEBOX_EXT_2_88E ((pHalData->bIsMPChip) ? 0x01F8 : 0x008C) +#define REG_HMEBOX_EXT_3_88E ((pHalData->bIsMPChip) ? 0x01FC : 0x008E) + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN 0x0200 +#define REG_FIFOPAGE 0x0204 +#define REG_TDECTRL 0x0208 +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 +#define REG_RQPN_NPQ 0x0214 +#define REG_TDECTRL1 0x0208 + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_FW_UPD_RDPTR 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 +#define REG_RXDMA_CONTROL 0x0286 // Control the RX DMA. +#define REG_RXPKT_NUM_OLD 0x0287 // The number of packets in RXPKTBUF. +#define REG_RXDMA_STATUS 0x0288 + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG 0x0300 +#define REG_INT_MIG 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address +//sherry added for DBI Read/Write 20091126 +#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration +#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration +#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration +//#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY +#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY +#define REG_DBG_SEL 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM +#define REG_WATCH_DOG 0x0368 + +// RTL8723 series ------------------------------- +#define REG_PCIE_HISR_EN 0x0394 //PCIE Local Interrupt Enable Register +#define REG_PCIE_HISR 0x03A0 +#define REG_PCIE_HISRE 0x03A4 +#define REG_PCIE_HIMR 0x03A8 +#define REG_PCIE_HIMRE 0x03AC + +#define REG_USB_HIMR 0xFE38 +#define REG_USB_HIMRE 0xFE3C +#define REG_USB_HISR 0xFE78 +#define REG_USB_HISRE 0xFE7C + +// spec version 11 +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_VOQ_INFORMATION 0x0400 +#define REG_VIQ_INFORMATION 0x0404 +#define REG_BEQ_INFORMATION 0x0408 +#define REG_BKQ_INFORMATION 0x040C +#define REG_MGQ_INFORMATION 0x0410 +#define REG_HGQ_INFORMATION 0x0414 +#define REG_BCNQ_INFORMATION 0x0418 +#define REG_TXPKT_EMPTY 0x041A + +#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_HWSEQ_CTRL 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY 0x0425 +#define REG_LIFECTRL_CTRL 0x0426 +#define REG_MULTI_BCNQ_OFFSET 0x0427 +#define REG_SPEC_SIFS 0x0428 +#define REG_RL 0x042A +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1 0x0448 +#define REG_ARFR2 0x044C +#define REG_ARFR3 0x0450 +#define REG_TXPKTBUF_BCNQ_BDNY1 0x0424 + +#define REG_AGGLEN_LMT 0x0458 +#define REG_AMPDU_MIN_SPACE 0x045C +#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D +#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_RD_RESP_PKT_TH 0x0463 + +#define REG_INIRTS_RATE_SEL 0x0480 + +// [483h] REG_DATA_SC +// [3:0] = BIT_TXSC_20M, [7:4] = BIT_TXSC_40M +#define REG_DATA_SC 0x483 +#define REG_INIDATA_RATE_SEL 0x0484 + +#define REG_POWER_STAGE1 0x04B4 +#define REG_POWER_STAGE2 0x04B8 +#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 +#define REG_STBC_SETTING 0x04C4 +#define REG_QUEUE_CTRL 0x04C6 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_MAX_AGGR_NUM 0x04CA +#define REG_RTS_MAX_AGGR_NUM 0x04CB +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF +#define REG_EARLY_MODE_CONTROL 0x04D0 +#define REG_HW_SEQ_NUM_0 0x04D8 +#define REG_HW_SEQ_NUM_1 0x04DA +#define REG_NQOS_SEQ 0x04DC +#define REG_QOS_SEQ 0x04DE +#define REG_NEED_CPU_HANDLE 0x04E0 +#define REG_PKT_LOSE_RPT 0x04E1 +#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_TX_RPT_CTRL 0x04EC +#define REG_TX_RPT_TIME 0x04F0 // 2 byte +#define REG_DUMMY 0x04FC + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CTX 0x0514 +#define REG_SIFS_TRX 0x0516 +#define REG_TSFTR_SNC_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 +#define REG_BCN_CTRL_1 0x0551 +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 // HW Port 1 TSF Register +#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU) +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACMHWCTRL 0x05C0 +#define REG_NOA_DESC_SEL 0x05CF +#define REG_NOA_DESC_DURATION 0x05E0 +#define REG_NOA_DESC_INTERVAL 0x05E4 +#define REG_NOA_DESC_START 0x05E8 +#define REG_NOA_DESC_COUNT 0x05EC + +#define REG_DMC 0x05F0 //Dual MAC Co-Existence Register +#define REG_SCH_TX_CMD 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +#define REG_APSD_CTRL 0x0600 +#define REG_BWOPMODE 0x0603 +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F + +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG 0x0628 + +#define REG_FW_AOAC_DBG_MSG_1 0x0630 +#define REG_FW_AOAC_DBG_MSG_2 0x0634 +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063A +#define REG_RESP_SIFS_CCK 0x63C +#define REG_RESP_SIFS_OFDM 0x63E +#define REG_TRX_SIFS_OFDM 0x517 +// 20100719 Joseph: Hardware register definition change. (HW datasheet v54) +// 2013115 Roger: Hardware register definition error. (HW datasheet ??) +#define REG_RESP_CCK_SIFS 0x063C // CCK R2T [15:8], T2T[7:0] +#define REG_RESP_OFDM_SIFS 0x063E // OFDM R2T [15:8], T2T[7:0] +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + + +// +// Note: +// The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is +// always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending +// CTS in the air. We must update this value greater than 25,000 microseconds to pass the item. +// The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented +// by SD1 Scott. +// By Bruce, 2011-07-18. +// +#define REG_NAV_UPPER 0x0652 // unit of 128 + + +// Security +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +#define REG_TRXPTCL_CTRL 0x668 +// Power +#define REG_WOW_CTRL 0x0690 +#define REG_PS_RX_INFO 0x0692 +#define REG_UAPSD_TID 0x0693 +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_NUM REG_WKFMCAM_CMD +#define REG_WKFMCAM_NUM_88E 0x698 +#define REG_WKFMCAM_RWD 0x069C +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP2 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 +#define REG_BT_COEX_TABLE 0x06C0 + + +// Hardware Port 2 +#define REG_MACID1 0x0700 +#define REG_BSSID1 0x0708 + +#define REG_IQ_DUMP 0x07C0 + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 + +// for 92DU high_Queue low_Queue Normal_Queue select +#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 +//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45 +#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 +//#define REG_USB_LOW_Queue_Select_MAC1 0xFE48 +#define REG_USB_ACCESS_TIMEOUT 0xFE4C + + +// For normal chip +#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 +#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 +#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 +#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF + +// for 8814AE memory mapping CTRL_INFO 4KB /RPT_CRC 4KB/MACID 8KB +#define MEMORY_MAP_BUF_READ 0x8000 +#define CTRL_INFO_PAGE 0x660 +#define RPT_CRC 0x661 +#define TX_SHORT_CUT_MACID_0_31 0x662 +#define TX_SHORT_CUT_MACID_32_63 0x663 +#define RPT_BUF_DESC_NUM_8814A 256 + +#define RPT_BUF_DESC_NUM_8821B 256 + +#define RPT_BUF_DESC_NUM_8822B 256 + + +//----------------------------------------------------- + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. + +#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. +#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. +#define MSR (REG_CR + 2) // Media Status register +#define ISR_88E REG_HISR_88E +#define ISR_92C REG_HISR + +// +// <Roger_TODO> We should take RTL8723B into consideration, 2012.10.08 +// +#define GET_ISR(_Adapter) \ + (IS_HARDWARE_TYPE_JAGUAR(_Adapter)||IS_HARDWARE_TYPE_8723B(_Adapter) || IS_HARDWARE_TYPE_8703B(_Adapter) || IS_HARDWARE_TYPE_8723D(_Adapter) || IS_HARDWARE_TYPE_8188F(_Adapter) || IS_HARDWARE_TYPE_8192E(_Adapter))?REG_HISR0: \ + (IS_HARDWARE_TYPE_8188E(_Adapter) ? ISR_88E : ISR_92C) + +#define TSFR REG_TSFTR // Timing Sync Function Timer Register. +#define TSFR1 REG_TSFTR1 // HW Port 1 TSF Register + +#define PBP REG_PBP + +// Redifine MACID register, to compatible prior ICs. +#define IDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd +#define WCAMI REG_CAMWRITE // Software write CAM input content +#define RCAMO REG_CAMREAD // Software read/write CAM config +#define CAMDBG REG_CAMDBG +#define SECR REG_SECCFG //Security Configuration Register + +// Unused register +#define UnusedRegister 0x1BF +#define DCAM UnusedRegister +#define PSR UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister + +// Min Spacing related settings. +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A + +//---------------------------------------------------------------------------- +// 8192C Cmd9346CR bits (Offset 0xA, 16bit) +//---------------------------------------------------------------------------- +#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 +#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 +#define Cmd9346CR_9356SEL BIT4 + +//---------------------------------------------------------------------------- +// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) +//---------------------------------------------------------------------------- +#define GPIOSEL_GPIO 0 +#define GPIOSEL_ENBT BIT5 + +//---------------------------------------------------------------------------- +// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) +//---------------------------------------------------------------------------- +#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value +#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value +#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. +#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) + +//---------------------------------------------------------------------------- +// 8811A GPIO PIN Control Register (offset 0x60, 4 byte) +//---------------------------------------------------------------------------- +#define GPIO_IN_8811A REG_GPIO_PIN_CTRL_2 // GPIO pins input value +#define GPIO_OUT_8811A (REG_GPIO_PIN_CTRL_2+1) // GPIO pins output value +#define GPIO_IO_SEL_8811A (REG_GPIO_PIN_CTRL_2+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. +#define GPIO_MOD_8811A (REG_GPIO_PIN_CTRL_2+3) + + +//---------------------------------------------------------------------------- +// 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) +//---------------------------------------------------------------------------- +#define HSIMR_GPIO12_0_INT_EN BIT0 +#define HSIMR_SPS_OCP_INT_EN BIT5 +#define HSIMR_RON_INT_EN BIT6 +#define HSIMR_PDN_INT_EN BIT7 +#define HSIMR_GPIO9_INT_EN BIT25 + + +//---------------------------------------------------------------------------- +// 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) +//---------------------------------------------------------------------------- +#define HSISR_GPIO12_0_INT BIT0 +#define HSISR_SPS_OCP_INT BIT5 +#define HSISR_RON_INT_EN BIT6 +#define HSISR_PDNINT BIT7 +#define HSISR_GPIO9_INT BIT25 + +//---------------------------------------------------------------------------- +// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) +//---------------------------------------------------------------------------- +/* +Network Type +00: No link +01: Link in ad hoc network +10: Link in infrastructure network +11: AP mode +Default: 00b. +*/ +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 +#define MSR_TYPE_MASK 0x03 + +//---------------------------------------------------------------------------- +// 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) +//---------------------------------------------------------------------------- +#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISRE_OFFSET 52 + +// +// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) +// +//---------------------------------------------------------------------------- +// 8192C Response Rate Set Register (offset 0x181, 24bits) +//---------------------------------------------------------------------------- +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 + +//---------------------------------------------------------------------------- +// 8192C Rate Definition +//---------------------------------------------------------------------------- +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 + + +// NOTE: For 92CU - Ziv +//CCK +#define RATE_1M BIT(0) +#define RATE_2M BIT(1) +#define RATE_5_5M BIT(2) +#define RATE_11M BIT(3) +//OFDM +#define RATE_6M BIT(4) +#define RATE_9M BIT(5) +#define RATE_12M BIT(6) +#define RATE_18M BIT(7) +#define RATE_24M BIT(8) +#define RATE_36M BIT(9) +#define RATE_48M BIT(10) +#define RATE_54M BIT(11) + +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ + RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ + RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 + +//---------------------------------------------------------------------------- +// 8192C BW_OPMODE bits (Offset 0x203, 8bit) +//---------------------------------------------------------------------------- +#define BW_OPMODE_20MHZ BIT2 +#define BW_OPMODE_5G BIT1 + + +//---------------------------------------------------------------------------- +// 8192C CAM Config Setting (offset 0x250, 1 byte) +//---------------------------------------------------------------------------- +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 + +#define TOTAL_CAM_ENTRY 32 + +#define CAM_CONFIG_USEDK TRUE +#define CAM_CONFIG_NO_USEDK FALSE + + +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 + +// +// 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) +// +#define WOW_PMEN BIT0 // Power management Enable. +#define WOW_WOMEN BIT1 // WoW function on or off. +#define WOW_MAGIC BIT2 // Magic packet +#define WOW_UWF BIT3 // Unicast Wakeup frame. + +// +// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) +// +//---------------------------------------------------------------------------- +// 8190 IMR/ISR bits (offset 0xfd, 8bits) +//---------------------------------------------------------------------------- +#define IMR8190_DISABLED 0x0 +#define IMR_DISABLED 0x0 +// IMR DW0 Bit 0-31 +#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 +#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 +#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 +#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 +#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow +#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt +#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 +#define IMR_RXFOVW BIT12 // Receive FIFO Overflow +#define IMR_RDU BIT11 // Receive Descriptor Unavailable +#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. +#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup +#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt +#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup +#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt +#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt +#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt +#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt +#define IMR_VODOK BIT1 // AC_VO DMA Interrupt +#define IMR_ROK BIT0 // Receive DMA OK Interrupt + +// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) +#define IMR_TSF_BIT32_TOGGLE BIT15 +#define IMR_TXERR BIT11 +#define IMR_RXERR BIT10 +#define IMR_C2HCMD BIT9 +#define IMR_CPWM BIT8 +//RSVD [2-7] + +//---------------------------------------------------------------------------- +// 8723E series PCIE Host IMR/ISR bit +//---------------------------------------------------------------------------- +// IMR DW0 Bit 0-31 +#define PHIMR_TIMEOUT2 BIT31 +#define PHIMR_TIMEOUT1 BIT30 +#define PHIMR_PSTIMEOUT BIT29 +#define PHIMR_GTINT4 BIT28 +#define PHIMR_GTINT3 BIT27 +#define PHIMR_TXBCNERR BIT26 +#define PHIMR_TXBCNOK BIT25 +#define PHIMR_TSF_BIT32_TOGGLE BIT24 +#define PHIMR_BCNDMAINT3 BIT23 +#define PHIMR_BCNDMAINT2 BIT22 +#define PHIMR_BCNDMAINT1 BIT21 +#define PHIMR_BCNDMAINT0 BIT20 +#define PHIMR_BCNDOK3 BIT19 +#define PHIMR_BCNDOK2 BIT18 +#define PHIMR_BCNDOK1 BIT17 +#define PHIMR_BCNDOK0 BIT16 +#define PHIMR_HSISR_IND_ON BIT15 +#define PHIMR_BCNDMAINT_E BIT14 +#define PHIMR_ATIMEND_E BIT13 +#define PHIMR_ATIM_CTW_END BIT12 +#define PHIMR_HISRE_IND BIT11 // RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) +#define PHIMR_C2HCMD BIT10 +#define PHIMR_CPWM2 BIT9 +#define PHIMR_CPWM BIT8 +#define PHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt +#define PHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define PHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt +#define PHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt +#define PHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt +#define PHIMR_VODOK BIT2 // AC_VO DMA Interrupt +#define PHIMR_RDU BIT1 // Receive Descriptor Unavailable +#define PHIMR_ROK BIT0 // Receive DMA OK Interrupt + +// PCIE Host Interrupt Status Extension bit +#define PHIMR_BCNDMAINT7 BIT23 +#define PHIMR_BCNDMAINT6 BIT22 +#define PHIMR_BCNDMAINT5 BIT21 +#define PHIMR_BCNDMAINT4 BIT20 +#define PHIMR_BCNDOK7 BIT19 +#define PHIMR_BCNDOK6 BIT18 +#define PHIMR_BCNDOK5 BIT17 +#define PHIMR_BCNDOK4 BIT16 +// bit12-15: RSVD +#define PHIMR_TXERR BIT11 +#define PHIMR_RXERR BIT10 +#define PHIMR_TXFOVW BIT9 +#define PHIMR_RXFOVW BIT8 +// bit2-7: RSVD +#define PHIMR_OCPINT BIT1 +// bit0: RSVD + +#define UHIMR_TIMEOUT2 BIT31 +#define UHIMR_TIMEOUT1 BIT30 +#define UHIMR_PSTIMEOUT BIT29 +#define UHIMR_GTINT4 BIT28 +#define UHIMR_GTINT3 BIT27 +#define UHIMR_TXBCNERR BIT26 +#define UHIMR_TXBCNOK BIT25 +#define UHIMR_TSF_BIT32_TOGGLE BIT24 +#define UHIMR_BCNDMAINT3 BIT23 +#define UHIMR_BCNDMAINT2 BIT22 +#define UHIMR_BCNDMAINT1 BIT21 +#define UHIMR_BCNDMAINT0 BIT20 +#define UHIMR_BCNDOK3 BIT19 +#define UHIMR_BCNDOK2 BIT18 +#define UHIMR_BCNDOK1 BIT17 +#define UHIMR_BCNDOK0 BIT16 +#define UHIMR_HSISR_IND BIT15 +#define UHIMR_BCNDMAINT_E BIT14 +//RSVD BIT13 +#define UHIMR_CTW_END BIT12 +//RSVD BIT11 +#define UHIMR_C2HCMD BIT10 +#define UHIMR_CPWM2 BIT9 +#define UHIMR_CPWM BIT8 +#define UHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt +#define UHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define UHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt +#define UHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt +#define UHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt +#define UHIMR_VODOK BIT2 // AC_VO DMA Interrupt +#define UHIMR_RDU BIT1 // Receive Descriptor Unavailable +#define UHIMR_ROK BIT0 // Receive DMA OK Interrupt + +// USB Host Interrupt Status Extension bit +#define UHIMR_BCNDMAINT7 BIT23 +#define UHIMR_BCNDMAINT6 BIT22 +#define UHIMR_BCNDMAINT5 BIT21 +#define UHIMR_BCNDMAINT4 BIT20 +#define UHIMR_BCNDOK7 BIT19 +#define UHIMR_BCNDOK6 BIT18 +#define UHIMR_BCNDOK5 BIT17 +#define UHIMR_BCNDOK4 BIT16 +// bit14-15: RSVD +#define UHIMR_ATIMEND_E BIT13 +#define UHIMR_ATIMEND BIT12 +#define UHIMR_TXERR BIT11 +#define UHIMR_RXERR BIT10 +#define UHIMR_TXFOVW BIT9 +#define UHIMR_RXFOVW BIT8 +// bit2-7: RSVD +#define UHIMR_OCPINT BIT1 +// bit0: RSVD + + +#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF // The value when the NIC is unplugged for PCI. +#define HAL_NIC_UNPLUG_PCI_ISR 0xEAEAEAEA // The value when the NIC is unplugged for PCI in PCI interrupt (page 3). + +//---------------------------------------------------------------------------- +// 8188 IMR/ISR bits +//---------------------------------------------------------------------------- +#define IMR_DISABLED_88E 0x0 +// IMR DW0(0x0060-0063) Bit 0-31 +#define IMR_TXCCK_88E BIT30 // TXRPT interrupt when CCX bit of the packet is set +#define IMR_PSTIMEOUT_88E BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_88E BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_88E BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TBDER_88E BIT26 // Transmit Beacon0 Error +#define IMR_TBDOK_88E BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_88E BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_88E BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDOK0_88E BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_88E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End +#define IMR_HISR1_IND_INT_88E BIT11 // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) +#define IMR_C2HCMD_88E BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_88E BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK +#define IMR_BKDOK_88E BIT5 // AC_BK DMA OK +#define IMR_BEDOK_88E BIT4 // AC_BE DMA OK +#define IMR_VIDOK_88E BIT3 // AC_VI DMA OK +#define IMR_VODOK_88E BIT2 // AC_VO DMA OK +#define IMR_RDU_88E BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_88E BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_88E BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_88E BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_88E BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_88E BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_88E BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_88E BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_88E BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_88E BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_88E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_88E BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_88E BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow + +#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF // The value when the NIC is unplugged for PCI. + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ + //---------------------------------------------------------------------------- + // 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) + //---------------------------------------------------------------------------- +// Note: +// The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, +// the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. +// 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. +// By Bruce, 2011-09-22. +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopBK BIT3 +#define StopBE BIT2 +#define StopVI BIT1 +#define StopVO BIT0 + +//---------------------------------------------------------------------------- +// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_NONQOS_VHT BIT26 // Reserved +#define RCR_RSVD_BIT25 BIT25 // Reserved +#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. +#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. +#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. +#define RCR_RSVD_BIT21 BIT21 // Reserved +#define RCR_RSVD_BIT20 BIT20 // Reserved +#define RCR_RSVD_BIT19 BIT19 // Reserved +#define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser. +#define RCR_BM_DATA_EN BIT17 // Broadcast data packet interrupt enable. +#define RCR_UC_DATA_EN BIT16 // Unicast data packet interrupt enable. +#define RCR_RSVD_BIT15 BIT15 // Reserved +#define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0 +#define RCR_AMF BIT13 // Accept management type frame +#define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. +#define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). +#define RCR_RSVD_BIT10 BIT10 // Reserved +#define RCR_AICV BIT9 // Accept ICV error packet +#define RCR_ACRC32 BIT8 // Accept CRC32 error packet +#define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp) +#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data) +#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet +#define RCR_APWRMGT BIT5 // Accept power management packet +#define RCR_ADD3 BIT4 // Accept address 3 match packet +#define RCR_AB BIT3 // Accept broadcast packet +#define RCR_AM BIT2 // Accept multicast packet +#define RCR_APM BIT1 // Accept physical match packet +#define RCR_AAP BIT0 // Accept all unicast packet + +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- + +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BITT3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + + +//2 EFUSE_TEST (For RTL8723 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define CPU_DL_READY BIT(15) //add flag by gw for fw download ready 20130826 +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define EXT_VENDOR_ID (BIT(18)|BIT(19)) //Currently only for RTL8723B +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +//2REG_GPIO_OUTSTS (For RTL8723 only) +#define EFS_HCI_SEL (BIT(0)|BIT(1)) +#define PAD_HCI_SEL (BIT(2)|BIT(3)) +#define HCI_SEL (BIT(4)|BIT(5)) +#define PKG_SEL_HCI BIT(6) +#define FEN_GPS BIT(7) +#define FEN_BT BIT(8) +#define FEN_WL BIT(9) +#define FEN_PCI BIT(10) +#define FEN_USB BIT(11) +#define BTRF_HWPDN_N BIT(12) +#define WLRF_HWPDN_N BIT(13) +#define PDN_BT_N BIT(14) +#define PDN_GPS_N BIT(15) +#define BT_CTL_HWPDN BIT(16) +#define GPS_CTL_HWPDN BIT(17) +#define PPHY_SUSB BIT(20) +#define UPHY_SUSB BIT(21) +#define PCI_SUSEN BIT(22) +#define USB_SUSEN BIT(23) +#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) + + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- + + +//2 Function Enable Registers +//2 CR + + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + +//2 PBP - Page Size Register +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + + +//2 TRXFF_BNDY + + +//2 LLT_INIT +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 +#if USE_8814AS_MACRO_SETTING == 1 +#define _LLT_INIT_DATA(x) (((x) & 0xFFF)<<16) //20130415 KaiYuan modify for 8814 +#define _LLT_INIT_ADDR(x) ((x) & 0xFFF ) //20130415 KaiYuan Modify for 8814 +#else +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#endif +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +#define _LLT_INIT_DATA_8814A(x) (((x) & 0xFFF)<<16) +#define _LLT_INIT_ADDR_8814A(x) ((x) & 0xFFF) + +#define _LLT_INIT_DATA_8821B(x) (((x) & 0xFFF)<<16) +#define _LLT_INIT_ADDR_8821B(x) ((x) & 0xFFF) + +#define _LLT_INIT_DATA_8822B(x) (((x) & 0xFFF)<<16) +#define _LLT_INIT_ADDR_8822B(x) ((x) & 0xFFF) + + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +//2 RQPN +#define _HPQ(x) ((x) & 0xFF) +#define _LPQ(x) (((x) & 0xFF) << 8) +#define _PUBQ(x) (((x) & 0xFF) << 16) +#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register + + +#define HPQ_PUBLIC_DIS BIT(24) +#define LPQ_PUBLIC_DIS BIT(25) +#define LD_RQPN BIT(31) + + +//2 TDECTL +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK +#define DROP_DATA_EN BIT(9) + +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- + +//2 REG_RXDMA_CONTROL, 0x0286h +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +//2 FWHW_TXQ_CTRL +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 SPEC SIFS +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +//2 REG_DATA_SC (0x483) + +#define HAL_DATA_SC_DONT_CARE 0 +#define HAL_DATA_SC_UPPER 1 +#define HAL_DATA_SC_LOWER 2 +#define HAL_DATA_DUPLICATE 3 + + + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- + + + +//2 EDCA setting +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) + + +//2 BCN_CTRL +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) +#define STOP_BCNQ BIT(6) + + +//2 ACMHWCTRL +#define AcmHw_HwEn BIT(0) +#define AcmHw_BeqEn BIT(1) +#define AcmHw_ViqEn BIT(2) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) +#define AcmHw_ViqStatus BIT(5) +#define AcmHw_VoqStatus BIT(6) + +//2 //REG_DUAL_TSF_RST (0x553) +#define DUAL_TSF_RST_P2P BIT(4) + + +//2 // REG_NOA_DESC_SEL (0x5CF) +#define NOA_DESC_SEL_0 0 +#define NOA_DESC_SEL_1 BIT(4) + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- + +//2 APSD_CTRL +#define APSDOFF BIT(6) + +#define RATE_BITMAP_ALL 0xFFFFF + +// Only use CCK 1M rate for ACK +#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 + +//2 TCR +#define TSFRST BIT(0) +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) + + + +//2 RCR +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +//ADF is not used in 8822B, Bit 11 has other purpose and should not be set when init +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define FORCEACK BIT(26) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +#define APP_FCS BIT(31) + + +//2 SECCFG +#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key +#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key +#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption +#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption +#define SCR_SKByA2 BIT(4) //Search kEY BY A2 +#define SCR_NoSKMC BIT(5) //No Key Search Multicast +#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key +#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key + + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration +// +//----------------------------------------------------- + +//SDIO host local register space mapping. +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] + +#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID +#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_TX_EXTQ_DEVICE_ID 7 // 0b[16], 110b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +//SDIO Tx Free Page Index +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 +#define EXTRA_QUEUE_IDX 4 //20130422 KaiYuan added for 8814 Extra Queue + +#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control +#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask +#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine +#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode +#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SDIO_REG_HCPWM1 0x0025 // HCI Current Power Mode 1 +#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 +#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SDIO_REG_H2C 0x0060 // Host to Client +#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 +#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 +#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control +#define SDIO_REG_HIMR_ON 0x0090 //SDIO Host Extension Interrupt Mask Always +#define SDIO_REG_HISR_ON 0x0091 //SDIO Host Extension Interrupt Status Always + +#define SDIO_HIMR_DISABLED 0 + +// RTL8723/RTL8188E SDIO Host Interrupt Mask Register +#define SDIO_HIMR_RX_REQUEST_MSK BIT0 +#define SDIO_HIMR_AVAL_MSK BIT1 +#define SDIO_HIMR_TXERR_MSK BIT2 +#define SDIO_HIMR_RXERR_MSK BIT3 +#define SDIO_HIMR_TXFOVW_MSK BIT4 +#define SDIO_HIMR_RXFOVW_MSK BIT5 +#define SDIO_HIMR_TXBCNOK_MSK BIT6 +#define SDIO_HIMR_TXBCNERR_MSK BIT7 +#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 +#define SDIO_HIMR_C2HCMD_MSK BIT17 +#define SDIO_HIMR_CPWM1_MSK BIT18 +#define SDIO_HIMR_CPWM2_MSK BIT19 +#define SDIO_HIMR_HSISR_IND_MSK BIT20 +#define SDIO_HIMR_GTINT3_IND_MSK BIT21 +#define SDIO_HIMR_GTINT4_IND_MSK BIT22 +#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 +#define SDIO_HIMR_OCPINT_MSK BIT24 +#define SDIO_HIMR_ATIMEND_MSK BIT25 +#define SDIO_HIMR_ATIMEND_E_MSK BIT26 +#define SDIO_HIMR_CTWEND_MSK BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HIMR_MCU_ERR_MSK BIT28 +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 + +// SDIO Host Interrupt Service Routine +#define SDIO_HISR_RX_REQUEST BIT0 +#define SDIO_HISR_AVAL BIT1 +#define SDIO_HISR_TXERR BIT2 +#define SDIO_HISR_RXERR BIT3 +#define SDIO_HISR_TXFOVW BIT4 +#define SDIO_HISR_RXFOVW BIT5 +#define SDIO_HISR_TXBCNOK BIT6 +#define SDIO_HISR_TXBCNERR BIT7 +#define SDIO_HISR_BCNERLY_INT BIT16 +#define SDIO_HISR_C2HCMD BIT17 +#define SDIO_HISR_CPWM1 BIT18 +#define SDIO_HISR_CPWM2 BIT19 +#define SDIO_HISR_HSISR_IND BIT20 +#define SDIO_HISR_GTINT3_IND BIT21 +#define SDIO_HISR_GTINT4_IND BIT22 +#define SDIO_HISR_PSTIMEOUT BIT23 +#define SDIO_HISR_OCPINT BIT24 +#define SDIO_HISR_ATIMEND BIT25 +#define SDIO_HISR_ATIMEND_E BIT26 +#define SDIO_HISR_CTWEND BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HISR_MCU_ERR BIT28 +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 + + +// SDIO HCI Suspend Control Register +#define HCI_RESUME_PWR_RDY BIT1 +#define HCI_SUS_CTRL BIT0 + +#define MAX_TX_AGG_PACKET_NUMBER 0x8 + + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- + +//2 USB Information (0xFE17) +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +//2 Special Option +#define USB_AGG_EN BIT(3) + + +//2REG_C2HEVT_CLEAR +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + +//2REG_MULTI_FUNC_CTRL(For RTL8723 Only) +#define WL_HWPDN_EN BIT0 // Enable GPIO[9] as WiFi HW PDn source +#define WL_HWPDN_SL BIT1 // WiFi HW PDn polarity control +#define WL_FUNC_EN BIT2 // WiFi function enable +#define WL_HWROF_EN BIT3 // Enable GPIO[9] as WiFi RF HW PDn source +#define BT_HWPDN_EN BIT16 // Enable GPIO[11] as BT HW PDn source +#define BT_HWPDN_SL BIT17 // BT HW PDn polarity control +#define BT_FUNC_EN BIT18 // BT function enable +#define BT_HWROF_EN BIT19 // Enable GPIO[11] as BT/GPS RF HW PDn source +#define GPS_HWPDN_EN BIT20 // Enable GPIO[10] as GPS HW PDn source +#define GPS_HWPDN_SL BIT21 // GPS HW PDn polarity control +#define GPS_FUNC_EN BIT22 // GPS function enable + +//3 REG_LIFECTRL_CTRL +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL_MSDU_LIFE_TIME_UNIT_128 128 // in us, said by Tim. +#define HAL_MSDU_LIFE_TIME_UNIT_256 256 // in us, said by Tim. + +//2 8192D PartNo. +#define PARTNO_92D_NIC (BIT7|BIT6) +#define PARTNO_92D_NIC_REMARK (BIT5|BIT4) +#define PARTNO_SINGLE_BAND_VS BIT3 +#define PARTNO_SINGLE_BAND_VS_REMARK BIT1 +#define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) +#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) + + +//======================================================== +// General definitions +//======================================================== +//YP change for 88E SMIC +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) ( IS_VENDOR_8188E_SMIC_SERIES(__Adapter) ? 255 : 175 ) +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8821B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8822B 2048-1 + +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A 2048-1 //20130415 KaiYuan add for 8814 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 + +#define POLLING_LLT_THRESHOLD 20 + + +#define POLLING_READY_TIMEOUT_COUNT_88E(__Adapter) ((GET_HAL_DATA(__Adapter)->bIsMPChip) ? (u4Byte)3000 : (u4Byte)1000) + +#define POLLING_READY_TIMEOUT_COUNT_92C 1000 + +// Min Spacing related settings. +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A + +// GPIO BIT +#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 +#define HAL_8192EU_HW_GPIO_WPS_BIT BIT7 + + +#endif // #ifndef __INC_HALCOMREG_H diff --git a/network/wlan/WDI/HAL/HalComTxPwrCfg.h b/network/wlan/WDI/HAL/HalComTxPwrCfg.h new file mode 100644 index 00000000..4497cce3 --- /dev/null +++ b/network/wlan/WDI/HAL/HalComTxPwrCfg.h @@ -0,0 +1,119 @@ + +u1Byte +PHY_GetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u1Byte Band, + IN u1Byte RfPath, + IN u1Byte TxNum, + IN RATE_SECTION RateSection + ); + +u1Byte +PHY_GetRateSectionIndexOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + + +VOID +PHY_GetRateValuesOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Value, + OUT pu1Byte RateIndex, + OUT ps1Byte PwrByRateVal, + OUT pu1Byte RateNum + ); + +u1Byte +PHY_GetRateIndexOfTxPowerByRate( + IN u1Byte Rate + ); + +VOID +PHY_SetTxPowerIndexByRateSection( + IN PADAPTER pAdapter, + IN u1Byte RFPath, + IN u1Byte Channel, + IN u1Byte RateSection + ); + + +s1Byte +PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u1Byte Band, + IN u1Byte RFPath, + IN u1Byte TxNum, + IN u1Byte RateIndex + ); + +VOID +PHY_SetTxPowerByRate( + IN PADAPTER pAdapter, + IN u1Byte Band, + IN u1Byte RFPath, + IN u1Byte TxNum, + IN u1Byte Rate, + IN s1Byte Value + ); + +VOID +PHY_SetTxPowerLevelByPath( + IN PADAPTER Adapter, + IN u1Byte channel, + IN u1Byte path + ); + +VOID +PHY_SetTxPowerIndexByRateArray( + IN PADAPTER pAdapter, + IN u1Byte RFPath, + IN CHANNEL_WIDTH BandWidth, + IN u1Byte Channel, + IN pu1Byte Rates, + IN u1Byte RateArraySize + ); + +VOID +PHY_InitTxPowerByRate( + IN PADAPTER pAdapter + ); + +VOID +PHY_StoreTxPowerByRate( + IN PADAPTER pAdapter, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + + +VOID +PHY_TxPowerByRateConfiguration( + IN PDM_ODM_T pDM_Odm + ); + +u1Byte +PHY_GetTxPowerIndexBase( + IN PADAPTER pAdapter, + IN u1Byte RFPath, + IN u1Byte Rate, + IN CHANNEL_WIDTH BandWidth, + IN u1Byte Channel, + OUT PBOOLEAN bIn24G + ); + +s1Byte +PHY_GetTxPowerTrackingOffset( + PADAPTER pAdapter, + u1Byte RFPath, + u1Byte Rate + ); + + diff --git a/network/wlan/WDI/HAL/HalComTxPwrLmtCfg.h b/network/wlan/WDI/HAL/HalComTxPwrLmtCfg.h new file mode 100644 index 00000000..fabb60d7 --- /dev/null +++ b/network/wlan/WDI/HAL/HalComTxPwrLmtCfg.h @@ -0,0 +1,33 @@ + +s1Byte +PHY_GetTxPowerLimit( + IN PADAPTER Adapter, + IN u4Byte RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u1Byte RfPath, + IN u1Byte DataRate, + IN u1Byte Channel + ); + +VOID +PHY_SetTxPowerLimit( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +VOID +PHY_ConvertTxPowerLimitToPowerIndex( + IN PADAPTER Adapter + ); + +VOID +PHY_InitTxPowerLimit( + IN PDM_ODM_T pDM_Odm + );
\ No newline at end of file diff --git a/network/wlan/WDI/HAL/HalDM.h b/network/wlan/WDI/HAL/HalDM.h new file mode 100644 index 00000000..d0855954 --- /dev/null +++ b/network/wlan/WDI/HAL/HalDM.h @@ -0,0 +1,123 @@ +/***************************************************************************** + * Copyright(c) 2011, RealTEK Technology Inc. All Right Reserved. + * + * Module: HALDM.h + * + * + * Note: The header file records + * + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * 09/22/2011 MHC Create initial version. + * +******************************************************************************/ +#ifndef __HALDM_H__ +#define __HALDM_H__ + + + + +//============================================================ +// Description: +// +// This file is for 92CE/92CU dynamic mechanism only +// +// +//============================================================ + +//============================================================ +// structure and define +//============================================================ +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 + +//============================================================ +// function prototype +//============================================================ +void InitHalDm( + IN PADAPTER Adapter + ); +void DeInitHalDm( + IN PADAPTER Adapter + ); + + +void HalDmWatchDog( + IN PADAPTER Adapter + ); + + +u1Byte +dm_initial_gain_MinPWDB( + IN PADAPTER pAdapter +); + +void +dm_CCK_PacketDetectionThresh( + IN PADAPTER pAdapter +); + +VOID +dm_CCK_PacketDetectionThresh_DMSP( + IN PADAPTER pAdapter +); + + +VOID +DM_Write_DIG_DMSP( + IN PADAPTER pAdapter +); + + +extern VOID +DM_AggModeSwitch( + IN PADAPTER Adapter + ); + + +BOOLEAN +dm_DualMacGetParameterFromBuddyAdapter( + PADAPTER Adapter +); + + +// +// 2011/02/10 MH Add 92D relative definition in the section. +// +VOID +DM_Write_DIG_DMSP( + IN PADAPTER pAdapter +); +// +// 2011/02/10 MH Add 92D relative definition in the section. +// + +VOID +odm_FindMinimumRSSI_Dmsp( + IN PADAPTER pAdapter +); + +VOID +DM_OverwriteDig( + IN PADAPTER Adapter, + IN u1Byte digValue + ); + +VOID +DM_OverwriteCckCcaThres( + IN PADAPTER Adapter, + IN u1Byte ccaThres + ); + +VOID +DM_HwPbcGPIOChk( + IN PADAPTER pAdapter + ); + +#endif //__HALDM_H__ + diff --git a/network/wlan/WDI/HAL/HalEEPROM.h b/network/wlan/WDI/HAL/HalEEPROM.h new file mode 100644 index 00000000..913ac988 --- /dev/null +++ b/network/wlan/WDI/HAL/HalEEPROM.h @@ -0,0 +1,97 @@ +#ifndef __INC_EEPROM_H +#define __INC_EEPROM_H + +#define EEPROM_MAX_SIZE 256 +#define CLOCK_RATE 50 //100us + +//- EEPROM opcodes +#define EEPROM_READ_OPCODE 06 +#define EEPROM_WRITE_OPCODE 05 +#define EEPROM_ERASE_OPCODE 07 +#define EEPROM_EWEN_OPCODE 19 // Erase/write enable +#define EEPROM_EWDS_OPCODE 16 // Erase/write disable + +#define CSR_EEPROM_CONTROL_REG (Adapter->HalFunc.pEEPROMOffset->CmdRegister) +#define EEDO (Adapter->HalFunc.pEEPROMOffset->BIT_EEDO) // EEPROM data out +#define EEDI (Adapter->HalFunc.pEEPROMOffset->BIT_EEDI) // EEPROM data in (set for writing data) +#define EECS (Adapter->HalFunc.pEEPROMOffset->BIT_EECS) // EEPROM chip select (1=high, 0=low) +#define EESK (Adapter->HalFunc.pEEPROMOffset->BIT_EESK) // EEPROM shift clock (1=high, 0=low) +#define EEM0 (Adapter->HalFunc.pEEPROMOffset->BIT_EEM0) +#define EEM1 (Adapter->HalFunc.pEEPROMOffset->BIT_EEM1) + + +u2Byte +GetEEpromAddressSize( + u2Byte Size + ); + +u2Byte +GetEEpromSize( + PADAPTER Adapter + ); + +u2Byte +ReadEEprom( + PADAPTER Adapter, + u2Byte Reg + ); + + + +VOID +ShiftOutBits( + PADAPTER Adapter, + u2Byte data, + u2Byte count + ); + +u2Byte +ShiftInBits( + PADAPTER Adapter + ); + +VOID +RaiseClock( + PADAPTER Adapter, + u2Byte *x + ); + +VOID +LowerClock( + PADAPTER Adapter, + u2Byte *x + ); + +VOID +EEpromCleanup( + PADAPTER Adapter + ); + +VOID +UpdateChecksum( + PADAPTER Adapter + ); + +VOID +WriteEEprom( + PADAPTER Adapter, + u2Byte reg, + u2Byte data + ); + +u2Byte +WaitEEPROMCmdDone( + PADAPTER Adapter + ); + +VOID +StandBy( + PADAPTER Adapter + ); + +extern BOOLEAN +EEPROM_ProgramMap( + IN PADAPTER Adapter, + IN ps1Byte pFileName); + +#endif // #ifndef __INC_EEPROM_H diff --git a/network/wlan/WDI/HAL/HalEfuse.h b/network/wlan/WDI/HAL/HalEfuse.h new file mode 100644 index 00000000..9bfe9d94 --- /dev/null +++ b/network/wlan/WDI/HAL/HalEfuse.h @@ -0,0 +1,461 @@ +/****************************************************************************** + * + * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + * + * 03/04/2011 Cosa Modify + * +******************************************************************************/ +#ifndef __INC_HAL_EFUSE_H__ +#define __INC_HAL_EFUSE_H__ + +//============================================= +// Here we define which chip need to be supported or not +//============================================= +#define SUPPORT_EFUSE 1 +#if(SUPPORT_EFUSE == 1) + +#define EFUSE_SUPPORT_92S 1 +#define EFUSE_SUPPORT_92C 1 +#define EFUSE_SUPPORT_92D 1 +#define EFUSE_SUPPORT_8188E 1 +#define EFUSE_SUPPORT_8188F 1 +#define EFUSE_SUPPORT_8812A 1 +#define EFUSE_SUPPORT_8811A 1 +#define EFUSE_SUPPORT_8821A 1 +#define EFUSE_SUPPORT_8192E 1 +#define EFUSE_SUPPORT_8814A 1 +#define EFUSE_SUPPORT_8723B 1 +#define EFUSE_SUPPORT_8703B 1 +#define EFUSE_SUPPORT_8822B 1 +#define EFUSE_SUPPORT_8723D 1 + +#else +#define EFUSE_SUPPORT_92S 0 +#define EFUSE_SUPPORT_92C 0 +#define EFUSE_SUPPORT_92D 0 +#define EFUSE_SUPPORT_8188E 0 +#define EFUSE_SUPPORT_8188F 0 +#define EFUSE_SUPPORT_8812A 0 +#define EFUSE_SUPPORT_8192E 0 +#define EFUSE_SUPPORT_8814A 0 +#endif +//============================================= + + +#define HWSET_MAX_SIZE_128 128 +#define HWSET_MAX_SIZE_256 256 +#define HWSET_MAX_SIZE_512 512 + +#define EFUSE_BANK_SIZE 512 + +#define EFUSE_ERROE_HANDLE 1 +/*--------------------------Define Parameters-------------------------------*/ +#define EFUSE_INIT_MAP 0 +#define EFUSE_MODIFY_MAP 1 + +#define _TRUE 1 +#define _FALSE 0 + +#define EFUSE_CLK_CTRL EFUSE_CTRL +#ifdef BIT + #undef BIT +#endif +#define BIT(x) (1 << (x)) + + +#define PG_STATE_HEADER 0x01 +#define PG_STATE_WORD_0 0x02 +#define PG_STATE_WORD_1 0x04 +#define PG_STATE_WORD_2 0x08 +#define PG_STATE_WORD_3 0x10 +#define PG_STATE_DATA 0x20 + +#define PG_SWBYTE_H 0x01 +#define PG_SWBYTE_L 0x02 + +#define PGPKT_DATA_SIZE 8 + +#define EFUSE_WIFI 0 +#define EFUSE_BT 1 + +enum{ + VOLTAGE_V25 = 0x03, + LDOE25_SHIFT = 28 , + }; + +enum _EFUSE_DEF_TYPE { + TYPE_EFUSE_MAX_SECTION = 0, + TYPE_EFUSE_REAL_CONTENT_LEN = 1, + TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, + TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, + TYPE_EFUSE_MAP_LEN = 4, + TYPE_EFUSE_PROTECT_BYTES_BANK = 5, + TYPE_EFUSE_CONTENT_LEN_BANK = 6, +}; + +#define EFUSE_MAX_MAP_LEN 1024 +#define EFUSE_MAX_HW_SIZE 1024 + +#define EFUSE_MAX_SECTION_BASE 16 + +typedef enum _PACKAGE_TYPE_E +{ + PACKAGE_DEFAULT, + PACKAGE_QFN68, + PACKAGE_TFBGA90, + PACKAGE_TFBGA80, + PACKAGE_TFBGA79 +}PACKAGE_TYPE_E; + + +#define IS_AVAILABLE_EFUSE_ADDR(_Adapter, _Addr) \ + (IS_HARDWARE_TYPE_8188E(_Adapter) ? AVAILABLE_EFUSE_ADDR_88E(_Addr) : AVAILABLE_EFUSE_ADDR_92C(_Addr)) +#define IS_AVAILABLE_BT_EFUSE_ADDR(_eFuse_Addr, _endBank) (_eFuse_Addr < (_endBank+1) * EFUSE_MAX_BANK_SIZE) + +#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F) +#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) +#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5) + +#define EFUSE_REPEAT_THRESHOLD_ 0 +#define EFUSE_REPEAT_HEADER_THRESHOLD 0 + +#define EFUSE_MAP_LEN 128 +#define EFUSE_MAX_SECTION 16 +#define EFUSE_MAX_WORD_UNIT 4 + +// +// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section +// 9bytes + 1byt + 5bytes and pre 1byte. +// For worst case: +// | 1byte|----8bytes----|1byte|--5bytes--| +// | | Reserved(14bytes) | +// +#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. + + +//============================================= + +#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset)) +#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset)) +#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt()) +#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt()) +#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset)) +#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset)) + + +#define IS_MASKED(ic, txt, offset) ((pHalData->bIsMPChip) ? IS_MASKED_MP(ic,txt, offset) : IS_MASKED_TC(ic,txt, offset)) +#define GET_MASK_ARRAY_LEN(ic, txt) ((pHalData->bIsMPChip) ? GET_MASK_ARRAY_LEN_MP(ic,txt) : GET_MASK_ARRAY_LEN_TC(ic,txt)) +#define GET_MASK_ARRAY(ic, txt, out) do {((pHalData->bIsMPChip) ? GET_MASK_ARRAY_MP(ic,txt, out) : GET_MASK_ARRAY_TC(ic,txt, out));} while(0) + + + +//============================================= +// The following is for BT Efuse definition +//============================================= +#define EFUSE_BT_MAX_MAP_LEN 1024 +#define EFUSE_MAX_BANK 4 +#define EFUSE_MAX_BANK_SIZE 512 +#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) +//============================================= +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ +typedef struct PG_PKT_STRUCT_A{ + UINT8 offset; + UINT8 word_en; + UINT8 data[8]; + u1Byte word_cnts; +}PGPKT_STRUCT,*PPGPKT_STRUCT; + + +typedef struct _EFUSE_HAL{ + u1Byte fakeEfuseBank; + u4Byte fakeEfuseUsedBytes; + u1Byte fakeEfuseContent[EFUSE_MAX_HW_SIZE]; + u1Byte fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; + u1Byte fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; + + u4Byte EfuseUsedBytes; + u1Byte EfuseUsedPercentage; + + u2Byte BTEfuseUsedBytes; + u1Byte BTEfuseUsedPercentage; + u1Byte BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u1Byte BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u1Byte BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + u2Byte fakeBTEfuseUsedBytes; + u1Byte fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u1Byte fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u1Byte fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + // EFUSE Configuration, initialized in HAL_CmnInitPGData(). + const u2Byte MaxSecNum_WiFi; + const u2Byte MaxSecNum_BT; + const u2Byte WordUnit; + const u2Byte PhysicalLen_WiFi; + const u2Byte PhysicalLen_BT; + const u2Byte LogicalLen_WiFi; + const u2Byte LogicalLen_BT; + const u2Byte BankSize; + const u2Byte TotalBankNum; + const u2Byte BankNum_WiFi; + const u2Byte BankNum_BT; + const u2Byte OOBProtectBytes; + const u2Byte ProtectBytes; + const u2Byte BankAvailBytes; + const u2Byte TotalAvailBytes_WiFi; + const u2Byte TotalAvailBytes_BT; + + const u2Byte HeaderRetry; + const u2Byte DataRetry; + + RT_ERROR_CODE Status; +}EFUSE_HAL, *PEFUSE_HAL; +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ + +extern VOID +EFUSE_ShadowRead( + IN PADAPTER pAdapter, + IN u1Byte ByteCount, + IN u2Byte Offset, + IN OUT u4Byte *Value ); + +extern VOID +EFUSE_MaskedShadowRead( + IN PADAPTER pAdapter, + IN u1Byte ByteCount, + IN u2Byte Offset, + IN OUT u4Byte *Value ); + +extern VOID +EFUSE_ShadowWrite( + IN PADAPTER pAdapter, + IN u1Byte Type, + IN u2Byte Offset, + IN OUT u4Byte Value ); +BOOLEAN +EFUSE_ShadowUpdate( + IN PADAPTER pAdapter, + IN BOOLEAN bPseudoTest + ); +BOOLEAN +EFUSE_ShadowUpdateChk( + IN PADAPTER pAdapter, + IN u1Byte efuseType, + IN BOOLEAN bPseudoTest); +VOID +EFUSE_RenewShadowMaps( + IN PADAPTER pAdapter, + IN u1Byte efuseType, + IN BOOLEAN bPseudoTest); + + +extern VOID +EFUSE_ForceWriteVendorId( + IN PADAPTER pAdapter); + +BOOLEAN +EFUSE_ProgramMap( + IN PADAPTER Adapter, + IN ps1Byte pFileName, + IN u1Byte TableType, + IN BOOLEAN bPseudoTest); // 0=Shadow 1=Real Efuse + +extern VOID +EFUSE_ResetLoader( + IN PADAPTER pAdapter); + + + +VOID +Hal_InitEfuseVars( + IN PEFUSE_HAL pEfuseHal + ); + + +VOID +Hal_ReadEFuseByIC( + PADAPTER Adapter, + u1Byte efuseType, + u2Byte _offset, + u2Byte _size_byte, + u1Byte *pbuf, + IN BOOLEAN bPseudoTest + ); +VOID +Hal_ReadEFuse_Pseudo( + PADAPTER Adapter, + u1Byte efuseType, + u2Byte _offset, + u2Byte _size_byte, + u1Byte *pbuf, + IN BOOLEAN bPseudoTest + ); +VOID +EFUSE_LoadMap( + IN PADAPTER pAdapter, + IN u1Byte efuseType, + IN OUT u1Byte *Efuse, + IN BOOLEAN bPseudoTest); + +VOID +EFUSE_PowerSwitch( + IN PADAPTER pAdapter, + IN UINT8 bWrite, + IN UINT8 PwrState); +INT32 +EFUSE_PgPacketWrite( + IN PADAPTER pAdapter, + IN UINT8 efuseType, + IN UINT8 offset, + IN UINT8 word_en, + IN UINT8 *data, + IN BOOLEAN bPseudoTest); + +VOID +EFUSE_FakeShadowRead1Byte( + IN PADAPTER pAdapter, + IN u1Byte efuseType, + IN u2Byte Offset, + IN OUT UINT8 *Value ); +VOID +EFUSE_FakeShadowWrite1Byte( + IN PADAPTER pAdapter, + IN u2Byte Offset, + IN UINT8 Value ); +BOOLEAN +EFUSE_FakeContentRead1Byte( + IN PADAPTER pAdapter, + IN u2Byte Offset, + IN OUT UINT8 *Value ); +BOOLEAN +EFUSE_FakeContentWrite1Byte( + IN PADAPTER pAdapter, + IN u2Byte Offset, + IN UINT8 Value ); +VOID +EFUSE_GetEfuseDefinition( + IN PADAPTER pAdapter, + IN u1Byte efuseType, + IN u1Byte type, + OUT pu2Byte pOut, + IN BOOLEAN bPseudoTest + ); +u2Byte +EFUSE_GetCurrentSize( + IN PADAPTER pAdapter, + IN u1Byte efuseType, + IN BOOLEAN bPseudoTest); +UINT8 +EFUSE_CalculateWordCnts( + IN UINT8 word_en); + +void +EFUSE_WordEnableDataRead( IN UINT8 word_en, + IN UINT8 *sourdata, + IN UINT8 *targetdata); +INT32 +EFUSE_OneByteRead( + IN PADAPTER pAdapter, + IN u2Byte addr, + IN UINT8 *data, + IN BOOLEAN bPseudoTest); +INT32 +EFUSE_OneByteWrite( + IN PADAPTER pAdapter, + IN u2Byte addr, + IN UINT8 data, + IN BOOLEAN bPseudoTest); + +INT32 +EFUSE_PgPacketRead( IN PADAPTER pAdapter, + IN UINT8 offset, + IN UINT8 *data, + IN BOOLEAN bPseudoTest); +UINT8 +EFUSE_WordEnableDataWrite( IN PADAPTER pAdapter, + IN u2Byte efuse_addr, + IN UINT8 word_en, + IN UINT8 *data, + IN BOOLEAN bPseudoTest); + +BOOLEAN +EFUSE_ContentWrite1Byte( + IN PADAPTER pAdapter, + IN UINT8 bank, + IN u2Byte Offset, + IN UINT8 Value ); + +VOID +efuse_ShadowRead1Byte_BT( + IN PADAPTER pAdapter, + IN u2Byte Offset, + IN OUT UINT8 *Value ); +VOID +EFUSE_ShadowReadBT( + IN PADAPTER pAdapter, + IN u1Byte Type, + IN u2Byte Offset, + IN OUT u4Byte *Value ); +VOID +efuse_ShadowWrite1Byte_BT( + IN PADAPTER pAdapter, + IN u2Byte Offset, + IN UINT8 Value ); +VOID +EFUSE_ShadowWriteBT( + IN PADAPTER pAdapter, + IN u1Byte Type, + IN u2Byte Offset, + IN OUT u4Byte Value ); +VOID +EFUSE_FakeShadowWrite1Byte_BT( + IN PADAPTER pAdapter, + IN u2Byte Offset, + IN UINT8 Value ); + +BOOLEAN +EFUSE_SwitchToBank( + IN PADAPTER pAdapter, + IN u1Byte bank, + IN BOOLEAN bPseudoTest + ); +BOOLEAN +EFUSE_ShadowUpdateBT( + IN PADAPTER pAdapter, + IN BOOLEAN bPseudoTest + ); +u1Byte +EFUSE_GetFakeEfusebank( + IN PADAPTER Adapter + ); +VOID +EFUSE_SetFakeEfusebank( + IN PADAPTER Adapter, + IN u1Byte bank + ); + +VOID +Hal_EEValueCheck( + IN u1Byte EEType, + IN PVOID pInValue, + OUT PVOID pOutValue + ); + +/*--------------------------Exported Function prototype---------------------*/ + +#endif + diff --git a/network/wlan/WDI/HAL/HalFw.h b/network/wlan/WDI/HAL/HalFw.h new file mode 100644 index 00000000..9a4603e8 --- /dev/null +++ b/network/wlan/WDI/HAL/HalFw.h @@ -0,0 +1,105 @@ +#ifndef __INC_HAL_FW_H +#define __INC_HAL_FW_H + + +#define FW_QUEME_MECHANISM_NEW 0 + +#define FW_QUEUE_IDLE 0 +#define FW_QUEUE_WAIT 1 + +#define FW_H2C_MAX_NUM 20 + +#if(FW_QUEME_MECHANISM_NEW == 1) +typedef struct _FW_COM_STR{ + VIRTUAL_MEMORY fwDataListBuf; + u4Byte NumTotalH2c; + RT_LIST_ENTRY halFwH2cWaitQueue; + u4Byte NumFwWaitH2c; + RT_LIST_ENTRY halFwH2cIdleQueue; + u4Byte NumFwIdleH2c; +}FW_COM_STR, *PFW_COM_STR; +#else +#define FW_COM_STR u1Byte +#endif + +// H2C command structre to keep the info for USB/SDIO interface. +// The H2C cmd format in 92S is different from 92C/88E series +// so use_H2C_CMD _8192C to separare 92S and 92C/88E series. +typedef struct _H2C_CMD_8192C +{ + u1Byte ElementID; + u4Byte CmdLen; + u4Byte CmdBuffer[2]; + u1Byte InProgress; +}H2C_CMD_8192C,*PH2C_CMD_8192C; + +typedef struct _H2C_CMD_ENTRY +{ + RT_LIST_ENTRY listEntry; + H2C_CMD_8192C h2cCmd; +}H2C_CMD_ENTRY,*PH2C_CMD_ENTRY; + +#if(FW_QUEME_MECHANISM_NEW == 1) +//================================================== +// extern function +//================================================== +RT_STATUS +FW_AllocateMemory( + IN PADAPTER Adapter + ); +VOID +FW_FreeMemory( + IN PADAPTER Adapter + ); +BOOLEAN +FW_SendH2c( + IN PADAPTER Adapter, + IN u1Byte elementId, + IN u4Byte dataLen, + IN pu1Byte pData + ); +BOOLEAN +FW_RetrieveH2c( + IN PADAPTER Adapter, + IN pu1Byte pData + ); +BOOLEAN +FW_IsH2cWaitQueueEmpty( + IN PADAPTER Adapter + ); +#else +#define FW_AllocateMemory(Adapter) RT_STATUS_SUCCESS +#define FW_FreeMemory(Adapter) +#endif + +VOID +FW_InitializeVariables( + IN PADAPTER Adapter + ); + +VOID +FW_FillH2CCmd( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer + ); + + +VOID +FW_WaitForH2CQueueEmpty( + IN PADAPTER pAdapter + ); + +VOID +FW_InitializeHALVars( + IN PADAPTER Adapter + ); + +RT_STATUS +FW_FirmwareDownload( + IN PADAPTER Adapter, + IN BOOLEAN bUsedWoWLANFw + ); + +#endif diff --git a/network/wlan/WDI/HAL/HalH2cIOCmd.h b/network/wlan/WDI/HAL/HalH2cIOCmd.h new file mode 100644 index 00000000..c2b51a6d --- /dev/null +++ b/network/wlan/WDI/HAL/HalH2cIOCmd.h @@ -0,0 +1,372 @@ +#ifndef __INC_HAL_H2CIOCMD_H +#define __INC_HAL_H2CIOCMD_H + +//-------------------------------------------- +//3 Host Message Box +//-------------------------------------------- + +//_RSVDPAGE_LOC_CMD0 +#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_BT_CTS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + +//_MEDIA_STATUS_RPT_PARM_CMD1 +#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) + +// _WoWLAN PARAM_CMD5 +#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 1, __Value) +#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 2, 1, __Value) +#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value) +#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 5, 1, __Value) +#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 6, 1, __Value) +#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 7, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_PULSE_CNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 8, __Value) + +//WLANINFO_PARM +#define SET_H2CCMD_WLANINFO_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_WLANINFO_PARM_CHANNEL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_WLANINFO_PARM_BW40MHZ(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +// _REMOTE_WAKEUP_CMD7 +#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NETWORK_LIST_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) + +// _AP_OFFLOAD_CMD8 +#define SET_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +// FCS_LOC_CMD10 (Not appear in 8192EE) +#define SET_H2CCMD_RSVDPAGE_FCS_LOC_NULL_DATA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_FCS_LOC_NULL_DATA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_FCS_LOC_NULL_DATA2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +// FCS_INFO_CMD11 +#define SET_H2CCMD_FCS_INFO_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 4, __Value) +#define SET_H2CCMD_FCS_INFO_TOTAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 4, __Value) +#define SET_H2CCMD_FCS_INFO_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+1), 0, 8, __Value) +#define SET_H2CCMD_FCS_INFO_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 0, 2, __Value) +#define SET_H2CCMD_FCS_INFO_BWSC_40(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 2, 3, __Value) +#define SET_H2CCMD_FCS_INFO_BWSC_80(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 5, 3, __Value) +#define SET_H2CCMD_FCS_INFO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+3), 0, 8, __Value) +#define SET_H2CCMD_FCS_INFO_MACID0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+4), 0, 8, __Value) +#define SET_H2CCMD_FCS_INFO_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+5), 0, 8, __Value) + +// From Jaguar +#define SET_H2CCMD_FCS_INFO_RFETYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+6), 0, 8, __Value) + +// _PWR_MOD_CMD20 +#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) +#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) +#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_H2CCMD_PWRMODE_PARM_TWO_ANTENNA_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + +#define GET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE((__pH2CCmd), 0, 8) + +// AOAC_GLOBAL_INFO +#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +// AOAC_RSVDPAGE_LOC +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROT_OFFLOAD_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value) + +// RSVDPAGE_LOC_3 +#define SET_H2CCMD_RSVDPAGE_LOC_3_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) + +//_SCAN_OFFLOAD_CTRL +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_D0_SCAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_RTD3_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 1, __Value) +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_U3_SCAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 2, 1, __Value) +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_NLO_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value) +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_IPS_DEPENDENT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value) +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_CHNL_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_SSID_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +#define GET_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_ENABLE(__pH2CCmd) LE_BITS_TO_1BYTE((__pH2CCmd), 0, 8) + +//_CHANNEL_PATTERN +#define SET_H2CCMD_CHANNEL_PATTERN_PARM_CHNL_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_CHANNEL_PATTERN_PARM_TXPWRIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_CHANNEL_PATTERN_PARM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_CHANNEL_PATTERN_PARM_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +// BT_FW_PATCH +//#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) +#define SET_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+4, 0, 8, __Value) +#define SET_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+5, 0, 8, __Value) + +//_INACTIVE_PS_CTRL +#define SET_H2CCMD_INACTIVE_PS_PARM_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) +#define SET_H2CCMD_INACTIVE_PS_PARM_IGNORE_PS_CONDITION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 1, __Value) +#define SET_H2CCMD_INACTIVE_PS_PARM_SCAN_FREQUENCY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_INACTIVE_PS_PARM_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +#define GET_H2CCMD_INACTIVE_PS_PARM_FUNC_ENABLE(__pH2CCmd) LE_BITS_TO_1BYTE((__pH2CCmd), 0, 1) + +// Disconnect_Decision_Control +// <Note> +// 1. The value "CHECK_PERIOD" should be larger than 5 which Fw checks beacon lost period. +// 2. "TRY_OK_BCN_LOST_CNT" should be smaller than "CHECK_PERIOD". +#define SET_H2CCMD_DISCONNECT_DECISION_CTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) +#define SET_H2CCMD_DISCONNECT_DECISION_CTRL_USER_SETTING(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 1, __Value) +#define SET_H2CCMD_DISCONNECT_DECISION_CTRL_CNT_BCN_LOST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 2, 1, __Value) +#define SET_H2CCMD_DISCONNECT_DECISION_CTRL_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) // unit: beacon period +#define SET_H2CCMD_DISCONNECT_DECISION_CTRL_TRYPKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_DISCONNECT_DECISION_CTRL_TRY_OK_BCN_LOST_CNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +// WIFI_CALIBRATION +#define SET_H2CCMD_WIFI_CALIBRATION_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) + +// Keep Alive Control +#define SET_H2CCMD_KEEP_ALIVE_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) +#define SET_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 1, __Value) +#define SET_H2CCMD_KEEP_ALIVE_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +typedef enum _H2C_CMD +{ + H2C_RSVDPAGE = 0, + H2C_MSRRPT = 1, + H2C_SCAN = 2, // No used in 8723B, 8192E, 8812/8821 + H2C_KEEP_ALIVE_CTRL = 3, + H2C_DISCONNECT_DECISION = 4, + + H2C_INIT_OFFLOAD = 6, // No used in 8723B, 8192E, 8812/8821 + H2C_AP_OFFLOAD = 8, // + H2C_BCN_RSVDPAGE = 9, // + H2C_PROBERSP_RSVDPAGE = 10, // + H2C_TXPOWER_INDEX_OFFLOAD = 0x0B, + H2C_FCS_LOCATION = 0x10, + H2C_FCS_INFO = 0x11, + + H2C_NAN = 0x1B, + + H2C_SETPWRMODE = 0x20, + + H2C_PS_TUNING_PARA = 0x21, // No used in 8723B, 8192E, 8812/8821 + H2C_PS_TUNING_PARA2 = 0x22, // + H2C_PS_LPS_PARA = 0x23, // + H2C_P2P_PS_OFFLOAD = 0x24, // + + H2C_INACTIVE_PS = 0x27, + + H2C_RA_MASK = 0x40, + H2C_TxBF = 0x41, // ADDed from 8192E and 8812 + H2C_RSSI_REPORT = 0x42, + H2C_AP_REQ_TXRPT = 0x43, + H2C_INIT_RATE_COLLECT = 0x44, + H2C_IQ_CALIBRATION = 0x45, + H2C_RA_PARA_ADJUST = 0x47, + H2C_FW_TRACE_EN = 0x49, + + + H2C_BT_FW_PATCH = 0x6a, + H2C_WIFI_CALIBRATION = 0x6d, // 8723B used only + + H2C_WO_WLAN = 0x80, + H2C_REMOTE_WAKE_CTRL = 0x81, + H2C_AOAC_GLOBAL_INFO = 0x82, + H2C_AOAC_RSVDPAGE = 0x83, + + H2C_AOAC_RSVDPAGE2 = 0x84, // 8812 used only + + H2C_SCAN_OFFLOAD_CTRL = 0x86, + H2C_FW_SWCHANNL = 0x87, + H2C_AOAC_RSVDPAGE3 = 0x88, + + //Not defined in new 88E H2C CMD Format + H2C_SELECTIVE_SUSPEND_ROF_CMD, + H2C_P2P_PS_MODE, // This be replaced with H2C_P2P_PS_OFFLOAD(0x24) + H2C_PSD_RESULT, + MAX_H2CCMD +}_H2C_CMD; + +VOID +FillH2CCmd( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +BOOLEAN +CheckFwReadLastH2C( + IN PADAPTER Adapter, + IN u1Byte BoxNum +); + +VOID +SetFwPwrModeCmd( + IN PADAPTER Adapter, + IN u1Byte Mode +); + +VOID +SetFwMediaStatusRptCmd( + IN PADAPTER Adapter, + IN u1Byte mstatus, + IN BOOLEAN macId_Ind, + IN u1Byte macId, + IN u1Byte macId_End +); + +VOID +SetFwRemoteWakeCtrlCmd( + IN PADAPTER Adapter, + IN u1Byte Enable +); + +VOID +SetFwGlobalInfoCmd( + IN PADAPTER Adapter +); + +VOID +SetFwScanOffloadCtrlCmd( + IN PADAPTER Adapter, + IN u1Byte Type, + IN u1Byte ScanOffloadEnable, + IN u1Byte NLOEnable +); + +VOID +SetFwInactivePSCmd( + IN PADAPTER Adapter, + IN u1Byte Enable, + IN BOOLEAN bActiveWakeup, + IN BOOLEAN bForceClkOff +); + +VOID +SetFwBTFwPatchCmd( + IN PADAPTER Adapter, + IN u2Byte FwSize +); + +VOID +SetFwDisconnectDecisionCtrlCmd( + IN PADAPTER Adapter, + IN BOOLEAN bEnabled +); + +VOID +SetFwWiFiCalibrationCmd( + IN PADAPTER Adapter, + IN u1Byte u1Enable +); + +VOID +ConstructFwGTKInfo( + IN PADAPTER Adapter, + OUT pu1Byte pBuffer +); + +VOID +ConstructFwRemoteWakeCtrlInfo( + IN PADAPTER Adapter, + OUT pu1Byte pBuffer +); + +VOID +ConstructFwProtrolOffloadInfo( + IN PADAPTER Adapter, + OUT pu1Byte pBuffer +); + +VOID +ConstructFwChannelInfo( + IN PADAPTER Adapter, + OUT pu1Byte pBuffer, + OUT pu4Byte pBufferLen +); + +VOID +ConstructFwSsidInfo( + IN PADAPTER Adapter, + OUT pu1Byte pBuffer, + OUT pu4Byte pBufferLen +); + +VOID +ConstructFwNLOInfo( + IN PADAPTER Adapter, + OUT pu1Byte pBuffer, + OUT pu4Byte pBufferLen +); + +u4Byte +FillH2CCommand( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +#if(FW_QUEME_MECHANISM_NEW != 1) +VOID +AddH2CCmdQueue( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +BOOLEAN +RetriveH2CCmdQueue( + IN PADAPTER Adapter, + IN pu1Byte pH2CCmdBuf +); +#endif + + +VOID +SetFwFcsLocCmd( + IN PADAPTER Adapter +); + +VOID +SetFwFcsInfoCmd( + IN PADAPTER Adapter, + IN pu1Byte pContext, + IN BOOLEAN bSet +); + +VOID +HalSetFwKeepAliveCmd( + IN PADAPTER pAdapter, + IN BOOLEAN bFuncEn +); + +RT_STATUS +HalSetFWWoWlanMode( + IN PADAPTER pAdapter, + IN BOOLEAN bFuncEn +); +#endif
\ No newline at end of file diff --git a/network/wlan/WDI/HAL/HalIcGlue.h b/network/wlan/WDI/HAL/HalIcGlue.h new file mode 100644 index 00000000..c1c0cceb --- /dev/null +++ b/network/wlan/WDI/HAL/HalIcGlue.h @@ -0,0 +1,1110 @@ +#if (RTL8822B_SUPPORT == 0) +#define ex_halbtc8822b1ant_power_on_setting(btcoexist) +#define ex_halbtc8822b1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8822b1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8822b1ant_init_coex_dm(btcoexist) +#define ex_halbtc8822b1ant_ips_notify(btcoexist, type) +#define ex_halbtc8822b1ant_lps_notify(btcoexist, type) +#define ex_halbtc8822b1ant_scan_notify(btcoexist, type) +#define ex_halbtc8822b1ant_connect_notify(btcoexist, type) +#define ex_halbtc8822b1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8822b1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8822b1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8822b1ant_halt_notify(btcoexist) +#define ex_halbtc8822b1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8822b1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8822b1ant_periodical(btcoexist) +#define ex_halbtc8822b1ant_display_coex_info(btcoexist) +#define ex_halbtc8822b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8822b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8822b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8822b1ant_display_ant_detection(btcoexist) +#define ex_halbtc8822b1ant_dbg_control(btcoexist, op_code, op_len, pdata) + +#define SDIO_8822B_HWDESC_HEADER_LEN 0 +#define SDIO_8822B_DUMMY_OFFSET 1 +#define SDIO_8822B_ALL_DUMMY_LENGTH 0 + +#define REG_SYS_FUNC_EN_8822B 0 +#define REG_RF_CTRL_8822B 0 + +#define TxDescriptorChecksum_8822B(_txDesc) + +#define SwLedOn_8822B(_Adapter, _pLed) 0 +#define SwLedOff_8822B(_Adapter, _pLed) 0 + +#define TxUsbAggregation8822BU(_Adapter, _queueId) + +#define SetWoWLANCAMEntry8822B(_Adapter) +#define HalSetFWWoWlanMode8822B(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8822B(_pAdapter, _bFuncEn) +#define H2CCmdAction8822B(_Adapter, _pBuf, _bufLen) 0 + +#define SET_TX_DESC_USB_TXAGG_NUM_8822B(__pTxDesc, __Value) + +#define TxDescriptorChecksum_8822B(_txDesc) + +#define Hal_InitEfuseVars_8822B(_pEfuseHal) +#define Hal_ReadTxPowerInfo8822B(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfuseSwitchToBank8822B(_pAdapter, _bank, _bPseudoTest) TRUE +#define Hal_EfusePowerSwitch8822B(_pAdapter, _bWrite, _PwrState) +#define Hal_EfusePowerSwitch8822B_TestChip(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8822B(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8822B(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8822B(_Adapter, _Type, _ScanOffloadEnable, _NLOEnable) +#define SetFwRemoteWakeCtrlCmd_8822B(_Adapter, _Enable) +#define SetFwInactivePSCmd_8822B(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8822B(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8822B(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define PHY_QueryBBReg8822B(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8822B(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8822B(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8822B(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define PHY_BB8822B_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8822B(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8822B(_Adapter, _PowerIndex, _RFPath, _Rate) + +#define PHY_Combine4ByteTxPowerIndex_8822B(_A, _RF, _R, _B, _C) 0 +#define HAL_DownloadRSVD_PreCfg_8822B(_A) +#define HAL_DownloadRSVD_PostCfg_8822B(_A) RT_STATUS_FAILURE + + + +#endif //#if (RTL8822B_SUPPORT == 0) + +#if (RTL8723D_SUPPORT == 0) + +#define NAN_Allocate(_pAdapter) RT_STATUS_SUCCESS +#define NAN_Free(_pAdapter) +#define NAN_FreeAllWorkItem(Adapter) +#define NAN_InitTimer(Adapter) +#define NAN_CancelTimer(Adapter) +#define NAN_ReleaseTimer(Adapter) +#define NAN_ENABLED(_pAdapter) FALSE +#define NAN_OnBeaconReceived(_pAdapter, _pRfd, _posMpdu) RT_STATUS_SUCCESS +#define NAN_OnSDFReceived(_pAdapter, _pRfd, _posMpdu) RT_STATUS_SUCCESS +#define NAN_UpdateDefaultSetting(_pAdapter, _ID, _pInputBuffer, _InputBufferLen) RT_STATUS_SUCCESS +#define NAN_GetAvailabilityInfo(_pAdapter, _pInputBuffer, _InputBufferLen) RT_STATUS_SUCCESS + +#define MAX_RX_DMA_BUFFER_SIZE_8723D 0x3800 // RX 14K + +#define ex_halbtc8723d1ant_power_on_setting(btcoexist) +#define ex_halbtc8723d1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8723d1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8723d1ant_init_coex_dm(btcoexist) +#define ex_halbtc8723d1ant_ips_notify(btcoexist, type) +#define ex_halbtc8723d1ant_lps_notify(btcoexist, type) +#define ex_halbtc8723d1ant_scan_notify(btcoexist, type) +#define ex_halbtc8723d1ant_connect_notify(btcoexist, type) +#define ex_halbtc8723d1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8723d1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8723d1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8723d1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8723d1ant_halt_notify(btcoexist) +#define ex_halbtc8723d1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8723d1ant_ScoreBoardStatusNotify(btcoexist, tmp_buf, length) +#define ex_halbtc8723d1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8723d1ant_periodical(btcoexist) +#define ex_halbtc8723d1ant_display_coex_info(btcoexist) +#define ex_halbtc8723d1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8723d1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8723d1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8723d1ant_display_ant_detection(btcoexist) + +#define ex_halbtc8723d2ant_power_on_setting(btcoexist) +#define ex_halbtc8723d2ant_pre_load_firmware(btcoexist) +#define ex_halbtc8723d2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8723d2ant_init_coex_dm(btcoexist) +#define ex_halbtc8723d2ant_ips_notify(btcoexist, type) +#define ex_halbtc8723d2ant_lps_notify(btcoexist, type) +#define ex_halbtc8723d2ant_scan_notify(btcoexist, type) +#define ex_halbtc8723d2ant_connect_notify(btcoexist, type) +#define ex_halbtc8723d2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8723d2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8723d2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8723d2ant_halt_notify(btcoexist) +#define ex_halbtc8723d2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8723d2ant_periodical(btcoexist) +#define ex_halbtc8723d2ant_display_coex_info(btcoexist) + +#define PrepareRxDesc8723DE(_Adapter, _LengthArray) RT_STATUS_FAILURE +#define FreeRxDesc8723DE(_Adapter) +#define ResetRxDesc8723DE(_Adapter, _LengthArray) RT_STATUS_FAILURE +#define ReturnRxDescBuffer8723DE(_Adapter, _QueueID, _index, _buffer) +#define IsRxDescFilledWithPacket8723DE(_Adapter, _QueueID, _index, _uBufferAddress) FALSE + +#define HalDownloadRSVDPage8723DE(_Adapter) +#define Hal_DBIRead4Byte_8723DE(_Adapter, _Addr) 0 +#define Hal_DBIWrite4Byte_8723DE(_Adapter, _Addr, _Data) + +#define SwLedOn_8723D(_Adapter, _pLed) 0 +#define SwLedOff_8723D(_Adapter, _pLed) 0 + +#define TxUsbAggregation8723DU(_Adapter, _queueId) + +#define SetWoWLANCAMEntry8723D(_Adapter) +#define HalSetFWWoWlanMode8723D(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8723D(_pAdapter, _bFuncEn) +#define H2CCmdAction8723D(_Adapter, _pBuf, _bufLen) 0 + +#define Hal_InitEfuseVars_8723D(_pEfuseHal) +#define Hal_ReadTxPowerInfo8723D(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfuseSwitchToBank8723D(_pAdapter, _bank, _bPseudoTest) TRUE +#define Hal_EfusePowerSwitch8723D(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8723D(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8723D(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8723D(_Adapter, _Type, _ScanOffloadEnable, _NLOEnable) +#define SetFwRemoteWakeCtrlCmd_8723D(_Adapter, _Enable) +#define SetFwInactivePSCmd_8723D(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8723D(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8723D(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define HAL_FwLPSDeepSleepInit8723D(_pAdapter) +#define HAL_FwLPSDeepSleepDeInit8723D(_pAdapter) +#define HAL_CheckChangeTxBoundaryInProgress8723D(_pAdapter) FALSE +#define HAL_FwLPSDeepSleepGetStatusForEnterLPS8723D(_pAdapter) FALSE + +#define PHY_QueryBBReg8723D(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8723D(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8723D(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8723D(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8723D_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8723D(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8723D(_Adapter, _PowerIndex, _RFPath, _Rate) + +#endif // (RTL8723D_SUPPORT == 0) + + +#if (RTL8703B_SUPPORT == 0) + +#define MAX_RX_DMA_BUFFER_SIZE_8703B 0x2800 // RX 10K + +#define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) + +#define TxDescriptorChecksum_8723D(_txDesc) + +#define SwLedOn_8703B(_Adapter, _pLed) 0 +#define SwLedOff_8703B(_Adapter, _pLed) 0 + +#define TxUsbAggregation8703BU(_Adapter, _queueId) + +#define SetWoWLANCAMEntry8703B(_Adapter) +#define HalSetFWWoWlanMode8703B(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8703B(_pAdapter, _bFuncEn) +#define H2CCmdAction8703B(_Adapter, _pBuf, _bufLen) 0 + +#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) + +#define TxDescriptorChecksum_8703B(_txDesc) + +#define Hal_InitEfuseVars_8703B(_pEfuseHal) +#define Hal_ReadTxPowerInfo8703B(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfuseSwitchToBank8703B(_pAdapter, _bank, _bPseudoTest) TRUE +#define Hal_EfusePowerSwitch8703B(_pAdapter, _bWrite, _PwrState) +#define Hal_EfusePowerSwitch8703B_TestChip(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8703B(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8703B(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8703B(_Adapter, _Type, _ScanOffloadEnable, _NLOEnable) +#define SetFwRemoteWakeCtrlCmd_8703B(_Adapter, _Enable) +#define SetFwInactivePSCmd_8703B(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8703B(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8703B(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define PHY_QueryBBReg8703B(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8703B(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8703B(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8703B(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8703B_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8703B(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8703B(_Adapter, _PowerIndex, _RFPath, _Rate) + +#define ex_halbtc8703b1ant_power_on_setting(btcoexist) +#define ex_halbtc8703b1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8703b1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8703b1ant_init_coex_dm(btcoexist) +#define ex_halbtc8703b1ant_ips_notify(btcoexist, type) +#define ex_halbtc8703b1ant_lps_notify(btcoexist, type) +#define ex_halbtc8703b1ant_scan_notify(btcoexist, type) +#define ex_halbtc8703b1ant_connect_notify(btcoexist, type) +#define ex_halbtc8703b1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8703b1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8703b1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8703b1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8703b1ant_halt_notify(btcoexist) +#define ex_halbtc8703b1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8703b1ant_ScoreBoardStatusNotify(btcoexist, tmp_buf, length) +#define ex_halbtc8703b1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8703b1ant_periodical(btcoexist) +#define ex_halbtc8703b1ant_display_coex_info(btcoexist) +#define ex_halbtc8703b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8703b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8703b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8703b1ant_display_ant_detection(btcoexist) + + +#endif // (RTL8703B_SUPPORT == 0) + +#if (RTL8188F_SUPPORT == 0) + +#define MAX_RX_DMA_BUFFER_SIZE_8188F 0x4000 // RX 10K +#define AVG_THERMAL_NUM_8188F 4 +#define RF_T_METER_8188F 0x42 +#define IQK_DELAY_TIME_8188F 25 + +#define SwLedOn_8188F(_Adapter, _pLed) 0 +#define SwLedOff_8188F(_Adapter, _pLed) 0 + +#define TxUsbAggregation8188FU(_Adapter, _queueId) + +#define SetWoWLANCAMEntry8188F(_Adapter) +#define HalSetFWWoWlanMode8188F(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8188F(_pAdapter, _bFuncEn) +#define H2CCmdAction8188F(_Adapter, _pBuf, _bufLen) 0 + +#define TxDescriptorChecksum_8188F(_txDesc) + +#define Hal_InitEfuseVars_8188F(_pEfuseHal) +#define Hal_ReadTxPowerInfo8188F(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfuseSwitchToBank8188F(_pAdapter, _bank, _bPseudoTest) TRUE +#define Hal_EfusePowerSwitch8188F(_pAdapter, _bWrite, _PwrState) +#define Hal_EfusePowerSwitch8188F_TestChip(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8188F(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8188F(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8188F(_Adapter, _Type, _ScanOffloadEnable, _NLOEnable) +#define SetFwRemoteWakeCtrlCmd_8188F(_Adapter, _Enable) +#define SetFwInactivePSCmd_8188F(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8188F(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8188F(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define PHY_QueryBBReg8188F(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8188F(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8188F(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8188F(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8188F_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8188F(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8188F(_Adapter, _PowerIndex, _RFPath, _Rate) + +#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) + +void PHY_IQCalibrate_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore + ); + +#endif // (RTL8188F_SUPPORT == 0) +#if (RTL8821B_SUPPORT == 0) + +#define MAX_RX_DMA_BUFFER_SIZE_8821B 0x6000 + +#define TxDescriptorChecksum_8821B(_txDesc) + +#define SwLedOn_8821B(_Adapter, _pLed) 0 +#define SwLedOff_8821B(_Adapter, _pLed) 0 + +#define TxUsbAggregation8821BU(_Adapter, _queueId) + +#define SetWoWLANCAMEntry8821B(_Adapter) +#define HalSetFWWoWlanMode8821B(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8821B(_pAdapter, _bFuncEn) +#define H2CCmdAction8821B(_Adapter, _pBuf, _bufLen) 0 + +#define SET_TX_DESC_USB_TXAGG_NUM_8821B(__pTxDesc, __Value) + +#define TxDescriptorChecksum_8821B(_txDesc) + +#define Hal_InitEfuseVars_8821B(_pEfuseHal) +#define Hal_ReadTxPowerInfo8821B(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfuseSwitchToBank8821B(_pAdapter, _bank, _bPseudoTest) TRUE +#define Hal_EfusePowerSwitch8821B(_pAdapter, _bWrite, _PwrState) +#define Hal_EfusePowerSwitch8821B_TestChip(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8821B(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8821B(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8821B(_Adapter, _Type, _ScanOffloadEnable, _NLOEnable) +#define SetFwRemoteWakeCtrlCmd_8821B(_Adapter, _Enable) +#define SetFwInactivePSCmd_8821B(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8821B(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8821B(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define PHY_QueryBBReg8821B(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8821B(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8821B(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8821B(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8821B_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8821B(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8821B(_Adapter, _PowerIndex, _RFPath, _Rate) + +#endif // (RTL8821B_SUPPORT == 0) + +#if (RTL8814A_SUPPORT == 0) + +#define REG_HSIMR_8814A 0 +#define REG_IQ_DUMP_8814A 0 +#define REG_PKTBUF_DBG_CTRL_8814A 0 +#define RX_STATUS_DESC_SIZE 0 +#define REG_SYS_FUNC_EN_8814A 0 + + +#define REG_RF_CTRL0_8814A 0x001F // 1 Byte +#define REG_RF_CTRL1_8814A 0x0020 // 1 Byte +#define REG_RF_CTRL3_8814A 0x0076 // 1 Byte + +#define H2C_8814A_RSSI_REPORT 0x42 +#define H2C_8814A_RA_PARA_ADJUST 0x47 +#define H2C_8814A_DYNAMIC_TX_PATH 0x48 +#define H2C_8814A_FW_TRACE_EN 0x49 + +#define REG_NDPA_OPT_CTRL_8814A 0x045F +#define REG_NDPA_RATE_8814A 0x045D + +#define TxDescriptorChecksum_8814A(_txDesc) + +#define SwLedOn_8814A(_Adapter, _pLed) 0 +#define SwLedOff_8814A(_Adapter, _pLed) 0 + +#define TxUsbAggregation8814AU(_Adapter, _queueId) + +#define SetWoWLANCAMEntry8814A(_Adapter) +#define HalSetFWWoWlanMode8814A(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8814A(_pAdapter, _bFuncEn) +#define H2CCmdAction8814A(_Adapter, _pBuf, _bufLen) 0 + +#define SET_TX_DESC_USB_TXAGG_NUM_8814A(__pTxDesc, __Value) + +#define TxDescriptorChecksum_8814A(_txDesc) + +#define Hal_InitEfuseVars_8814A(_pEfuseHal) +#define Hal_ReadTxPowerInfo8814A(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfuseSwitchToBank8814A(_pAdapter, _bank, _bPseudoTest) TRUE +#define Hal_EfusePowerSwitch8814A(_pAdapter, _bWrite, _PwrState) +#define Hal_EfusePowerSwitch8814A_TestChip(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8814A(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8814A(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8814A(_Adapter, _Type, _ScanOffloadEnable, _NLOEnable) +#define SetFwRemoteWakeCtrlCmd_8814A(_Adapter, _Enable) +#define SetFwInactivePSCmd_8814A(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8814A(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8814A(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define PHY_QueryBBReg8814A(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8814A(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8814A(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8814A(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8814A_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8814A(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8814A(_Adapter, _PowerIndex, _RFPath, _Rate) + +#endif // (RTL8821B_SUPPORT == 0) + + +#if (RTL8192E_SUPPORT == 0) + + +#define RX_DESC_SIZE_92EE 24 +#define REG_DARFRC_8192E 0x0430 +#define REG_NDPA_OPT_CTRL_8192E 0x045F + +#define REG_RXQ_TXBD_IDX_8192E 0x03B4 +#define rA_RSSIDump_92E 0xcb0 +#define rB_RSSIDump_92E 0xcb1 +#define rS1_RXevmDump_92E 0xcb2 +#define rS2_RXevmDump_92E 0xcb3 +#define rA_RXsnrDump_92E 0xcb4 +#define rB_RXsnrDump_92E 0xcb5 +#define rA_CfoShortDump_92E 0xcb6 +#define rB_CfoShortDump_92E 0xcb8 +#define rA_CfoLongDump_92E 0xcba +#define rB_CfoLongDump_92E 0xcbc + +#define HalDownloadRSVDPage8192EE(_Adapter) +#define Hal_DBIRead4Byte_8192EE(_Adapter, _Addr) 0 +#define Hal_DBIWrite4Byte_8192EE(_Adapter, _Addr, _Data) + +#define SwLedOn_8192E(_Adapter, _pLed) 0 +#define SwLedOff_8192E(_Adapter, _pLed) 0 + +#define SetWoWLANCAMEntry8192E(_Adapter) +#define HalSetFWWoWlanMode8192E(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8192E(_pAdapter, _bFuncEn) +#define H2CCmdAction8192E(_Adapter, _pBuf, _bufLen) 0 + +#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) + +#define TxDescriptorChecksum_8192E(_txDesc) +#define TxUsbAggregation8192E(_Adapter, _queueId) + +#define Hal_InitEfuseVars_8192E(_pEfuseHal) +#define Hal_ReadTxPowerInfo8192E(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfuseSwitchToBank8192E(_pAdapter, _bank, _bPseudoTest) TRUE +#define Hal_EfusePowerSwitch8192E(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8192E(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8192E(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8192E(_Adapter, _Type, _ScanOffloadEnable, _NLOEnable) +#define SetFwRemoteWakeCtrlCmd_8192E(_Adapter, _Enable) +#define SetFwInactivePSCmd_8192E(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8192E(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8192E(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define PHY_QueryBBReg8192E(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8192E(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8192E(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8192E(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8192E_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8192E(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8192E(_Adapter, _PowerIndex, _RFPath, _Rate) + +#define ex_halbtc8192e1ant_power_on_setting(btcoexist) +#define ex_halbtc8192e1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8192e1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8192e1ant_init_coex_dm(btcoexist) +#define ex_halbtc8192e1ant_ips_notify(btcoexist, type) +#define ex_halbtc8192e1ant_lps_notify(btcoexist, type) +#define ex_halbtc8192e1ant_scan_notify(btcoexist, type) +#define ex_halbtc8192e1ant_connect_notify(btcoexist, type) +#define ex_halbtc8192e1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8192e1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8192e1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8192e1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8192e1ant_halt_notify(btcoexist) +#define ex_halbtc8192e1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8192e1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8192e1ant_periodical(btcoexist) +#define ex_halbtc8192e1ant_display_coex_info(btcoexist) +#define ex_halbtc8192e1ant_dbg_control(btcoexist, op_code, op_len, pdata) + +#define ex_halbtc8192e2ant_power_on_setting(btcoexist) +#define ex_halbtc8192e2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8192e2ant_init_coex_dm(btcoexist) +#define ex_halbtc8192e2ant_ips_notify(btcoexist, type) +#define ex_halbtc8192e2ant_lps_notify(btcoexist, type) +#define ex_halbtc8192e2ant_scan_notify(btcoexist, type) +#define ex_halbtc8192e2ant_connect_notify(btcoexist, type) +#define ex_halbtc8192e2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8192e2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8192e2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8192e2ant_halt_notify(btcoexist) +#define ex_halbtc8192e2ant_periodical(btcoexist) +#define ex_halbtc8192e2ant_display_coex_info(btcoexist) + +#endif // (RTL8192E_SUPPORT == 0) + + +#if (RTL8188E_SUPPORT == 0) + +#define H2C_88E_RSSI_REPORT 0x42 + +#define PCIE_8188E_HWDESC_HEADER_LEN 32//sizeof(TX_DESC_8192SE) + +#define PrepareRxDesc8188EE(_Adapter, _LengthArray) RT_STATUS_FAILURE +#define FreeRxDesc8188EE(_Adapter) +#define ResetRxDesc8188EE(_Adapter, _LengthArray) RT_STATUS_FAILURE +#define ReturnRxDescBuffer8188EE(_Adapter, _QueueID, _index, _buffer) +#define IsRxDescFilledWithPacket8188EE(_Adapter, _QueueID, _index, _uBufferAddress) FALSE + +#define SwLedOn_8188E(_Adapter, _pLed) 0 +#define SwLedOff_8188E(_Adapter, _pLed) 0 + +#define TxUsbAggregation8188E(_Adapter, _queueId) + +#define ForceLeaveHwClock32K8188E(_Adapter) + +#define SetWoWLANCAMEntry8188E(_Adapter) +#define HalSetFWWoWlanMode8188E(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8188E(_pAdapter, _bFuncEn) +#define H2CCmdAction8188E(_Adapter, _pBuf, _bufLen) 0 +#define SetBcnCtrlReg_8188E(_Adapter, _SetBits, _ClearBits) + +#define SET_TX_DESC_USB_TXAGG_NUM_88E(__pTxDesc, __Value) +#define TxDescriptorChecksum_8188E(_txDesc) + +#define Hal_InitEfuseVars_8188E(_pEfuseHal) +#define Hal_ReadTxPowerInfo88E(_Adapter, _PROMContent, _AutoLoadFail) + +#define SetFwGlobalInfoCmd_8188E(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8188E(_Adapter, _bEnabled) +#define SetFwScanOffloadCtrlCmd_8188E(_Adapter, _Type, _ScanOffloadEnable) +#define SetFwRemoteWakeCtrlCmd_8188E(_Adapter, _Enable) +#define SetFwInactivePSCmd_8188E(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd88E(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload88E(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define PHY_QueryBBReg8188E(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8188E(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8188E(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8188E(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8188E_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8188E(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8188E(_Adapter, _PowerIndex, _RFPath, _Rate) + +#define SDIO_8188E_DUMMY_OFFSET 1 // Reseved for Early Mode information. +#define SDIO_92C_DUMMY_UNIT 8 +#define SDIO_8188E_ALL_DUMMY_LENGTH (SDIO_8188E_DUMMY_OFFSET * SDIO_92C_DUMMY_UNIT) +#define SDIO_8188E_HWDESC_HEADER_LEN (TX_DESC_SIZE + SDIO_8188E_ALL_DUMMY_LENGTH) + + +#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_SMIC_SERIES(__Adapter))?((GET_HAL_DATA(__Adapter)->bIsMPChip) ? 0x2400 : 0x1C00):0x3A00) + + +#endif // (RTL8188E_SUPPORT == 0) + +#if (RTL8812A_SUPPORT == 0) + +#define REG_RXDMA_AGG_PG_TH_8812A 0x280 +#define REG_APS_FSMCO_8812A 0x0004 +#define REG_MACID_8812A 0x0610 +#define REG_TRXDMA_CTRL_8812A 0x010C +#define REG_TXDMA_OFFSET_CHK_8812A 0x020C +#define REG_DUAL_TSF_RST_8812A 0x0553 +#define REG_SECONDARY_CCA_CTRL_8812A 0x577 + +#define REG_MULTI_FUNC_CTRL_8812A 0x0068 + +#define REG_CR_8812A 0x0100 +#define REG_FWHW_TXQ_CTRL_8812A 0x0420 +#define REG_TDECTRL_8812A 0x0208 +#define REG_MACID1_8812A 0x0700 +#define REG_BSSID1_8812A 0x0708 +#define REG_BFMEE_SEL_8812A 0x0714 +#define REG_SND_PTCL_CTRL_8812A 0x0718 +#define REG_TXBF_CTRL_8812A 0x042C +#define REG_BFMER0_INFO_8812A 0x06E4 +#define REG_BFMER1_INFO_8812A 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC +#define REG_TXPKT_EMPTY_8812A 0x041A +#define REG_PCIE_CTRL_REG_8812A 0x0300 +#define REG_TXPAUSE_8812A 0x0522 +#define REG_SCH_TXCMD_8812A 0x05F8 +#define REG_RXDMA_CONTROL_8812A 0x0286 // Control the RX DMA. +#define REG_SYS_CLKR_8812A 0x0008 // 2 Byte +#define REG_AFE_PLL_CTRL_8812A 0x0028 // 4 Byte + +#define REG_NDPA_OPT_CTRL_8812A 0x045F + +#define EFUSE_MAX_SECTION_JAGUAR 64 +#define HWSET_MAX_SIZE_JAGUAR 512 + +#define EFUSE_PROTECT_BYTES_BANK_JAGUAR 16 +#define EFUSE_MAX_SECTION_JAGUAR 64 +#define EFUSE_REAL_CONTENT_LEN_JAGUAR 512 +#define EFUSE_MAP_LEN_JAGUAR 512 + + + +#define REG_RF_CTRL_8812A 0x001F // 1 Byte +#define REG_OPT_CTRL_8812A 0x0074 + +#define rDMA_trigger_Jaguar2 0x95C // ADC sample mode +#define rDMA_trigger_Jaguar2 0x95C // ADC sample mode + + +#define rA_SIRead_Jaguar 0xd08 // RF readback with SI +#define rB_SIRead_Jaguar 0xd48 // RF readback with SI +#define rA_PIRead_Jaguar 0xd04 // RF readback with PI +#define rB_PIRead_Jaguar 0xd44 // RF readback with PI + +#define rA_LSSIWrite_Jaguar 0xc90 // RF write addr +#define rB_LSSIWrite_Jaguar 0xe90 // RF write addr +#define bLSSIWrite_data_Jaguar 0x000fffff +#define bLSSIWrite_addr_Jaguar 0x0ff00000 + +#define rC_PIRead_Jaguar2 0xd84 // RF readback with PI +#define rD_PIRead_Jaguar2 0xdC4 // RF readback with PI +#define rC_SIRead_Jaguar2 0xd88 // RF readback with SI +#define rD_SIRead_Jaguar2 0xdC8 // RF readback with SI +#define rC_LSSIWrite_Jaguar2 0x1890 // RF write addr +#define rD_LSSIWrite_Jaguar2 0x1A90 // RF write addr + +#define rHSSIRead_Jaguar 0x8b0 // RF read addr + +#define HalDownloadRSVDPage8812AE(_Adapter) +#define Hal_DBIRead4Byte_8812AE(_Adapter, _Addr) 0 +#define Hal_DBIWrite4Byte_8812AE(_Adapter, _Addr, _Data) +#define Hal_DBIRead4Byte_8812AE(_Adapter, _Addr) 0 +#define Hal_DBIWrite4Byte_8812AE(_Adapter, _Addr, _Data) + +#define SwLedOn_8812A(_Adapter, _pLed) 0 +#define SwLedOff_8812A(_Adapter, _pLed) 0 + +#define SetWoWLANCAMEntry8812A(_Adapter) +#define HalSetFWWoWlanMode8812A(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8812A(_pAdapter, _bFuncEn) +#define H2CCmdAction8812A(_Adapter, _pBuf, _bufLen) 0 + +#define Hal_InitEfuseVars_8812A(_pEfuseHal) +#define Hal_ReadTxPowerInfo_8812A(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfusePgPacketExceptionHandle_8812A(_pAdapter, _ErrOffset) 0 +#define Hal_EfusePowerSwitch8812A(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8812A(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8812A(_Adapter, _bEnabled) +#define SetFwRemoteWakeCtrlCmd_8812A(_Adapter, _Enable) +#define SetFwInactivePSCmd_8812A(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8812A(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8812A(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define TxDescriptorChecksum_8812(_txDesc) + +#define PHY_QueryBBReg8812(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8812(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8812(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8812(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8812A_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8812A(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8812A(_Adapter, _PowerIndex, _RFPath, _Rate) +#define PHY_GetTxBBSwing_8812A(_Adapter, _Band, _RFPath) 0 + +#define ex_halbtc8812a1ant_power_on_setting(btcoexist) +#define ex_halbtc8812a1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8812a1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8812a1ant_init_coex_dm(btcoexist) +#define ex_halbtc8812a1ant_ips_notify(btcoexist, type) +#define ex_halbtc8812a1ant_lps_notify(btcoexist, type) +#define ex_halbtc8812a1ant_scan_notify(btcoexist, type) +#define ex_halbtc8812a1ant_connect_notify(btcoexist, type) +#define ex_halbtc8812a1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8812a1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8812a1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8812a1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8812a1ant_halt_notify(btcoexist) +#define ex_halbtc8812a1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8812a1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8812a1ant_periodical(btcoexist) +#define ex_halbtc8812a1ant_dbg_control(btcoexist, op_code, op_len, pdata) +#define ex_halbtc8812a1ant_display_coex_info(btcoexist) + +#define ex_halbtc8812a2ant_power_on_setting(btcoexist) +#define ex_halbtc8812a2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8812a2ant_init_coex_dm(btcoexist) +#define ex_halbtc8812a2ant_ips_notify(btcoexist, type) +#define ex_halbtc8812a2ant_lps_notify(btcoexist, type) +#define ex_halbtc8812a2ant_scan_notify(btcoexist, type) +#define ex_halbtc8812a2ant_connect_notify(btcoexist, type) +#define ex_halbtc8812a2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8812a2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8812a2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8812a2ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8812a2ant_halt_notify(btcoexist) +#define ex_halbtc8812a2ant_periodical(btcoexist) +#define ex_halbtc8812a2ant_display_coex_info(btcoexist) +#define ex_halbtc8812a2ant_dbg_control(btcoexist, op_code, op_len, pdata) + + + +#endif // (RTL8812A_SUPPORT == 0) + +#if (RTL8821A_SUPPORT == 0) + +#define EFUSE_MAX_BANK_8821A 3 +#define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) +#define DRIVER_EARLY_INT_TIME_8821 0x05 + +#define FillH2CCommand8821A(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) 0 + + +#define Hal_EfuseSwitchToBank8821A(_pAdapter, _bank, _bPseudoTest) TRUE + +#define HalDownloadRSVDPage8821AE(_Adapter) +#define Hal_DBIRead4Byte_8821AE(_Adapter, _Addr) 0 +#define Hal_DBIWrite4Byte_8821AE(_Adapter, _Addr, _Data) +#define Hal_DBIRead4Byte_8821AE(_Adapter, _Addr) 0 +#define Hal_DBIWrite4Byte_8821AE(_Adapter, _Addr, _Data) + +#define SwLedOn_8821A(_Adapter, _pLed) 0 +#define SwLedOff_8821A(_Adapter, _pLed) 0 + +#define SetWoWLANCAMEntry8821A(_Adapter) +#define HalSetFWWoWlanMode8821A(_pAdapter, _bFuncEn) RT_STATUS_SUCCESS +#define HalSetFwKeepAliveCmd8821A(_pAdapter, _bFuncEn) +#define H2CCmdAction8821A(_Adapter, _pBuf, _bufLen) 0 + +#define Hal_InitEfuseVars_8821A(_pEfuseHal) +#define Hal_ReadTxPowerInfo_8821A(_Adapter, _PROMContent, _AutoLoadFail) +#define Hal_EfusePgPacketExceptionHandle_8821A(_pAdapter, _ErrOffset) 0 +#define Hal_EfusePowerSwitch8821A(_pAdapter, _bWrite, _PwrState) + +#define SetFwGlobalInfoCmd_8821A(_Adapter) +#define SetFwDisconnectDecisionCtrlCmd_8821A(_Adapter, _bEnabled) +#define SetFwRemoteWakeCtrlCmd_8821A(_Adapter, _Enable) +#define SetFwInactivePSCmd_8821A(_Adapter, _Enable, _bActiveWakeup, _bForceClkOff) +#define FillH2CCmd8821A(_Adapter, _ElementID, _CmdLen, _pCmdBuffer) +#define FirmwareDownload8821A(_Adapter, _bUsedWoWLANFw) RT_STATUS_SUCCESS + +#define TxDescriptorChecksum_8821(_txDesc) + +#define PHY_QueryBBReg8821A(_Adapter, _RegAddr, _BitMask) 0 +#define PHY_SetBBReg8821A(_Adapter, _RegAddr, _BitMask, _Data) +#define PHY_QueryRFReg8821A(_Adapter, _eRFPath, _RegAddr, _BitMask) 0 +#define PHY_SetRFReg8821A(_Adapter, _eRFPath, _RegAddr, _BitMask, _Data) +#define phy_BB8821A_Config_ParaFile(_Adapter) RT_STATUS_SUCCESS +#define PHY_GetTxPowerIndex_8821A(_pAdapter, _RFPath, _Rate, _BandWidth, _Channel) 0 +#define PHY_SetTxPowerIndex_8821A(_Adapter, _PowerIndex, _RFPath, _Rate) +#define PHY_GetTxBBSwing_8821A(_Adapter, _Band, _RFPath) 0 + +#define ex_halbtc8821a1ant_power_on_setting(btcoexist) +#define ex_halbtc8821a1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8821a1ant_init_coex_dm(btcoexist) +#define ex_halbtc8821a1ant_ips_notify(btcoexist, type) +#define ex_halbtc8821a1ant_lps_notify(btcoexist, type) +#define ex_halbtc8821a1ant_scan_notify(btcoexist, type) +#define ex_halbtc8821a1ant_connect_notify(btcoexist, type) +#define ex_halbtc8821a1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8821a1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8821a1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8821a1ant_halt_notify(btcoexist) +#define ex_halbtc8821a1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8821a1ant_periodical(btcoexist) +#define ex_halbtc8821a1ant_display_coex_info(btcoexist) + +#define ex_halbtc8821a2ant_power_on_setting(btcoexist) +#define ex_halbtc8821a2ant_pre_load_firmware(btcoexist) +#define ex_halbtc8821a2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8821a2ant_init_coex_dm(btcoexist) +#define ex_halbtc8821a2ant_ips_notify(btcoexist, type) +#define ex_halbtc8821a2ant_lps_notify(btcoexist, type) +#define ex_halbtc8821a2ant_scan_notify(btcoexist, type) +#define ex_halbtc8821a2ant_connect_notify(btcoexist, type) +#define ex_halbtc8821a2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8821a2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8821a2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8821a2ant_halt_notify(btcoexist) +#define ex_halbtc8821a2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8821a2ant_periodical(btcoexist) +#define ex_halbtc8821a2ant_display_coex_info(btcoexist) + +#define ex_halbtc8821aCsr2ant_power_on_setting(btcoexist) +#define ex_halbtc8821aCsr2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8821aCsr2ant_init_coex_dm(btcoexist) +#define ex_halbtc8821aCsr2ant_ips_notify(btcoexist, type) +#define ex_halbtc8821aCsr2ant_lps_notify(btcoexist, type) +#define ex_halbtc8821aCsr2ant_scan_notify(btcoexist, type) +#define ex_halbtc8821aCsr2ant_connect_notify(btcoexist, type) +#define ex_halbtc8821aCsr2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8821aCsr2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8821aCsr2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8821aCsr2ant_halt_notify(btcoexist) +#define ex_halbtc8821aCsr2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8821aCsr2ant_periodical(btcoexist) +#define ex_halbtc8821aCsr2ant_display_coex_info(btcoexist) + +#define SDIO_8821_DUMMY_UNIT 8 +#define SDIO_8821_DUMMY_OFFSET 1 +#define SDIO_8821_ALL_DUMMY_LENGTH SDIO_8821_DUMMY_OFFSET * SDIO_8821_DUMMY_UNIT +#define HWDESC_HEADER_LEN_SDIO_8821 40 +#define SDIO_8821_HWDESC_HEADER_LEN (HWDESC_HEADER_LEN_SDIO_8821 + SDIO_8821_ALL_DUMMY_LENGTH) // 8byte dummy + + +#endif // (RTL8821A_SUPPORT == 0) + +#if (RTL8723B_SUPPORT == 0) + +#define EFUSE_REAL_CONTENT_LEN_8723B 512 +#define AVAILABLE_EFUSE_ADDR_8723B(addr) (addr < EFUSE_REAL_CONTENT_LEN_8723B) + + +BOOLEAN +Hal_EfuseSwitchToBank8723B( + IN PADAPTER pAdapter, + IN u1Byte bank, + IN BOOLEAN bPseudoTest + ); + +VOID +Hal_EfusePowerSwitch8723B( + IN PADAPTER pAdapter, + IN UINT8 bWrite, + IN UINT8 PwrState + ); + +VOID +Hal_EfusePowerSwitch8723B_TestChip( + IN PADAPTER pAdapter, + IN UINT8 bWrite, + IN UINT8 PwrState + ); + +VOID +Hal_InitEfuseVars_8723B( + IN PEFUSE_HAL pEfuseHal + ); + +VOID +HalSetFcsAdjustTsf_8723B( + IN PADAPTER Adapter + ); + +VOID +SetWoWLANCAMEntry8723B( + PADAPTER Adapter + ); + +VOID +SetFwGlobalInfoCmd_8723B( + IN PADAPTER Adapter + ); + +RT_STATUS +HalSetFWWoWlanMode8723B( + IN PADAPTER pAdapter, + IN BOOLEAN bFuncEn + ); + +VOID +HalSetFwKeepAliveCmd8723B( + IN PADAPTER pAdapter, + IN BOOLEAN bFuncEn + ); + +VOID +SetFwScanOffloadCtrlCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte Type, + IN u1Byte ScanOffloadEnable, + IN u1Byte NLOEnable + ); + +VOID +SetFwDisconnectDecisionCtrlCmd_8723B( + IN PADAPTER Adapter, + IN BOOLEAN bEnabled + ); + +VOID +SetFwRemoteWakeCtrlCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte Enable + ); + +VOID +SetFwInactivePSCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte Enable, + IN BOOLEAN bActiveWakeup, + IN BOOLEAN bForceClkOff + ); + +VOID +SetFwWiFiCalibrationCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte u1Enable + ); + +VOID +FillH2CCmd8723B( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer + ); + +u4Byte +FillH2CCommand8723B( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer + ); + +u4Byte +FW8723B_FillH2cCommand( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer + ); + +RT_STATUS +FirmwareDownload8723B( + IN PADAPTER Adapter, + IN BOOLEAN bUsedWoWLANFw + ); + +VOID +HalDownloadRSVDPage8723BE( + IN PADAPTER Adapter + ); + +u1Byte +hal_DBIRead_8723BE( + IN PADAPTER Adapter, + IN u2Byte Addr + ); + +VOID +hal_DBIWrite_8723BE( + IN PADAPTER Adapter, + IN u2Byte Addr, + IN u1Byte Data + ); + +VOID +Hal_ReadTxPowerInfo8723B( + IN PADAPTER Adapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_Set8723bAntPath( + IN PADAPTER pAdapter, + IN BOOLEAN bAntennaAux, //For 1-Ant--> 1: Antenna at S0, 0: Antenna at S1. Set 0 for 2-Ant + IN BOOLEAN bExtSwitch, // 1: Ext Switch (SPDT) exist on module, 0: no Ext Switch (SPDT) exist on module + IN BOOLEAN bTwoAntenna, // 1: 2-Antenna, 0:1-Antenna + IN u1Byte antennaPos, //Set Antenna Pos, For 1-Ant: BTC_ANT_PATH_WIFI, BTC_ANT_PATH_BT, BTC_ANT_PATH_PTA, For 2-Ant:BTC_ANT_WIFI_AT_MAIN, BTC_ANT_WIFI_AT_Aux + IN u1Byte wifiState //BTC_WIFI_STAT_INIT, BTC_WIFI_STAT_IQK, BTC_WIFI_STAT_NORMAL_OFF, BTC_WIFI_STAT_MP_OFF, BTC_WIFI_STAT_NORMAL, BTC_WIFI_STAT_ANT_DIV + ); + +#define ex_halbtc8723b1ant_power_on_setting(btcoexist) +#define ex_halbtc8723b1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8723b1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8723b1ant_init_coex_dm(btcoexist) +#define ex_halbtc8723b1ant_ips_notify(btcoexist, type) +#define ex_halbtc8723b1ant_lps_notify(btcoexist, type) +#define ex_halbtc8723b1ant_scan_notify(btcoexist, type) +#define ex_halbtc8723b1ant_connect_notify(btcoexist, type) +#define ex_halbtc8723b1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8723b1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8723b1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8723b1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8723b1ant_halt_notify(btcoexist) +#define ex_halbtc8723b1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8723b1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8723b1ant_periodical(btcoexist) +#define ex_halbtc8723b1ant_display_coex_info(btcoexist) +#define ex_halbtc8723b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8723b1ant_display_ant_detection(btcoexist) + +#define ex_halbtc8723b2ant_power_on_setting(btcoexist) +#define ex_halbtc8723b2ant_pre_load_firmware(btcoexist) +#define ex_halbtc8723b2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8723b2ant_init_coex_dm(btcoexist) +#define ex_halbtc8723b2ant_ips_notify(btcoexist, type) +#define ex_halbtc8723b2ant_lps_notify(btcoexist, type) +#define ex_halbtc8723b2ant_scan_notify(btcoexist, type) +#define ex_halbtc8723b2ant_connect_notify(btcoexist, type) +#define ex_halbtc8723b2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8723b2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8723b2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8723b2ant_halt_notify(btcoexist) +#define ex_halbtc8723b2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8723b2ant_periodical(btcoexist) +#define ex_halbtc8723b2ant_display_coex_info(btcoexist) + +u4Byte +PHY_QueryBBReg8723B( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +PHY_SetBBReg8723B( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +PHY_QueryRFReg8723B( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +PHY_SetRFReg8723B( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +RT_STATUS +PHY_RF6052_Config_8723B( + IN PADAPTER Adapter + ); + +VOID +PHY_RF6052SetBandwidth8723B( + IN PADAPTER Adapter, + IN CHANNEL_WIDTH Bandwidth + ); + +RT_STATUS +phy_BB8723B_Config_ParaFile( + IN PADAPTER Adapter + ); + +u1Byte +PHY_GetTxPowerIndex_8723B( + IN PADAPTER Adapter, + IN u1Byte RFPath, + IN u1Byte Rate, + IN CHANNEL_WIDTH BandWidth, + IN u1Byte Channel + ); + +VOID +PHY_SetTxPowerIndex_8723B( + IN PADAPTER Adapter, + IN u4Byte PowerIndex, + IN u1Byte RFPath, + IN u1Byte Rate + ); + +u4Byte +PHY_GetTxBBSwing_8723B( + IN PADAPTER Adapter, + IN BAND_TYPE Band, + IN u1Byte RFPath + ); + +u4Byte +H2CCmdAction8723B( + IN PADAPTER Adapter, + IN PVOID pBuf, + IN u2Byte bufLen + ); + +VOID +TxDescriptorChecksum_8723B( + IN pu1Byte txDesc + ); + + +#define MAX_RX_DMA_BUFFER_SIZE_8723B 0x2800 // RX 10K +#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) + +VOID +SwLedOn_8723B( + IN PADAPTER Adapter, + IN PLED_SDIO pLed + ); + +VOID +SwLedOff_8723B( + IN PADAPTER Adapter, + IN PLED_SDIO pLed + ); + +#endif // (RTL8723B_SUPPORT == 0) + + + diff --git a/network/wlan/WDI/HAL/HalJaguarPhyReg.h b/network/wlan/WDI/HAL/HalJaguarPhyReg.h new file mode 100644 index 00000000..ac41eff9 --- /dev/null +++ b/network/wlan/WDI/HAL/HalJaguarPhyReg.h @@ -0,0 +1,399 @@ +#ifndef __INC_HALJAGUARPHYREG_H +#define __INC_HALJAGUARPHYREG_H + + +/*--------------------------Define Parameters-------------------------------*/ + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + + +// BB Register Definition +#define rCCAonSec_Jaguar 0x838 +#define rPwed_TH_Jaguar 0x830 +#define rL1_Weight_Jaguar 0x840 + +// BW and sideband setting +#define rBWIndication_Jaguar 0x834 +#define rL1PeakTH_Jaguar 0x848 +#define rRFMOD_Jaguar 0x8ac //RF mode + +#define rADC_Buf_160_Clk_Jaguar 0x8c4 +#define rADC_Buf_40_Clk_Jaguar2 0x8c8 + +#define bRFMOD_Jaguar 0xc3 +#define rCCK_System_Jaguar 0xa00 // for cck sideband +#define bCCK_System_Jaguar 0x10 + +// Block & Path enable +#define rOFDMCCKEN_Jaguar 0x808 // OFDM/CCK block enable +#define bOFDMEN_Jaguar 0x20000000 +#define bCCKEN_Jaguar 0x10000000 +#define rRxPath_Jaguar 0x808 // Rx antenna +#define bRxPath_Jaguar 0xff +#define rTxPath_Jaguar 0x80c // Tx antenna +#define bTxPath_Jaguar 0x0fffffff +#define rCCK_RX_Jaguar 0xa04 // for cck rx path selection +#define bCCK_RX_Jaguar 0x0c000000 +#define rVhtlen_Use_Lsig_Jaguar 0x8c3 // Use LSIG for VHT length + +#define rRxPath_Jaguar2 0xa04 // Rx antenna +#define rTxAnt_1Nsts_Jaguar2 0x93c // Tx antenna for 1Nsts +#define rTxAnt_23Nsts_Jaguar2 0x940 // Tx antenna for 2Nsts and 3Nsts + + +// RF read/write-related +#define rHSSIRead_Jaguar 0x8b0 // RF read addr +#define bHSSIRead_addr_Jaguar 0xff +#define bHSSIRead_trigger_Jaguar 0x100 +#define rA_PIRead_Jaguar 0xd04 // RF readback with PI +#define rB_PIRead_Jaguar 0xd44 // RF readback with PI +#define rA_SIRead_Jaguar 0xd08 // RF readback with SI +#define rB_SIRead_Jaguar 0xd48 // RF readback with SI +#define rRead_data_Jaguar 0xfffff +#define rA_LSSIWrite_Jaguar 0xc90 // RF write addr +#define rB_LSSIWrite_Jaguar 0xe90 // RF write addr +#define bLSSIWrite_data_Jaguar 0x000fffff +#define bLSSIWrite_addr_Jaguar 0x0ff00000 + +#define rC_PIRead_Jaguar2 0xd84 // RF readback with PI +#define rD_PIRead_Jaguar2 0xdC4 // RF readback with PI +#define rC_SIRead_Jaguar2 0xd88 // RF readback with SI +#define rD_SIRead_Jaguar2 0xdC8 // RF readback with SI +#define rC_LSSIWrite_Jaguar2 0x1890 // RF write addr +#define rD_LSSIWrite_Jaguar2 0x1A90 // RF write addr + + +// NBI & CSI Mask setting +#define rCSI_Mask_Setting1_Jaguar 0x874 +#define rCSI_Fix_Mask0_Jaguar 0x880 +#define rCSI_Fix_Mask1_Jaguar 0x884 +#define rCSI_Fix_Mask2_Jaguar 0x888 +#define rCSI_Fix_Mask3_Jaguar 0x88c +#define rCSI_Fix_Mask4_Jaguar 0x890 +#define rCSI_Fix_Mask5_Jaguar 0x894 +#define rCSI_Fix_Mask6_Jaguar 0x898 +#define rCSI_Fix_Mask7_Jaguar 0x89c +#define rNBI_Setting_Jaguar 0x87c + + +// YN: mask the following register definition temporarily +//#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 + +//#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +//#define rFPGA0_XCD_RFInterfaceSW 0x874 + +//#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +//#define rFPGA0_XCD_RFParameter 0x87c + +//#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +//#define rFPGA0_AnalogParameter2 0x884 +//#define rFPGA0_AnalogParameter3 0x888 +//#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy +//#define rFPGA0_AnalogParameter4 0x88c + + +// CCK TX scaling +#define rCCK_TxFilter1_Jaguar 0xa20 +#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 +#define bCCK_TxFilter1_C1_Jaguar 0xff000000 +#define rCCK_TxFilter2_Jaguar 0xa24 +#define bCCK_TxFilter2_C2_Jaguar 0x000000ff +#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 +#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 +#define bCCK_TxFilter2_C5_Jaguar 0xff000000 +#define rCCK_TxFilter3_Jaguar 0xa28 +#define bCCK_TxFilter3_C6_Jaguar 0x000000ff +#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 + + +// YN: mask the following register definition temporarily +//#define rPdp_AntA 0xb00 +//#define rPdp_AntA_4 0xb04 +//#define rConfig_Pmpd_AntA 0xb28 +//#define rConfig_AntA 0xb68 +//#define rConfig_AntB 0xb6c +//#define rPdp_AntB 0xb70 +//#define rPdp_AntB_4 0xb74 +//#define rConfig_Pmpd_AntB 0xb98 +//#define rAPK 0xbd8 + +// RXIQC +#define rA_RxIQC_AB_Jaguar 0xc10 //RxIQ imblance matrix coeff. A & B +#define rA_RxIQC_CD_Jaguar 0xc14 //RxIQ imblance matrix coeff. C & D +#define rA_TxScale_Jaguar 0xc1c // Pah_A TX scaling factor +#define rB_TxScale_Jaguar 0xe1c // Path_B TX scaling factor +#define rB_RxIQC_AB_Jaguar 0xe10 //RxIQ imblance matrix coeff. A & B +#define rB_RxIQC_CD_Jaguar 0xe14 //RxIQ imblance matrix coeff. C & D +#define b_RxIQC_AC_Jaguar 0x02ff // bit mask for IQC matrix element A & C +#define b_RxIQC_BD_Jaguar 0x02ff0000 // bit mask for IQC matrix element A & C + +#define rC_TxScale_Jaguar2 0x181c // Pah_C TX scaling factor +#define rD_TxScale_Jaguar2 0x1A1c // Path_D TX scaling factor +#define rRF_TxGainOffset 0x55 + +// DIG-related +#define rA_IGI_Jaguar 0xc50 // Initial Gain for path-A +#define rB_IGI_Jaguar 0xe50 // Initial Gain for path-B +#define rC_IGI_Jaguar2 0x1850 // Initial Gain for path-C +#define rD_IGI_Jaguar2 0x1A50 // Initial Gain for path-D + +#define rOFDM_FalseAlarm1_Jaguar 0xf48 // counter for break +#define rOFDM_FalseAlarm2_Jaguar 0xf4c // counter for spoofing +#define rCCK_FalseAlarm_Jaguar 0xa5c // counter for cck false alarm +#define b_FalseAlarm_Jaguar 0xffff +#define rCCK_CCA_Jaguar 0xa08 // cca threshold + +#define bCCK_CCA_Jaguar 0x00ff0000 + +// Tx Power Ttraining-related +#define rA_TxPwrTraing_Jaguar 0xc54 +#define rB_TxPwrTraing_Jaguar 0xe54 + +// Report-related +#define rOFDM_ShortCFOAB_Jaguar 0xf60 +#define rOFDM_LongCFOAB_Jaguar 0xf64 +#define rOFDM_EndCFOAB_Jaguar 0xf70 +#define rOFDM_AGCReport_Jaguar 0xf84 +#define rOFDM_RxSNR_Jaguar 0xf88 +#define rOFDM_RxEVMCSI_Jaguar 0xf8c +#define rOFDM_SIGReport_Jaguar 0xf90 + +// Misc functions +#define rEDCCA_Jaguar 0x8a4 // EDCCA +#define bEDCCA_Jaguar 0xffff +#define rAGC_table_Jaguar 0x82c // AGC tabel select +#define bAGC_table_Jaguar 0x3 +#define b_sel5g_Jaguar 0x1000 // sel5g +#define b_LNA_sw_Jaguar 0x8000 // HW/WS control for LNA +#define rFc_area_Jaguar 0x860 // fc_area +#define bFc_area_Jaguar 0x1ffe000 +#define rSingleTone_ContTx_Jaguar 0x914 + +#define rAGC_table_Jaguar2 0x958 // AGC tabel select +#define rDMA_trigger_Jaguar2 0x95C // ADC sample mode + + +// RFE +#define rA_RFE_Pinmux_Jaguar 0xcb0 // Path_A RFE cotrol pinmux +#define rB_RFE_Pinmux_Jaguar 0xeb0 // Path_B RFE control pinmux +#define rA_RFE_Inv_Jaguar 0xcb4 // Path_A RFE cotrol +#define rB_RFE_Inv_Jaguar 0xeb4 // Path_B RFE control +#define rA_RFE_Jaguar 0xcb8 // Path_A RFE cotrol +#define rB_RFE_Jaguar 0xeb8 // Path_B RFE control +#define r_ANTSEL_SW_Jaguar 0x900 // ANTSEL SW Control +#define bMask_RFEInv_Jaguar 0x3ff00000 +#define bMask_AntselPathFollow_Jaguar 0x00030000 + +#define rC_RFE_Pinmux_Jaguar 0x18B4 // Path_C RFE cotrol pinmux +#define rD_RFE_Pinmux_Jaguar 0x1AB4 // Path_D RFE cotrol pinmux +#define rA_RFE_Sel_Jaguar2 0x1990 + + + +// TX AGC +#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 +#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 +#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 +#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c +#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 +#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 +#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 +#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c +#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 +#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 +#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 +#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c +#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 +#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 +#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 +#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c +#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 +#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 +#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 +#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c +#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 +#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 +#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 +#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c +#define bTxAGC_byte0_Jaguar 0xff +#define bTxAGC_byte1_Jaguar 0xff00 +#define bTxAGC_byte2_Jaguar 0xff0000 +#define bTxAGC_byte3_Jaguar 0xff000000 + + +// TX AGC +#define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20 +#define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24 +#define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28 +#define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c +#define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30 +#define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34 +#define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38 +#define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8 +#define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc +#define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c +#define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40 +#define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44 +#define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48 +#define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c +#define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0 +#define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4 +#define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8 +#define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20 +#define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24 +#define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28 +#define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c +#define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30 +#define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34 +#define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38 +#define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8 +#define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc +#define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c +#define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40 +#define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44 +#define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48 +#define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c +#define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0 +#define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4 +#define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8 +#define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820 +#define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824 +#define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828 +#define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c +#define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830 +#define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834 +#define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838 +#define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8 +#define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc +#define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c +#define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840 +#define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844 +#define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848 +#define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c +#define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0 +#define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4 +#define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8 +#define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20 +#define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24 +#define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28 +#define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c +#define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30 +#define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34 +#define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38 +#define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8 +#define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc +#define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c +#define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40 +#define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44 +#define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48 +#define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c +#define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0 +#define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4 +#define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8 +// IQK YN: temporaily mask this part +//#define rFPGA0_IQK 0xe28 +//#define rTx_IQK_Tone_A 0xe30 +//#define rRx_IQK_Tone_A 0xe34 +//#define rTx_IQK_PI_A 0xe38 +//#define rRx_IQK_PI_A 0xe3c + +//#define rTx_IQK 0xe40 +//#define rRx_IQK 0xe44 +//#define rIQK_AGC_Pts 0xe48 +//#define rIQK_AGC_Rsp 0xe4c +//#define rTx_IQK_Tone_B 0xe50 +//#define rRx_IQK_Tone_B 0xe54 +//#define rTx_IQK_PI_B 0xe58 +//#define rRx_IQK_PI_B 0xe5c +//#define rIQK_AGC_Cont 0xe60 + + +// AFE-related +#define rA_AFEPwr1_Jaguar 0xc60 // dynamic AFE power control +#define rA_AFEPwr2_Jaguar 0xc64 // dynamic AFE power control +#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 +#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c +#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 +#define rA_Tx2Tx_RXCCK_Jaguar 0xc74 +#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 +#define rA_Rx2Rx_BT_Jaguar 0xc7c +#define rA_sleep_nav_Jaguar 0xc80 +#define rA_pmpd_Jaguar 0xc84 +#define rB_AFEPwr1_Jaguar 0xe60 // dynamic AFE power control +#define rB_AFEPwr2_Jaguar 0xe64 // dynamic AFE power control +#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 +#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c +#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 +#define rB_Tx2Tx_RXCCK_Jaguar 0xe74 +#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 +#define rB_Rx2Rx_BT_Jaguar 0xe7c +#define rB_sleep_nav_Jaguar 0xe80 +#define rB_pmpd_Jaguar 0xe84 + + +// YN: mask these registers temporaily +//#define rTx_Power_Before_IQK_A 0xe94 +//#define rTx_Power_After_IQK_A 0xe9c + +//#define rRx_Power_Before_IQK_A 0xea0 +//#define rRx_Power_Before_IQK_A_2 0xea4 +//#define rRx_Power_After_IQK_A 0xea8 +//#define rRx_Power_After_IQK_A_2 0xeac + +//#define rTx_Power_Before_IQK_B 0xeb4 +//#define rTx_Power_After_IQK_B 0xebc + +//#define rRx_Power_Before_IQK_B 0xec0 +//#define rRx_Power_Before_IQK_B_2 0xec4 +//#define rRx_Power_After_IQK_B 0xec8 +//#define rRx_Power_After_IQK_B_2 0xecc + + +// RSSI Dump +#define rA_RSSIDump_Jaguar 0xBF0 +#define rB_RSSIDump_Jaguar 0xBF1 +#define rS1_RXevmDump_Jaguar 0xBF4 +#define rS2_RXevmDump_Jaguar 0xBF5 +#define rA_RXsnrDump_Jaguar 0xBF6 +#define rB_RXsnrDump_Jaguar 0xBF7 +#define rA_CfoShortDump_Jaguar 0xBF8 +#define rB_CfoShortDump_Jaguar 0xBFA +#define rA_CfoLongDump_Jaguar 0xBEC +#define rB_CfoLongDump_Jaguar 0xBEE + + +// RF Register +// +#define RF_AC_Jaguar 0x00 // +#define RF_RF_Top_Jaguar 0x07 // +#define RF_TXLOK_Jaguar 0x08 // +#define RF_TXAPK_Jaguar 0x0B +#define RF_CHNLBW_Jaguar 0x18 // RF channel and BW switch +#define RF_RCK1_Jaguar 0x1c // +#define RF_RCK2_Jaguar 0x1d +#define RF_RCK3_Jaguar 0x1e +#define RF_ModeTableAddr 0x30 +#define RF_ModeTableData0 0x31 +#define RF_ModeTableData1 0x32 +#define RF_TxLCTank_Jaguar 0x54 +#define RF_APK_Jaguar 0x63 +#define RF_LCK 0xB4 +#define RF_WeLut_Jaguar 0xEF + +#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 +#define bRF_CHNLBW_BW 0xc00 + + +/*--------------------------Define Parameters-------------------------------*/ + + +#endif //__INC_HALJAGUARPHYREG_H + diff --git a/network/wlan/WDI/HAL/HalMacID.h b/network/wlan/WDI/HAL/HalMacID.h new file mode 100644 index 00000000..db9f04c8 --- /dev/null +++ b/network/wlan/WDI/HAL/HalMacID.h @@ -0,0 +1,199 @@ + +#ifndef __INC_HAL_MAC_ID_H +#define __INC_HAL_MAC_ID_H + +#define NUMBER_OF_HAL_MAC_ID_DESCRIPTOR 128 + +#define MAC_ID_OWNER_ASSOCIATED_CLIENT_AID_NO_USE 0 + + +// Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- +#define MAC_ID_STATIC_FOR_DEFAULT_PORT 0x00 +#define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 0x01 +#define MAC_ID_STATIC_FOR_BT_CLIENT_START 0x02 +#define MAC_ID_STATIC_FOR_BT_CLIENT_END 0x03 +#define MAC_ID_STATIC_FOR_AP_MULTICAST 0x08 +//TODO : temporily we use 0xff as UNSPECIFIED MACID +// but if new IC support more MACID(more than 0xff) +// We should enlarge macid data type from 1 byte->2byte +// Otherwise there will be one MACID never send out. hsiao_ho +#define MAC_ID_STATIC_UNSPECIFIED_MACID 0xff + +// ----------------------------------------------------------- + + +typedef enum _MAC_ID_OWNER_TYPE { + + MAC_ID_OWNER_NOT_IN_USE = 0, + + // No Single Peer + MAC_ID_OWNER_BROADCAST_MULTICAST, + + // Default Port + MAC_ID_OWNER_DEFAULT_PORT, + + // BT High Speed Client + MAC_ID_OWNER_BT, + + // TDLS Peer + MAC_ID_OWNER_TDLS, + + // Native Ad-hoc Client or UI-based fake AP Client + MAC_ID_OWNER_AD_HOC, + + // N62 Virtual Station / N63 P2P Client + MAC_ID_OWNER_INFRA_STA, + + // N62 Virtual Station / N62 P2P Client for broadcast & multicast + MAC_ID_OWNER_INFRA_STA_MULTICAST, + + // N62 Virtual AP / N63 P2P GO + MAC_ID_OWNER_INFRA_AP, + + MAC_ID_OWNER_MAX +} MAC_ID_OWNER_TYPE, *PMAC_ID_OWNER_TYPE; + + +typedef struct _MAC_ID_DESCRIPTOR { + + PADAPTER pOwnerAdapter; // Adapter which owns this descriptor + MAC_ID_OWNER_TYPE OwnerType; // Descriptor owner type + u4Byte OwnerAssociatedClientAID; // Assign for its client if the owner is AP-like + +} MAC_ID_DESCRIPTOR, *PMAC_ID_DESCRIPTOR; + + +typedef struct _HAL_MAC_ID_COMMON_CONTEXT{ + + u1Byte MAC_ID_CONSTRAINT_ON_COUNT_FOR_EACH_OWNER[MAC_ID_OWNER_MAX]; + + // Define the dynamically assigned MacID section + u1Byte MacIdDynamicZoneStart; + + MAC_ID_DESCRIPTOR MacIdDescriptor[NUMBER_OF_HAL_MAC_ID_DESCRIPTOR]; + +} HAL_MAC_ID_COMMON_CONTEXT, *PHAL_MAC_ID_COMMON_CONTEXT; + +#define HAL_MAC_ID_SIZE_OF_COMMON_CONTEXT sizeof(HAL_MAC_ID_COMMON_CONTEXT) + + + +VOID +MacIdInitializeCommonContext( + PADAPTER pAdapter +); + +VOID +MacIdDeInitializeCommonContext( + PADAPTER pAdapter +); + +VOID +MacIdInitializeMediaStatus( + PADAPTER pAdapter +); + +VOID +MacIdIndicateMediaStatus( + PADAPTER pAdapter, + u4Byte MacId, + u4Byte MacIdEnd, + RT_MEDIA_STATUS MediaStatus +); + +VOID +MacIdIndicateSpecificMediaStatus( + PADAPTER pAdapter, + u4Byte MacId, + RT_MEDIA_STATUS MediaStatus +); + +VOID +MacIdIndicateDisconnect( + PADAPTER pAdapter +); + +VOID +MacIdRecoverMediaStatus( + PADAPTER pAdapter +); + +VOID +MacIdDump( + PADAPTER pAdapter +); + +MAC_ID_OWNER_TYPE +MacIdGetOwnerType( + PADAPTER pAdapter, + u4Byte MacId +); + +u4Byte +MacIdGetTxMacId( + PADAPTER Adapter, + PRT_TCB pTcb +); + +u1Byte +MacIdHalGetMaxMacIdSupportNum( + IN PADAPTER Adapter +); + +u1Byte +MacIdHalGetMaxHWMacId( + IN PADAPTER Adapter +); + +VOID +MacIdDeregisterMacIdForInfraClient( + PADAPTER pAdapter, + u4Byte MacId +); + +VOID +MacIdDeregisterSpecificMacId( + PADAPTER pAdapter, + u4Byte MacId +); + +VOID +MacIdDeregisterForOwnerAdapter( + PADAPTER pAdapter +); + +u4Byte +MacIdRegisterMacIdForInfraClient( + PADAPTER pAdapter +); + +u4Byte +MacIdRegisterMacIdForMCastClient( + PADAPTER pAdapter +); + +u4Byte +MacIdRegisterMacIdForAssociatedID( + PADAPTER pAdapter, + MAC_ID_OWNER_TYPE OwnerType, + u4Byte AssociatedID +); + +u4Byte +MacIdGetOwnerAssociatedClientAID( + PADAPTER pAdapter, + u4Byte MacId +); + +u4Byte +MacIdRegisterMacIdForAPMcast( + PADAPTER pAdapter + ); + +MAC_ID_OWNER_TYPE +MacIdGetOwnerType( + PADAPTER pAdapter, + u4Byte MacId +); + +#endif diff --git a/network/wlan/WDI/HAL/HalPG.h b/network/wlan/WDI/HAL/HalPG.h new file mode 100644 index 00000000..3acda33d --- /dev/null +++ b/network/wlan/WDI/HAL/HalPG.h @@ -0,0 +1,809 @@ +#ifndef __INC_HAL_PG_H +#define __INC_HAL_PG_H + +//==================================================== +// EEPROM/Efuse PG Offset for 8192 CE/CU +//==================================================== +#define EEPROM_VID_92C 0x0A +#define EEPROM_PID_92C 0x0C +#define EEPROM_DID_92C 0x0C +#define EEPROM_SVID_92C 0x0E +#define EEPROM_SMID_92C 0x10 +#define EEPROM_MAC_ADDR_92C 0x16 + +#define EEPROM_SUBCUSTOMER_ID 0x59 + +#define EEPROM_MAC_ADDR 0x16 +#define EEPROM_TV_OPTION 0x50 +#define EEPROM_SUBCUSTOMER_ID 0x59 +#define EEPROM_CCK_TX_PWR_INX 0x5A +#define EEPROM_HT40_1S_TX_PWR_INX 0x60 +#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 +#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 +#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C +#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F +#define EEPROM_VERSION_92C 0x7E +#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 +#define EEPROM_CHANNEL_PLAN_92C 0x75 +#define EEPROM_TSSI_A 0x76 +#define EEPROM_TSSI_B 0x77 +#define EEPROM_THERMAL_METER_92C 0x78 +#define EEPROM_RF_OPT1_92C 0x79 +#define EEPROM_RF_OPT2_92C 0x7A +#define EEPROM_RF_OPT3_92C 0x7B +#define EEPROM_RF_OPT4_92C 0x7C +#define EEPROM_CUSTOMER_ID 0x7F +#define EEPROM_CUSTOMER_ID_92C 0x7F + +#define EEPROM_NORMAL_CHANNEL_PLAN 0x75 +#define EEPROM_NORMAL_BoardType_92C EEPROM_RF_OPT1_92C +#define BOARD_TYPE_NORMAL_MASK 0xE0 +#define BOARD_TYPE_TEST_MASK 0xF +#define EEPROM_TYPE_ID 0x7E + +// PCIe related +#define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74 +#define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75 + + +//==================================================== +// EEPROM/Efuse PG Offset for 8723AE/8723AU/8723AS +//==================================================== +#define EEPROM_CCK_TX_PWR_INX_8723A 0x10 +#define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16 +#define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C +#define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F +#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22 +#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25 + +#define EEPROM_ChannelPlan_8723A 0x28 +#define EEPROM_TSSI_A_8723A 0x29 +#define EEPROM_THERMAL_METER_8723A 0x2A +#define RF_OPTION1_8723A 0x2B +#define RF_OPTION2_8723A 0x2C +#define RF_OPTION3_8723A 0x2D +#define RF_OPTION4_8723A 0x2E +#define EEPROM_VERSION_8723A 0x30 +#define EEPROM_CustomID_8723A 0x31 +#define EEPROM_SubCustomID_8723A 0x32 +#define EEPROM_XTAL_K_8723A 0x33 +#define EEPROM_Chipset_8723A 0x34 + + +// RTL8723AE +#define EEPROM_VID_8723AE 0x49 +#define EEPROM_DID_8723AE 0x4B +#define EEPROM_SVID_8723AE 0x4D +#define EEPROM_SMID_8723AE 0x4F +#define EEPROM_MAC_ADDR_8723AE 0x67 + +//RTL8723AU +#define EEPROM_MAC_ADDR_8723AU 0xC6 +#define EEPROM_VID_8723AU 0xB7 +#define EEPROM_PID_8723AU 0xB9 + +// RTL8723AS +#define EEPROM_MAC_ADDR_8723AS 0xAA + +//==================================================== +// EEPROM/Efuse PG Offset for 8192 DE/DU +//==================================================== +// pcie +#define RTL8190_EEPROM_ID 0x8129 // 0-1 +#define EEPROM_HPON 0x02 // LDO settings.2-5 +#define EEPROM_CLK 0x06 // Clock settings.6-7 +#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8 + +#define EEPROM_MAC_ADDR_MAC0_92DE 0x55 +#define EEPROM_MAC_ADDR_MAC1_92DE 0x5B + +//usb +#define EEPROM_ENDPOINT_SETTING 0x10 +#define EEPROM_CHIRP_K 0x12 // Changed +#define EEPROM_USB_PHY 0x13 // Changed +#define EEPROM_STRING 0x1F +#define EEPROM_SUBCUSTOMER_ID 0x59 + +#define EEPROM_MAC_ADDR_MAC0_92DU 0x19 +#define EEPROM_MAC_ADDR_MAC1_92DU 0x5B +//---------------------------------------------------------------- +// 2.4G band Tx power index setting +#define EEPROM_CCK_TX_PWR_INX_2G_92D 0x61 +#define EEPROM_HT40_1S_TX_PWR_INX_2G_92D 0x67 +#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G_92D 0x6D +#define EEPROM_HT20_TX_PWR_INX_DIFF_2G_92D 0x70 +#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G_92D 0x73 +#define EEPROM_HT40_MAX_PWR_OFFSET_2G_92D 0x76 +#define EEPROM_HT20_MAX_PWR_OFFSET_2G_92D 0x79 + +//5GL channel 32-64 +#define EEPROM_HT40_1S_TX_PWR_INX_5GL_92D 0x7C +#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL_92D 0x82 +#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL_92D 0x85 +#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL_92D 0x88 +#define EEPROM_HT40_MAX_PWR_OFFSET_5GL_92D 0x8B +#define EEPROM_HT20_MAX_PWR_OFFSET_5GL_92D 0x8E + +//5GM channel 100-140 +#define EEPROM_HT40_1S_TX_PWR_INX_5GM_92D 0x91 +#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM_92D 0x97 +#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM_92D 0x9A +#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM_92D 0x9D +#define EEPROM_HT40_MAX_PWR_OFFSET_5GM_92D 0xA0 +#define EEPROM_HT20_MAX_PWR_OFFSET_5GM_92D 0xA3 + +//5GH channel 149-165 +#define EEPROM_HT40_1S_TX_PWR_INX_5GH_92D 0xA6 +#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH_92D 0xAC +#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH_92D 0xAF +#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH_92D 0xB2 +#define EEPROM_HT40_MAX_PWR_OFFSET_5GH_92D 0xB5 +#define EEPROM_HT20_MAX_PWR_OFFSET_5GH_92D 0xB8 + + +#define EEPROM_CHANNEL_PLAN_92D 0xBB // Map of supported channels. +#define EEPROM_TEST_CHANNEL_PLAN_92D 0xBB +#define EEPROM_THERMAL_METER_92D 0xC3 //[4:0] +#define EEPROM_IQK_DELTA_92D 0xBC +#define EEPROM_LCK_DELTA_92D 0xBC +#define EEPROM_XTAL_K_92D 0xBD //[7:5] +#define EEPROM_TSSI_A_5G_92D 0xBE +#define EEPROM_TSSI_B_5G_92D 0xBF +#define EEPROM_TSSI_AB_5G_92D 0xC0 + +#define EEPROM_RF_OPT6 0xC9 +#define EEPROM_RF_OPT7 0xCC + + +#define EEPROM_DEF_PART_NO 0x3FD //Byte +#define EEPROME_CHIP_VERSION_L 0x3FF +#define EEPROME_CHIP_VERSION_H 0x3FE + +//---------------------------------------------------------------- + +#define EEPROM_VID_92DE 0x28 +#define EEPROM_PID_92DE 0x2A +#define EEPROM_SVID_92DE 0x2C +#define EEPROM_SMID_92DE 0x2E +#define EEPROM_PATHDIV_92D 0xC4 + +#define EEPROM_BOARD_OPTIONS_92D 0xC4 +#define EEPROM_5G_LNA_GAIN_92D 0xC6 +#define EEPROM_FEATURE_OPTIONS_92D 0xC7 +#define EEPROM_BT_SETTING_92D 0xC8 + +#define EEPROM_VERSION_92D 0xCA +#define EEPROM_CUSTOMER_ID_92D 0xCB + + +#define EEPROM_THERMAL_METER_92D 0xC3 + +#define EEPROM_VID_92DU 0xC +#define EEPROM_PID_92DU 0xE + +//==================================================== +// EEPROM/Efuse PG Offset for 88EE/88EU/88ES +//==================================================== +#define EEPROM_TX_PWR_INX_88E 0x10 + +#define EEPROM_ChannelPlan_88E 0xB8 +#define EEPROM_XTAL_88E 0xB9 +#define EEPROM_THERMAL_METER_88E 0xBA +#define EEPROM_IQK_LCK_88E 0xBB + +#define EEPROM_RF_BOARD_OPTION_88E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 +#define EEPROM_RF_BT_SETTING_88E 0xC3 +#define EEPROM_VERSION_88E 0xC4 +#define EEPROM_CustomID_88E 0xC5 +#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 +#define EEPROM_RF_BB_GAIN 0xFD + +// RTL88EE +#define EEPROM_MAC_ADDR_88EE 0xD0 +#define EEPROM_VID_88EE 0xD6 +#define EEPROM_DID_88EE 0xD8 +#define EEPROM_SVID_88EE 0xDA +#define EEPROM_SMID_88EE 0xDC + +//RTL88EU +#define EEPROM_MAC_ADDR_88EU 0xD7 +#define EEPROM_VID_88EU 0xD0 +#define EEPROM_PID_88EU 0xD2 + +// RTL88ES +#define EEPROM_MAC_ADDR_88ES 0x11A + +//==================================================== +// EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS +//==================================================== +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_USB_MODE_8812 0x08 + +#define EEPROM_RF_FEATURE_OPTION_8812 0xC2 +#define EEPROM_RF_BT_SETTING_8812 0xC3 +#define EEPROM_VERSION_8812 0xC4 +#define EEPROM_CustomID_8812 0xC5 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8812 0xC9 + +// RTL8812AE +#define EEPROM_MAC_ADDR_8812AE 0xD0 +#define EEPROM_VID_8812AE 0xD6 +#define EEPROM_DID_8812AE 0xD8 +#define EEPROM_SVID_8812AE 0xDA +#define EEPROM_SMID_8812AE 0xDC + + +// RTL8821BE +#define EEPROM_MAC_ADDR_8821BE 0xD0 +#define EEPROM_VID_8821BE 0xD6 +#define EEPROM_DID_8821BE 0xD8 +#define EEPROM_SVID_8821BE 0xDA +#define EEPROM_SMID_8821BE 0xDC + +// RTL8822BE +#define EEPROM_MAC_ADDR_8822BE 0xD0 +#define EEPROM_VID_8822BE 0xD6 +#define EEPROM_DID_8822BE 0xD8 +#define EEPROM_SVID_8822BE 0xDA +#define EEPROM_SMID_8822BE 0xDC + + +//RTL8812AU +#define EEPROM_MAC_ADDR_8812AU 0xD7 +#define EEPROM_VID_8812AU 0xD0 +#define EEPROM_PID_8812AU 0xD2 + + +//=========================================================== +// EEPROM/Efuse PG Offset for 8821BE/8821BU/8821BS +//=========================================================== + +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_USB_MODE_8821B 0x08 +#define EEPROM_TX_PWR_INX_8821B 0x10 + +#define EEPROM_ChannelPlan_8821B 0xB8 +#define EEPROM_XTAL_8821B 0xB9 +#define EEPROM_THERMAL_METER_8821B 0xBA +#define EEPROM_IQK_LCK_8821B 0xBB + +#define EEPROM_RF_FEATURE_OPTION_8821B 0xC2 +#define EEPROM_RF_BT_SETTING_8821B 0xC3 +#define EEPROM_VERSION_8821B 0xC4 +#define EEPROM_CustomID_8821B 0xC5 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8821B 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8821B 0xC9 +#define EEPROM_RFE_OPTION_8821B 0xCA + +//RTL8821B +#define EEPROM_MAC_ADDR_8821B 0xD0 +#define EEPROM_VID_8821B 0xD6 +#define EEPROM_DID_8821B 0xD8 +#define EEPROM_SVID_8821B 0xDA +#define EEPROM_SMID_8821B 0xDC + +//RTL8821BU +#define EEPROM_MAC_ADDR_8821BU 0xD7 +#define EEPROM_VID_8821BU 0xD0 +#define EEPROM_PID_8821BU 0xD2 + +//=========================================================== +// EEPROM/Efuse PG Offset for 8822BE/8822BU/8822BS +//=========================================================== + +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_USB_MODE_8822B 0x08 +#define EEPROM_TX_PWR_INX_8822B 0x10 + +#define EEPROM_ChannelPlan_8822B 0xB8 +#define EEPROM_XTAL_8822B 0xB9 +#define EEPROM_THERMAL_METER_8822B 0xBA +#define EEPROM_IQK_LCK_8822B 0xBB + +#define EEPROM_RF_FEATURE_OPTION_8822B 0xC2 +#define EEPROM_RF_BT_SETTING_8822B 0xC3 +#define EEPROM_VERSION_8822B 0xC4 +#define EEPROM_CustomID_8822B 0xC5 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8822B 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8822B 0xC9 +#define EEPROM_RFE_OPTION_8822B 0xCA + +//RTL8822B +#define EEPROM_MAC_ADDR_8822BU 0x107 +#define EEPROM_VID_8822B 0x100 +#define EEPROM_DID_8822B 0x102 +#define EEPROM_SVID_8822B 0xDA +#define EEPROM_SMID_8822B 0xDC + +//RTL8821BU +#define EEPROM_MAC_ADDR_8821BU 0xD7 +#define EEPROM_VID_8821BU 0xD0 +#define EEPROM_PID_8821BU 0xD2 + + +//==================================================== +// EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS +//==================================================== +#define EEPROM_RF_FEATURE_OPTION_8821 0xC2 +#define EEPROM_RF_BT_SETTING_8821 0xC3 +#define EEPROM_VERSION_8821 0xC4 +#define EEPROM_CustomID_8821 0xC5 +#define EEPROM_RF_ANTENNA_OPT_8821 0xC9 + +// RTL8821AE +#define EEPROM_MAC_ADDR_8821AE 0xD0 +#define EEPROM_VID_8821AE 0xD6 +#define EEPROM_DID_8821AE 0xD8 +#define EEPROM_SVID_8821AE 0xDA +#define EEPROM_SMID_8821AE 0xDC + +// RTL8821AS +#define EEPROM_MAC_ADDR_8821AS 0x11A + +//RTL8821AU +#define EEPROM_MAC_ADDR_8821AU 0x107 +#define EEPROM_VID_8821AU 0x100 +#define EEPROM_PID_8821AU 0x102 + +// 8188EU / 8192EU EFUSE cloud key define +#define EEPROM_CLOUD_KEY_START_EX 0x122 +#define EEPROM_CLOUD_KEY_END 0x12F +#define EEPROM_CLOUD_KEY_LENGTH_EX 14 // 12F-122 = 14 +#define EEPROM_LENGTH 512 + +//==================================================== +// EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS +//==================================================== + +#define EEPROM_ChannelPlan_8723B 0xB8 +#define EEPROM_XTAL_8723B 0xB9 +#define EEPROM_THERMAL_METER_8723B 0xBA + +#define EEPROM_RF_BOARD_OPTION_8723B 0xC1 +#define EEPROM_RF_BT_SETTING_8723B 0xC3 + +// RTL8723BE +#define EEPROM_MAC_ADDR_8723BE 0xD0 +#define EEPROM_VID_8723BE 0xD6 +#define EEPROM_DID_8723BE 0xD8 +#define EEPROM_SVID_8723BE 0xDA +#define EEPROM_SMID_8723BE 0xDC +#define EEPROM_CustomID_8723B 0xC5 +#define EEPROM_RFE_Type_8723BE 0xCA + +//RTL8723BU +#define EEPROM_MAC_ADDR_8723BU 0x107 +#define EEPROM_VID_8723BU 0xD0 +#define EEPROM_PID_8723BU 0xD2 +#define EEPROM_PA_TYPE_8723BU 0xBC +#define EEPROM_LNA_TYPE_2G_8723BU 0xBD +#define EEPROM_LNA_TYPE_5G_8723BU 0xBF + +//RTL8723BS +#define EEPROM_MAC_ADDR_8723BS 0x11A + +//==================================================== +// EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES +//==================================================== +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_TX_PWR_INX_8192E 0x10 + +#define EEPROM_ChannelPlan_8192E 0xB8 +#define EEPROM_XTAL_8192E 0xB9 +#define EEPROM_THERMAL_METER_8192E 0xBA +#define EEPROM_IQK_LCK_8192E 0xBB +#define EEPROM_2G_5G_PA_TYPE_8192E 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF + +#define EEPROM_RF_BOARD_OPTION_8192E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8192E 0xC2 +#define EEPROM_RF_BT_SETTING_8192E 0xC3 +#define EEPROM_VERSION_8192E 0xC4 +#define EEPROM_CustomID_8192E 0xC5 +#define EEPROM_TX_BBSWING_2G_8192E 0xC6 +#define EEPROM_TX_BBSWING_5G_8192E 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8192E 0xC9 +#define EEPROM_RFE_OPTION_8192E 0xCA + +// RTL8192EE +#define EEPROM_MAC_ADDR_8192EE 0xD0 +#define EEPROM_VID_8192EE 0xD6 +#define EEPROM_DID_8192EE 0xD8 +#define EEPROM_SVID_8192EE 0xDA +#define EEPROM_SMID_8192EE 0xDC + +//RTL8192EU +#define EEPROM_MAC_ADDR_8192EU 0xD7 +#define EEPROM_VID_8192EU 0xD0 +#define EEPROM_PID_8192EU 0xD2 +#define EEPROM_PA_TYPE_8192EU 0xBC +#define EEPROM_LNA_TYPE_2G_8192EU 0xBD +#define EEPROM_LNA_TYPE_5G_8192EU 0xBF + +// RTL8192ES +#define EEPROM_MAC_ADDR_8192ES 0x11B + +//==================================================== +// EEPROM/Efuse PG Offset for 8814AE/8814AU/8814AS +//==================================================== +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_USB_MODE_8814A 0x0E + +#define EEPROM_RF_FEATURE_OPTION_8814A 0xC2 +#define EEPROM_RF_BT_SETTING_8814A 0xC3 +#define EEPROM_VERSION_8814A 0xC4 +#define EEPROM_CustomID_8814A 0xC5 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8814A 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8814A 0xC9 + +// RTL8814AE +#define EEPROM_MAC_ADDR_8814AE 0xD0 +#define EEPROM_VID_8814AE 0xD6 +#define EEPROM_DID_8814AE 0xD8 +#define EEPROM_SVID_8814AE 0xDA +#define EEPROM_SMID_8814AE 0xDC + +//RTL8814AU +#define EEPROM_MAC_ADDR_8814AU 0xD8 +#define EEPROM_VID_8814AU 0xD0 +#define EEPROM_PID_8814AU 0xD2 +#define EEPROM_PA_TYPE_8814AU 0xBC +#define EEPROM_LNA_TYPE_2G_8814AU 0xBD +#define EEPROM_LNA_TYPE_5G_8814AU 0xBF + +// RTL8814AS +#define EEPROM_MAC_ADDR_8814AS 0x11B + + +//=========================================================== +// EEPROM/Efuse PG Offset for 8812/8821/8814/8821B +//=========================================================== +//JAGUAR +#define EEPROM_TX_PWR_INX_JAGUAR 0x10 +#define EEPROM_ChannelPlan_JAGUAR 0xB8 +#define EEPROM_XTAL_JAGAUR 0xB9 +#define EEPROM_THERMAL_METER_JAGUAR 0xBA +#define EEPROM_IQK_LCK_JAGUAR 0xBB + +#define EEPROM_PA_TYPE_JAGUAR 0xBC +#define EEPROM_LNA_TYPE_AB_2G_JAGUAR 0xBD +#define EEPROM_LNA_TYPE_CD_2G_JAGUAR 0xBE +#define EEPROM_LNA_TYPE_AB_5G_JAGUAR 0xBF +#define EEPROM_LNA_TYPE_CD_5G_JAGUAR 0xC0 +#define EEPROM_RF_BOARD_OPTION_JAGUAR 0xC1 +#define EEPROM_TX_BBSWING_2G_JAGUAR 0xC6 +#define EEPROM_TX_BBSWING_5G_JAGUAR 0xC7 +#define EEPROM_RFE_OPTION_JAGUAR 0xCA + +//========================================================== +// EEPROM/Efuse PG Offset for 8703BE/8703BU/8703BS +//========================================================== + +#define EEPROM_ChannelPlan_8703B 0xB8 +#define EEPROM_XTAL_8703B 0xB9 +#define EEPROM_THERMAL_METER_8703B 0xBA + +#define EEPROM_RF_BOARD_OPTION_8703B 0xC1 +#define EEPROM_RF_BT_SETTING_8703B 0xC3 + +//RTL 8703BE +#define EEPROM_MAC_ADDR_8703BE 0xD0 +#define EEPROM_VID_8703BE 0xD6 +#define EEPROM_DID_8703BE 0xD8 +#define EEPROM_SVID_8703BE 0xDA +#define EEPROM_SMID_8703BE 0xDC +#define EEPROM_CustomID_8703B 0xC5 +#define EEPROM_RFE_Type_8703BE 0xCA + +//RTL8723BS +#define EEPROM_MAC_ADDR_8703BS 0x11A + +//RTL8723BU +#define EEPROM_MAC_ADDR_8703BU 0x107 +#define EEPROM_VID_8703BU 0xD0 +#define EEPROM_PID_8703BU 0xD2 +#define EEPROM_PA_TYPE_8703BU 0xBC +#define EEPROM_LNA_TYPE_2G_8703BU 0xBD +#define EEPROM_LNA_TYPE_5G_8703BU 0xBF + +//========================================================== +// EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS +//========================================================== + +#define EEPROM_ChannelPlan_8188F 0xB8 +#define EEPROM_XTAL_8188F 0xB9 +#define EEPROM_THERMAL_METER_8188F 0xBA + +#define EEPROM_RF_BOARD_OPTION_8188F 0xC1 +#define EEPROM_RF_BT_SETTING_8188F 0xC3 + +//RTL 8188FE +#define EEPROM_MAC_ADDR_8188FE 0xD0 +#define EEPROM_VID_8188FE 0xD6 +#define EEPROM_DID_8188FE 0xD8 +#define EEPROM_SVID_8188FE 0xDA +#define EEPROM_SMID_8188FE 0xDC +#define EEPROM_CustomID_8188F 0xC5 +#define EEPROM_RFE_Type_8188FE 0xCA + +//RTL8188FS +#define EEPROM_MAC_ADDR_8188FS 0x11A + +//RTL8188FU +#define EEPROM_MAC_ADDR_8188FU 0xD7 +#define EEPROM_VID_8188FU 0xD0 +#define EEPROM_PID_8188FU 0xD2 +#define EEPROM_PA_TYPE_8188FU 0xBC +#define EEPROM_LNA_TYPE_2G_8188FU 0xBD +#define EEPROM_LNA_TYPE_5G_8188FU 0xBF +#define EEPROM_RF_ANTENNA_OPT_8188FU 0xC9 + +//==================================================== +// EEPROM/Efuse PG Offset for 8723DE/8723DU/8723DS +//==================================================== +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_TX_PWR_INX_8723D 0x10 +#define EEPROM_Default_ThermalMeter_8723D 0x1A + +#define EEPROM_ChannelPlan_8723D 0xB8 +#define EEPROM_XTAL_8723D 0xB9 +#define EEPROM_THERMAL_METER_8723D 0xBA +#define EEPROM_IQK_LCK_8723D 0xBB +#define EEPROM_2G_5G_PA_TYPE_8723D 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723D 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723D 0xBF + +#define EEPROM_RF_BOARD_OPTION_8723D 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8723D 0xC2 +#define EEPROM_RF_BT_SETTING_8723D 0xC3 +#define EEPROM_VERSION_8723D 0xC4 +#define EEPROM_CustomID_8723D 0xC5 +#define EEPROM_TX_BBSWING_2G_8723D 0xC6 +#define EEPROM_TX_BBSWING_5G_8723D 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8723D 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8723D 0xC9 +#define EEPROM_RFE_OPTION_8723D 0xCA + +// RTL8723DE +#define EEPROM_MAC_ADDR_8723DE 0xD0 +#define EEPROM_VID_8723DE 0xD6 +#define EEPROM_DID_8723DE 0xD8 +#define EEPROM_SVID_8723DE 0xDA +#define EEPROM_SMID_8723DE 0xDC + +//RTL8723DU +#define EEPROM_MAC_ADDR_8723DU 0xD7 +#define EEPROM_VID_8723DU 0xD0 +#define EEPROM_PID_8723DU 0xD2 +#define EEPROM_PA_TYPE_8723DU 0xBC +#define EEPROM_LNA_TYPE_2G_8723DU 0xBD +#define EEPROM_LNA_TYPE_5G_8723DU 0xBF + +// RTL8723DS +#define EEPROM_MAC_ADDR_8723DS 0x11A + + +//==================================================== +// EEPROM/Efuse Value Type +//==================================================== +#define EETYPE_TX_PWR 0x0 +//==================================================== +// EEPROM/Efuse Default Value +//==================================================== +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_DEFAULT_EXT 0xFF // Reserved for Realtek +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_CCX 0x10 +#define EEPROM_CID_QMI 0x0D +#define EEPROM_CID_WHQL 0xFE + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB +#define EEPROM_CHANNEL_PLAN_CHIAN 0XC +#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD +#define EEPROM_CHANNEL_PLAN_KOREA 0xE +#define EEPROM_CHANNEL_PLAN_TURKEY 0xF +#define EEPROM_CHANNEL_PLAN_JAPAN 0x10 +#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11 +#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13 +#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14 + +#define EEPROM_USB_OPTIONAL1 0xE +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +#define RTL_EEPROM_ID 0x8129 +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_ThermalMeter 0x12 +#define EEPROM_Default_ThermalMeter_88E 0x18 +#define EEPROM_Default_ThermalMeter_Jaguar 0x18 +#define EEPROM_Default_ThermalMeter_8192E 0x1A + + + + +#define EEPROM_Default_CrystalCap 0x0 +#define EEPROM_Default_CrystalCap_8723A 0x20 +#define EEPROM_Default_CrystalFreq 0x0 +#define EEPROM_Default_TxPowerLevel_92C 0x22 +#define EEPROM_Default_TxPowerLevel_2G 0x2C +#define EEPROM_Default_TxPowerLevel_5G 0x22 +#define EEPROM_Default_TxPowerLevel 0x22 +#define EEPROM_Default_HT40_2SDiff 0x0 +#define EEPROM_Default_HT20_Diff 2 +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4 +#define EEPROM_Default_HT40_PwrMaxOffset 0 +#define EEPROM_Default_HT20_PwrMaxOffset 0 + +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_CustomerID_8188E 0x00 +#define EEPROM_Default_SubCustomerID 0xCD +#define EEPROM_Default_Version 0 + +#define EEPROM_Default_externalPA_C9 0x00 +#define EEPROM_Default_externalPA_CC 0xFF +#define EEPROM_Default_internalPA_SP3T_C9 0xAA +#define EEPROM_Default_internalPA_SP3T_CC 0xAF +#define EEPROM_Default_internalPA_SPDT_C9 0xAA + +#define EEPROM_Default_internalPA_SPDT_CC 0xFA + +#define EEPROM_Default_PAType 0 +#define EEPROM_Default_LNAType 0 + +//New EFUSE deafult value +#define EEPROM_DEFAULT_24G_INDEX 0x2D +#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 +#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_5G_INDEX 0X2A +#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 +#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_DIFF 0XFE +#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F +#define EEPROM_DEFAULT_BOARD_OPTION 0x00 +#define EEPROM_DEFAULT_RFE_OPTION 0x04 +#define EEPROM_DEFAULT_RFE_OPTION_8192E 0x03 +#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 +#define EEPROM_DEFAULT_BT_OPTION 0x10 + +#define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00 + +// +// For VHT series TX power by rate table. +// VHT TX power by rate off setArray = +// Band:-2G&5G = 0 / 1 +// RF: at most 4*4 = ABCD=0/1/2/3 +// CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 +// +#define TX_PWR_BY_RATE_NUM_BAND 2 +#define TX_PWR_BY_RATE_NUM_RF 4 +#define TX_PWR_BY_RATE_NUM_RATE 84 + +#define TXPWR_LMT_MAX_RF 4 + +//---------------------------------------------------------------------------- +// EEPROM/EFUSE data structure definition. +//---------------------------------------------------------------------------- +#define MAX_RF_PATH_NUM 2 +#define MAX_CHNL_GROUP 3+9 +typedef struct _TxPowerInfo{ + u1Byte CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; + u1Byte HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; + u1Byte HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; + s1Byte HT20IndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; + u1Byte OFDMIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; + u1Byte HT40MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; + u1Byte HT20MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; + u1Byte TSSI_A[3]; + u1Byte TSSI_B[3]; + u1Byte TSSI_A_5G[3]; //5GL/5GM/5GH + u1Byte TSSI_B_5G[3]; +}TxPowerInfo, *PTxPowerInfo; + + +//For 88E new structure + +/* +2.4G: +{ +{1,2}, +{3,4,5}, +{6,7,8}, +{9,10,11}, +{12,13}, +{14} +} + +5G: +{ +{36,38,40}, +{44,46,48}, +{52,54,56}, +{60,62,64}, +{100,102,104}, +{108,110,112}, +{116,118,120}, +{124,126,128}, +{132,134,136}, +{140,142,144}, +{149,151,153}, +{157,159,161}, +{173,175,177}, +} +*/ +#define MAX_RF_PATH 4 +#define MAX_CHNL_GROUP_24G 6 +#define MAX_CHNL_GROUP_5G 14 + +//It must always set to 4, otherwise read efuse table secquence will be wrong. +#define MAX_TX_COUNT 4 + +typedef struct _TxPowerInfo24G{ + u1Byte IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + u1Byte IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1]; + //If only one tx, only BW20 and OFDM are used. + s1Byte CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +}TxPowerInfo24G, *PTxPowerInfo24G; + +typedef struct _TxPowerInfo5G{ + u1Byte IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; + //If only one tx, only BW20, OFDM, BW80 and BW160 are used. + s1Byte OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +}TxPowerInfo5G, *PTxPowerInfo5G; + + +typedef enum _BT_TOTAL_ANT_NUM{ + ANT_TOTAL_X2 = 0, + ANT_TOTAL_X1 = 1 +} BT_TOTAL_ANT_NUM, *PBT_TOTAL_ANT_NUM; + +typedef enum _BT_BOARD_TYPE{ + BT_2WIRE = 0, + BT_ISSC_3WIRE = 1, + BT_ACCEL = 2, + BT_CSR_BC4 = 3, + BT_CSR_BC8 = 4, + BT_RTL8756 = 5, + BT_RTL8723A = 6, + BT_RTL8821 = 7, + BT_RTL8723B = 8, + BT_RTL8192E = 9, + BT_RTL8814A = 10, + BT_RTL8812A = 11, + BT_RTL8821B = 12, + BT_RTL8822B = 13, + BT_RTL8703B = 14, + BT_RTL8188F = 15, + BT_RTL8723D = 16 +} BT_BOARD_TYPE, *PBT_BOARD_TYPE; + + +#endif diff --git a/network/wlan/WDI/HAL/HalPhy.h b/network/wlan/WDI/HAL/HalPhy.h new file mode 100644 index 00000000..387fe95a --- /dev/null +++ b/network/wlan/WDI/HAL/HalPhy.h @@ -0,0 +1,349 @@ +#ifndef __INC_HALPHY_H +#define __INC_HALPHY_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalPhy.h + +Abstract: + Prototype of PHY_XXX() and related data structure. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-10 Lanhsin Create. +--*/ + +/*--------------------------Define Parameters-------------------------------*/ + +#if (DISABLE_BB_RF == 1) +#define HAL_FW_ENABLE 0 +#define HAL_MAC_ENABLE 0 +#define HAL_BB_ENABLE 0 +#define HAL_RF_ENABLE 0 +#else // FPGA_PHY and ASIC +#define HAL_FW_ENABLE 1 +#define HAL_MAC_ENABLE 1 +#define HAL_BB_ENABLE 1 +#define HAL_RF_ENABLE 1 +#endif + + +#define delay_ms(_t) PlatformStallExecution(1000*(_t)) +#define delay_us(_t) PlatformStallExecution(_t) + +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG_88E 0xFF +#define RF6052_MAX_REG_92C 0x7F + +#define RF6052_MAX_REG \ + (RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E: RF6052_MAX_REG_92C + +#define GET_RF6052_REAL_MAX_REG(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C + + +#define RF6052_MAX_PATH 4 + +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + + +#define PHY_SUPPORT_92C 1 +#define PHY_SUPPORT_92D 1 +#define PHY_SUPPORT_88E 1 +#define PHY_SUPPORT_8812 1 +#define PHY_SUPPORT_92E 1 +#define PHY_SUPPORT_8723B 1 +#define PHY_SUPPORT_8814A 1 +#define PHY_SUPPORT_8822B 1 + + +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + +// +// Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected. +// Added by Roger, 2013.05.22. +// +#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & BIT0) +#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & BIT1) +#define IS_ANT_DETECT_SUPPORT_PSD(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & BIT2) + +/*--------------------------Define Parameters-------------------------------*/ +typedef enum _RF_TYPE{ + RF_TYPE_MIN = 0, // 0 + RF_8225=1, // 1 11b/g RF for verification only + RF_8256=2, // 2 11b/g/n + RF_8258=3, // 3 11a/b/g/n RF + RF_6052=4, // 4 11b/g/n RF + RF_PSEUDO_11N=5, // 5, It is a temporality RF. + RF_TYPE_MAX +}RF_TYPE_E,*PRF_TYPE_E; + + +#define RF_PATH_MAX_92C_88E 2 +#define RF_PATH_MAX_90_8812 4 //Max RF number 90 support +#define RF_PATH_MAX_90_8814A 4 + + +typedef enum _ANTENNA_PATH{ + ANTENNA_NONE = 0, + ANTENNA_D = 1, + ANTENNA_C = 2, + ANTENNA_CD = 3, + ANTENNA_B = 4, + ANTENNA_BD = 5, + ANTENNA_BC = 6, + ANTENNA_BCD = 7, + ANTENNA_A = 8, + ANTENNA_AD = 9, + ANTENNA_AC = 10, + ANTENNA_ACD = 11, + ANTENNA_AB = 12, + ANTENNA_ABD = 13, + ANTENNA_ABC = 14, + ANTENNA_ABCD = 15 +} ANTENNA_PATH; + + typedef enum _RF_CONTENT{ + radioa_txt = 0x1000, + radiob_txt = 0x1001, + radioc_txt = 0x1002, + radiod_txt = 0x1003 +} RF_CONTENT; + +typedef enum _BaseBand_Config_Type{ + BaseBand_Config_PHY_REG = 0, //Radio Path A + BaseBand_Config_AGC_TAB = 1, //Radio Path B + BaseBand_Config_AGC_TAB_2G = 2, + BaseBand_Config_AGC_TAB_5G = 3, + BaseBand_Config_PHY_REG_PG +}BaseBand_Config_Type, *PBaseBand_Config_Type; + + + +typedef enum _HW_BLOCK{ + HW_BLOCK_MAC = 0, + HW_BLOCK_PHY0 = 1, + HW_BLOCK_PHY1 = 2, + HW_BLOCK_RF = 3, + HW_BLOCK_MAXIMUM = 4, // Never use this +}HW_BLOCK_E, *PHW_BLOCK_E; + +typedef enum _SwChnlCmdID{ + CmdID_End, + CmdID_SetTxPowerLevel, + CmdID_WritePortUlong, + CmdID_WritePortUshort, + CmdID_WritePortUchar, + CmdID_RF_WriteReg, +}SwChnlCmdID; + + + +typedef enum _RATR_TABLE_MODE{ + RATR_INX_WIRELESS_NGB = 0, // BGN 40 Mhz 2SS 1SS + RATR_INX_WIRELESS_NG = 1, // GN or N + RATR_INX_WIRELESS_NB = 2, // BGN 20 Mhz 2SS 1SS or BN + RATR_INX_WIRELESS_N = 3, + RATR_INX_WIRELESS_GB = 4, + RATR_INX_WIRELESS_G = 5, + RATR_INX_WIRELESS_B = 6, + RATR_INX_WIRELESS_MC = 7, + RATR_INX_WIRELESS_AC_5N = 8, + RATR_INX_WIRELESS_AC_24N = 9, +}RATR_TABLE_MODE, *PRATR_TABLE_MODE; + + +/*------------------------------Define structure----------------------------*/ +typedef struct _SwChnlCmd{ + SwChnlCmdID CmdID; + u4Byte Para1; + u4Byte Para2; + u4Byte msDelay; +}SwChnlCmd; + + +#ifdef REMOVE_PACK +#pragma pack(1) +#endif + +typedef struct _R_ANTENNA_SELECT_OFDM{ + u4Byte r_tx_antenna:4; + u4Byte r_ant_l:4; + u4Byte r_ant_non_ht:4; + u4Byte r_ant_ht1:4; + u4Byte r_ant_ht2:4; + u4Byte r_ant_ht_s1:4; + u4Byte r_ant_non_ht_s1:4; + u4Byte OFDM_TXSC:2; + u4Byte Reserved:2; +}R_ANTENNA_SELECT_OFDM; + +typedef struct _R_ANTENNA_SELECT_CCK{ + u1Byte r_cckrx_enable_2:2; + u1Byte r_cckrx_enable:2; + u1Byte r_ccktx_enable:4; +}R_ANTENNA_SELECT_CCK; + + +#ifdef REMOVE_PACK +#pragma pack() +#endif + + +typedef struct RF_Shadow_Compare_Map { + // Shadow register value + UINT32 Value; + // Compare or not flag + UINT8 Compare; + // Record If it had ever modified unpredicted + UINT8 ErrorOrNot; + // Recorver Flag + UINT8 Recorver; + // + UINT8 Driver_Write; +}RF_SHADOW_T; + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ + + +u4Byte +PHY_CalculateBitShift( + u4Byte BitMask + ); + +VOID +PHY_SetMacReg( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +PHY_QueryMacReg( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +u4Byte +PHY_QueryBBReg( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +PHY_SetBBReg( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +VOID +PHY_SetBBReg1Byte( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + + +u4Byte +PHY_QueryRFReg( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +PHY_SetRFReg( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +// +// RF Shadow operation relative API +// +u4Byte +PHY_RFShadowRead( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte Offset); + +VOID +PHY_RFShadowWrite( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte Offset, + IN u4Byte Data); + +BOOLEAN +PHY_RFShadowCompare( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte Offset); + +VOID +PHY_RFShadowRecorver( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte Offset); + +VOID +PHY_RFShadowCompareAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRecorverAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowCompareFlagSet( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte Offset, + IN u1Byte Type); + +VOID +PHY_RFShadowRecorverFlagSet( + IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte Offset, + IN u1Byte Type); + +VOID +PHY_RFShadowCompareFlagSetAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRecorverFlagSetAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRefresh( + IN PADAPTER Adapter); + + +#endif diff --git a/network/wlan/WDI/HAL/HalPowerSave.h b/network/wlan/WDI/HAL/HalPowerSave.h new file mode 100644 index 00000000..fa5934c4 --- /dev/null +++ b/network/wlan/WDI/HAL/HalPowerSave.h @@ -0,0 +1,138 @@ +#ifndef __INC_HALPOWERSAVE_H +#define __INC_HALPOWERSAVE_H + +//=========================================================== +// Defines +//=========================================================== + +//=========================================================== +// Enums +//=========================================================== + +//=========================================================== +// Structures +// Driver context for LPS 32K Close IO Power +typedef struct _LPS_DEEP_SLEEP_CONTEXT +{ + BOOLEAN bEnable; + pu1Byte pStaticConfigureFile; + pu1Byte pDynamicConfigureFile; + u4Byte ConfigurationFileOffset; + u2Byte ConfigureFileLengthForPTK; + u2Byte ConfigureFileLengthForGTK; + BOOLEAN bChangeTxBoundaryInProgress; + BOOLEAN bH2CSetPartialOffParam; + BOOLEAN bEnterLPSFail; +}LPS_DEEP_SLEEP_CONTEXT,*PLPS_DEEP_SLEEP_CONTEXT; +//=========================================================== + +//=========================================================== +// Function Prototype +//=========================================================== + +VOID +SetFwClockOn( + IN PADAPTER Adapter, + IN u1Byte RpwmVal, + IN BOOLEAN bNeedTurnoffClk + ); + +VOID +SetFwPSAllOn( + IN PADAPTER Adapter + ); + +VOID +SetFwPSRfOn( + IN PADAPTER Adapter + ); + +VOID +SetFwPSRFOffLowPower( + IN PADAPTER Adapter + ); + +VOID +FwClockOffTimerCallback( + IN PRT_TIMER pTimer + ); + + +VOID +FwClockOffWorkItemCallback( + IN PVOID pContext + ); + + +u4Byte +FwLeisurePSLeave( + IN PADAPTER Adapter, + IN PH2C_CMD_8192C pPwrModeCmd + ); + +u4Byte +FwLeisurePSEnter( + IN PADAPTER Adapter, + IN PH2C_CMD_8192C pPwrModeCmd + ); + + +BOOLEAN +FwLPS_IsInPSAndSupportLowPower( + IN PADAPTER Adapter + ); + +VOID +ForceInitFwClockOn( + IN PADAPTER Adapter + ); + +BOOLEAN +ForceInitFwClockOnWithACK( + IN PADAPTER Adapter + ); + +u4Byte +FwInactivePSEnterHandler( + IN PADAPTER Adapter, + IN PH2C_CMD_8192C pH2cCmd + ); + +u4Byte +FwInactivePSLeaveHandler( + IN PADAPTER Adapter, + IN PH2C_CMD_8192C pH2cCmd + ); + +VOID +FwInactivePSEnter( + IN PADAPTER Adapter, + IN u1Byte Mode + ); + +VOID +FwInactivePSLeave( + IN PADAPTER Adapter + ); + +VOID +FwLPSDeepSleepInit( + IN PADAPTER Adapter +); + +VOID +FwLPSDeepSleepDeInit( + IN PADAPTER Adapter +); + +BOOLEAN +FwLPSCheckChangeTxBoundary( + IN PADAPTER pAdapter +); + +BOOLEAN +FwLPSCheckEnterLPSFail( + IN PADAPTER pAdapter +); + +#endif // end of __INC_HALPOWERSAVE_H diff --git a/network/wlan/WDI/HAL/HalPwrSeqCmd.h b/network/wlan/WDI/HAL/HalPwrSeqCmd.h new file mode 100644 index 00000000..0fb66450 --- /dev/null +++ b/network/wlan/WDI/HAL/HalPwrSeqCmd.h @@ -0,0 +1,118 @@ +#ifndef REALTEK_POWER_SEQUENCE_CMD +#define REALTEK_POWER_SEQUENCE_CMD + +#include "Precomp.h" + +/*---------------------------------------------*/ +//3 The value of cmd: 4 bits +/*---------------------------------------------*/ +#define PWR_CMD_READ 0x00 + // offset: the read register offset + // msk: the mask of the read value + // value: N/A, left by 0 + // note: dirver shall implement this function by read & msk +#define PWR_CMD_WRITE 0x01 + // offset: the read register offset + // msk: the mask of the write bits + // value: write value + // note: driver shall implement this cmd by read & msk after write +#define PWR_CMD_POLLING 0x02 + // offset: the read register offset + // msk: the mask of the polled value + // value: the value to be polled, masked by the msd field. + // note: driver shall implement this cmd by + // do{ + // if( (Read(offset) & msk) == (value & msk) ) + // break; + // } while(not timeout); +#define PWR_CMD_DELAY 0x03 + // offset: the value to delay + // msk: N/A + // value: the unit of delay, 0: us, 1: ms + +#define PWR_CMD_END 0x04 + // offset: N/A + // msk: N/A + // value: N/A + +/*---------------------------------------------*/ +//3 The value of base: 4 bits +/*---------------------------------------------*/ + // define the base address of each block +#define PWR_BASEADDR_MAC 0x00 +#define PWR_BASEADDR_USB 0x01 +#define PWR_BASEADDR_PCIE 0x02 +#define PWR_BASEADDR_SDIO 0x03 + +/*---------------------------------------------*/ +//3 The value of interface_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_INTF_SDIO_MSK BIT0 +#define PWR_INTF_USB_MSK BIT1 +#define PWR_INTF_PCI_MSK BIT2 +#define PWR_INTF_ALL_MSK (BIT0|BIT1|BIT2|BIT3) + +/*---------------------------------------------*/ +//3 The value of fab_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_FAB_TSMC_MSK BIT0 +#define PWR_FAB_UMC_MSK BIT1 +#define PWR_FAB_ALL_MSK (BIT0|BIT1|BIT2|BIT3) + +/*---------------------------------------------*/ +//3The value of cut_msk: 8 bits +/*---------------------------------------------*/ +#define PWR_CUT_TESTCHIP_MSK BIT0 +#define PWR_CUT_A_MSK BIT1 +#define PWR_CUT_B_MSK BIT2 +#define PWR_CUT_C_MSK BIT3 +#define PWR_CUT_D_MSK BIT4 +#define PWR_CUT_E_MSK BIT5 +#define PWR_CUT_F_MSK BIT6 +#define PWR_CUT_G_MSK BIT7 +#define PWR_CUT_ALL_MSK 0xFF + + +typedef enum _PWRSEQ_CMD_DELAY_UNIT_ +{ + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +} PWRSEQ_DELAY_UNIT; + +typedef struct _WL_PWR_CFG_ +{ + u2Byte offset; + u1Byte cut_msk; + u1Byte fab_msk:4; + u1Byte interface_msk:4; + u1Byte base:4; + u1Byte cmd:4; + u1Byte msk; + u1Byte value; + +} WLAN_PWR_CFG, *PWLAN_PWR_CFG; + + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk +#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk +#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk +#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + + +//================================================================================ +// Prototype of protected function. +//================================================================================ +BOOLEAN +HalPwrSeqCmdParsing( + IN PADAPTER pAdapter, + IN u1Byte CutVersion, + IN u1Byte FabVersion, + IN u1Byte InterfaceType, + IN WLAN_PWR_CFG PwrCfgCmd[] + ); + +#endif diff --git a/network/wlan/WDI/HAL/HalSIC.h b/network/wlan/WDI/HAL/HalSIC.h new file mode 100644 index 00000000..ab46b9b3 --- /dev/null +++ b/network/wlan/WDI/HAL/HalSIC.h @@ -0,0 +1,122 @@ +#ifndef __INC_HALSIC_H +#define __INC_HALSIC_H + +//================================================================== +// Note: If SIC_ENABLE under PCIE, because of the slow operation +// you should +// 1) "#define USE_WORKITEM 1" in PrecompInc.h. +// 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows +// 3) "#define LOAD_FIRMWARE_FROM_HEADER 0" in Precomp.h.WlanE.Windows if needed. +// +#if (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1) +#define SIC_ENABLE 1 +#define SIC_HW_SUPPORT 1 +#else +#define SIC_ENABLE 0 +#define SIC_HW_SUPPORT 0 +#endif +//================================================================== + + +#define SIC_MAX_POLL_CNT 5 + +#if(SIC_HW_SUPPORT == 1) +#define SIC_CMD_READY 0 +#define SIC_CMD_PREWRITE 0x1 + +#define SIC_CMD_WRITE_88E 0x40 +#define SIC_CMD_PREREAD_88E 0x2 +#define SIC_CMD_READ_88E 0x80 +#define SIC_CMD_INIT_88E 0xf0 +#define SIC_INIT_VAL_88E 0xff + +#define SIC_INIT_REG_88E 0x1b7 +#define SIC_CMD_REG_88E 0x1EB // 1byte +#define SIC_ADDR_REG_88E 0x1E8 // 1b4~1b5, 2 bytes +#define SIC_DATA_REG_88E 0x1EC // 1b0~1b3 + +#define SIC_CMD_WRITE_92C 0x11 +#define SIC_CMD_PREREAD_92C 0x2 +#define SIC_CMD_READ_92C 0x12 +#define SIC_CMD_INIT_92C 0x1f +#define SIC_INIT_VAL_92C 0xff + +#define SIC_INIT_REG_92C 0x1b7 +#define SIC_CMD_REG_92C 0x1b6 // 1byte +#define SIC_ADDR_REG_92C 0x1b4 // 1b4~1b5, 2 bytes +#define SIC_DATA_REG_92C 0x1b0 // 1b0~1b3 + + +#define GET_SIC_CMD_READ(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_CMD_READ_88E : SIC_CMD_READ_92C + +#define GET_SIC_CMD_WRITE(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_CMD_WRITE_88E : SIC_CMD_WRITE_92C + +#define GET_SIC_INIT_REG(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_INIT_REG_88E : SIC_INIT_REG_92C + +#define GET_SIC_INIT_VAL(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_INIT_VAL_88E : SIC_INIT_VAL_92C + +#define GET_SIC_CMD_INIT(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_CMD_INIT_88E : SIC_CMD_INIT_92C + + +#else +#define SIC_CMD_READY 0 +#define SIC_CMD_WRITE 1 +#define SIC_CMD_READ 2 + +#define SIC_CMD_REG_88E 0x1EB // 1byte +#define SIC_ADDR_REG_88E 0x1E8 // 1b9~1ba, 2 bytes +#define SIC_DATA_REG_88E 0x1EC // 1bc~1bf + +#define SIC_CMD_REG_92C 0x1b8 // 1byte +#define SIC_ADDR_REG_92C 0x1b9 // 1b9~1ba, 2 bytes +#define SIC_DATA_REG_92C 0x1bc // 1bc~1bf + +#define GET_SIC_CMD_READ(_Adapter) SIC_CMD_READ +#define GET_SIC_CMD_WRITE(_Adapter) SIC_CMD_WRITE + +#endif + + +#define GET_SIC_CMD_REG(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_CMD_REG_88E : SIC_CMD_REG_92C + +#define GET_SIC_CMD_PREREAD(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_CMD_PREREAD_88E : SIC_CMD_PREREAD_92C + +#define GET_SIC_ADDR_REG(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_ADDR_REG_88E : SIC_ADDR_REG_92C + +#define GET_SIC_DATA_REG(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter)? SIC_DATA_REG_88E : SIC_DATA_REG_92C + + +VOID +SIC_SetBBReg( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +SIC_QueryBBReg( + IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +SIC_Init( + IN PADAPTER Adapter + ); + +BOOLEAN +SIC_LedOff( + IN PADAPTER Adapter + ); +#endif diff --git a/network/wlan/WDI/HAL/HalSdio.h b/network/wlan/WDI/HAL/HalSdio.h new file mode 100644 index 00000000..ec4006cf --- /dev/null +++ b/network/wlan/WDI/HAL/HalSdio.h @@ -0,0 +1,1107 @@ +#ifndef __INC_HALSDIO_H +#define __INC_HALSDIO_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalSdio.h + +Abstract: + Prototype of HalsdioXXX() and related data structure. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2010-12-12 Roger Create. + +--*/ + +#define SUPPORT_HW_RADIO_DETECT(_Adapter) TRUE + +#define DRIVER_EARLY_INT_TIME 0x10 +#define BCN_DMA_ATIME_INT_TIME 0x02 + + +#define MAX_NUM_OUT_PIPE 16 +#define MAX_NUM_SDIO_TX_QUEUE 3 + +// +// <Roger_Notes> The number of OutPipe request must larger than or equal to the number of +// pending request for each pipe. 2009. 01. 12. +// +#define MAX_NUM_REQUEST_PER_OUT_PIPE 8 +#define MAX_NUM_REQUEST_PER_IN_PIPE 128 + +#define MAX_NUM_REQUEST_PER_TX_QUEUE 3 +#define MAX_NUM_REQUEST_PER_RX_QUEUE 1 + +#define HAL_SDIO_COMPLETED_OK BIT1 +#define HAL_SDIO_COMPLETED_ERROR BIT2 +#define HAL_SDIO_COMPLETED_CANCELED BIT3 + +#define SDIO_TRANSFERS_MASK (DF_TX_BIT | DF_RX_BIT | DF_IO_BIT) +#define SDIO_TX_TRANSFERS_MASK DF_TX_BIT +#define SDIO_RX_TRANSFERS_MASK DF_RX_BIT + +#define SDIO_TX_TRANSFER_SIZE 64 + +#define RT_DISABLE_SDIO_TX_TRANSFERS(__pAdapter) RT_DISABLE_FUNC(__pAdapter, SDIO_TX_TRANSFERS_MASK) +#define RT_ENABLE_SDIO_TX_TRANSFERS(__pAdapter) RT_ENABLE_FUNC(__pAdapter, SDIO_TX_TRANSFERS_MASK) +#define RT_DISABLE_SDIO_RX_TRANSFERS(__pAdapter) RT_DISABLE_FUNC(__pAdapter, SDIO_RX_TRANSFERS_MASK) +#define RT_ENABLE_SDIO_RX_TRANSFERS(__pAdapter) RT_ENABLE_FUNC(__pAdapter, SDIO_RX_TRANSFERS_MASK) +#define RT_DISABLE_SDIO_TRANSFERS(__pAdapter) RT_DISABLE_FUNC(__pAdapter, SDIO_TRANSFERS_MASK) +#define RT_ENABLE_SDIO_TRANSFERS(__pAdapter) RT_ENABLE_FUNC(__pAdapter, SDIO_TRANSFERS_MASK) + +#define RT_SDIO_CANNOT_IO(__pAdapter) \ + ((__pAdapter)->bDriverStopped || \ + (__pAdapter)->bSurpriseRemoved || \ + RT_IS_FUNC_DISABLED((__pAdapter), DF_IO_BIT)) + +#define RT_SDIO_CANNOT_TX(__pAdapter) \ + ((__pAdapter)->bDriverStopped || \ + (__pAdapter)->bSurpriseRemoved || \ + RT_IS_FUNC_DISABLED((__pAdapter), DF_TX_BIT)) + +#define RT_SDIO_CANNOT_RX(__pAdapter) \ + ((__pAdapter)->bDriverStopped || \ + (__pAdapter)->bSurpriseRemoved || \ + RT_IS_FUNC_DISABLED((__pAdapter), DF_RX_BIT)) + +#define RT_GetInterfaceSelection(_Adapter) ((u1Byte)GET_HAL_DATA(_Adapter)->InterfaceSel) + +#define IS_NEED_OFFSET_ON_AMPDU(_Adapter) FALSE +#define IS_CHK_AMSDU_BUF_CNT(_Adapter) FALSE +#define IS_RW_PTR(_Adapter) FALSE +#define IS_SET_RX_AGGR(_Adapter) FALSE +#define IS_RSTO_WMM_AFTER_SCAN(_Adapter) FALSE + +typedef struct _SDIO_OUT_RESOURCE +{ + s4Byte PipeCnt; // # of OUT pipes. + s4Byte QueueCnt; // # of Tx Queues + + // + // Memory block of SDIO_OUT_CONTEXT objects. + // + pu1Byte SendContextsBuffer; + u4Byte SendContextsBufferSz; + + // + // Queue to manage free SDIO_OUT_CONTEXT objects. + // + RT_LIST_ENTRY TxFreeContextList; // An link list of SDIO_OUT_CONTEXT. Note that, every out pipe shall get and return SDIO_OUT_CONTEXT from and to here. + u4Byte TxFreeContextCount; // Number of conext available to use. + s4Byte TxContextCount; // Total number of SDIO_OUT_CONTEXT allocated. +} SDIO_OUT_RESOURCE, *PSDIO_OUT_RESOURCE; + +typedef struct _SDIO_OUT_CONTEXT +{ + RT_LIST_ENTRY List; + + // + // TODO: Replace pTcb as HalReserved[0]. + // + pu1Byte Buffer; // Pointer to the buffer to Transfer data to SDIO Host. + u4Byte BufLen; // Length of Buffer. + PRT_TCB pTcb; // Pointer to corresponding + BOOLEAN bData0Byte; // TRUE if this context is used as 0-byte padding for 512N-byte buffer on USB2.0 or 64N-byte on USB1.1. + BOOLEAN bTxPending; // TRUE if this context is pending in USBD. + u1Byte PendingCount; // Used in CheckForHang check sending stuck or not. + u1Byte TxQueueIndex; // An index to the Tx Queue, i.e., 0: HIQ, 1: MIQ, 2:LOQ + u1Byte AggrNum; // SDIO Tx aggregation number. + + // + // RT_PLATFORM reserved. + // For example, + // - on Windows NDIS5/WDM: [0]: PADAPTER, [1]: NULL, [2]: NULL. + // - On Windows NDIS6/WDF: [0]: PADAPTER, [1]: NULL, [2]: WDFREQUEST. + // + PVOID PlatformReserved[4]; +} SDIO_OUT_CONTEXT, *PSDIO_OUT_CONTEXT; + + +typedef struct _SDIO_IN_RESOURCE +{ + s4Byte PipeCnt; // # of IN pipes. + s4Byte QueueCnt; // # of Rx Queues + + // + // Memory block of SDIO_IN_CONTEXT objects. + // + pu1Byte ContextsBuffer; + u4Byte ContextsBufferSz; + + // + // Queue to manage free USB_IN_CONTEXT objects. + // + RT_LIST_ENTRY FreeContextList; // An link list of USB_IN_CONTEXT. Note that, every out pipe shall get and return USB_IN_CONTEXT from and to here. + u4Byte FreeContextCount; // Current number of conext available to use. + s4Byte ContextCounAlloc; // Total number of USB_IN_CONTEXT allocated. +} SDIO_IN_RESOURCE, *PSDIO_IN_RESOURCE; + +typedef struct _SDIO_IN_CONTEXT +{ + RT_LIST_ENTRY List; + + pu1Byte Buffer; // Pointer to the buffer to IN from USBD. + u4Byte BufferLen; // Length of Buffer allowed USBD to use. + u4Byte BufLenUsed; // Length of Buffer used for the bulk IN transfer. + BOOLEAN bRxPending; // TRUE if this context is pending in USBD. + u1Byte RxPipeIndex; // An index to the IN pipe. + + // + // RT_PLATFORM reserved. + // For example, + // - on Windows NDIS5/WDM: [0]:PADAPTER, [1]: NULL, [2]: NULL. + // - On Windows NDIS6/WDF: + // + PVOID PlatformReserved[4]; + + // + // HAL reserved: Data: pRFD, CMD + // + PVOID HalReserved[1]; + +#if VISTA_USB_RX_REVISE + u4Byte RetStatus; +#endif +} SDIO_IN_CONTEXT, *PSDIO_IN_CONTEXT; + + +typedef struct _HAL_SDIO_INFO +{ + SDIO_OUT_RESOURCE OutResource; + SDIO_IN_RESOURCE InResource; +} HAL_SDIO_INFO, *PHAL_SDIO_INFO; + +#define HAL_BUS_INFO_TYPE HAL_SDIO_INFO + +#define GET_HAL_BUS_INFO(__pAdapter) ((HAL_BUS_INFO_TYPE*)((__pAdapter)->pHalBusInfo)) + +#define GET_USB_DEVICE_SPEED(_pAdapter) USB_DEVICE_SPEED_FULL + + +#define GET_OUT_RES(__pBusInfo) (&((__pBusInfo)->OutResource)) +#define GET_IN_RES(__pBusInfo) (&((__pBusInfo)->InResource)) +#define FREE_OUT_CONTEXT_CNT(__pAdapter) ( GET_OUT_RES(GET_HAL_BUS_INFO(__pAdapter))->TxFreeContextCount ) + +//================================================================================ + +typedef struct _HAL_DATA_SDIO +{ + // + // Read-only hardware information, it should not be changed after set. + // Make a copy and change its copy if need. + // + u2Byte HardwareType; + VERSION_8192C VersionID; + VERSION_CVID CVID_Version; // For Version of Structure ChipVersion: 0:v1(before 8703B), 1:v2(since 8703B) + + RT_MULTI_FUNC MultiFunc; // For multi-function consideration. + RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. + RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO + //u1Byte HwROFEnable; // Enable GPIO[9] as WL RF HW PDn source + + + // + // For SDIO Interface HAL related + // + BOOLEAN bMacPwrCtrlOn; //Auto FSM to Turn On, include clock, isolation, power control for MAC only + + RT_BUS_TYPE BusType; + RT_EEPROM_TYPE EEType; + BOOLEAN bMPMode; + u1Byte MWIEnable; + u1Byte AutoloadFailFlag; + BOOLEAN bNOPG; + + // TODO: Let it be platform independent. + PlatformMutex mxRFOperate; // RF access lock + PlatformMutex mxCCKControl; + PlatformMutex mxChnlBwControl; + + // add for 92D Phy mode/mac/Band mode + //MACPHY_MODE_8192D MacPhyMode92D; + //u1Byte BandType92D; //0: 2.4G, 1: 5G + BAND_TYPE CurrentBandType; //0:2.4G, 1:5G + BAND_TYPE LastBandType; //0:2.4G, 1:5G + BAND_TYPE BandSet; + BOOLEAN bIsVS; + + // + // Add For EEPROM Efuse switch and Efuse Shadow map Setting + // + BOOLEAN EepromOrEfuse; + u1Byte EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) + u2Byte EfuseUsedBytes; + u1Byte EfuseUsedPercentage; + EFUSE_HAL EfuseHal; + + // + // For 92C USB endpoint setting + // + u1Byte OutEpQueueSel; + u1Byte OutEpNumber; + + // + //SDIO Tx FIFO related. + // + u1Byte SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; + u2Byte SdioTxFIFOFreePage8814A[SDIO_TX_FREE_PG_QUEUE_8814A]; //3 20130422 KaiYuan modify for 8814; for other IC, it is u1Byte + u4Byte SdioTxRsvdPageSize; // for download beacon queue + + // + // Default Settings + // + u4Byte ChipID; + u4Byte ChipVer; + BOOLEAN bNicWirelessMode; + BOOLEAN bIs88eSeries; + BOOLEAN bIsNicExistBt; + BOOLEAN bEnableSingleAmpdu; + BOOLEAN bNeedExtIQK; + BOOLEAN bCheckHiddenSsid; + BOOLEAN bDisableRtsOnAmpdu; + BOOLEAN bSupClkOnExcepResn; + u2Byte MaxRxDmaBufferSize; + u2Byte MaxTxBufSize; + u2Byte TcbNumOfMemSize0; + u2Byte TcbNumOfMemSize1; + u2Byte TxDescNum; + u2Byte TxDescNumBeQ; + u2Byte TxDescNumMp; + u2Byte TxDescNumBeQMp; + u2Byte MaxRxBufSize; + u2Byte MaxSubframeCntMmSize0; + u2Byte MaxSubframeCntMmSize1; + u2Byte RfdNumMmSize0; + u2Byte RxDescNumMmSize0; + u2Byte RfdNumMmSize1; + u2Byte RxDescNumMmSize1; + BOOLEAN bNicSupportWapi; + BOOLEAN bRemoveZeroLenBuf; + BOOLEAN bLeavePsBeforeEnNic; + + // + // EEPROM setting. + // + u1Byte EEPROMVersion; + u2Byte EEPROMVID; + u2Byte EEPROMPID; + u2Byte EEPROMSVID; + u2Byte EEPROMSDID; + u1Byte EEPROMCustomerID; + u1Byte EEPROMSubCustomerID; + u1Byte EEPROMRegulatory; + u1Byte EEPROMThermalMeter; // ThermalMeter value. + u1Byte EEPROMBluetoothCoexist; + u1Byte EEPROMBluetoothType; + u1Byte EEPROMBluetoothAntNum; + u1Byte EEPROMBluetoothSingleAntPath; + u2Byte EEPROMChannelPlan; + // 2011/03/10 Vivi Add for 92C/D common binary. + u1Byte USBDummyOffset; + u1Byte USBALLDummyLength; + u1Byte EFUSECloudKey_EX[EEPROM_CLOUD_KEY_LENGTH_EX]; + + // + // SDIO ISR Related + // + // Interrupt relatd register information. + RT_INT_REG IntArray[1]; + RT_INT_REG IntrMask[1]; + RT_INT_REG IntrMaskToClear[1]; + RT_INT_REG SysIntArray[1]; + RT_INT_REG SysIntrMask[1]; + RT_INT_REG SysIntrMaskToClear[1]; + u4Byte RxIntLength; // The length of rx packet from the intrrupt information in SDIO only. + LOG_INTERRUPT InterruptLog; + LOG_SYS_INTERRUPT SysInterruptLog; + + // + // The same as 92CE. May merge 92CU and 92CE into the other struct + // + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + + //s2Byte index_mapping_DPK_current[4][index_mapping_DPK_NUM]; + + BOOLEAN bRfPiEnable; + BOOLEAN bReloadtxpowerindex; + BOOLEAN bDoneTxpower; + u1Byte CrystalCap; + u1Byte CrystalFreq; + u1Byte CrystalSrc; + + s1Byte OFDM_index_HP[2]; + s1Byte CCK_index_HP; + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + + BOOLEAN bAPKdone; + BOOLEAN bDPKdone[2]; + + //for TxPwrTracking + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + //for IQK + BOOLEAN bIQKInitialized; + BOOLEAN bAntennaDetected; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + + //---------------------------------------------------------------------------------// + //3 [2.4G] + u1Byte Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; + u1Byte Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; + //If only one tx, only BW20 and OFDM are used. + s1Byte CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + //3 [5G] + u1Byte Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G]; + u1Byte Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; + s1Byte OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s1Byte BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + + // + // TX power by rate table at most 4RF path. + // The register is + // + // VHT TX power by rate off setArray = + // Band:-2G&5G = 0 / 1 + // RF: at most 4*4 = ABCD=0/1/2/3 + // CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 + // + u1Byte TxPwrByRateTable; + u1Byte TxPwrByRateBand; + s1Byte TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RATE]; + //---------------------------------------------------------------------------------// + + + u1Byte PowerIndex_backup[6]; + u1Byte TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; + u1Byte TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr + u1Byte TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr + s1Byte TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // HT 20<->40 Pwr diff + u1Byte TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT<->legacy pwr diff + + // Power Limit Table for 2.4G + s1Byte TxPwrLimit_2_4G[MAX_REGULATION_NUM] + [MAX_2_4G_BANDWITH_NUM] + [MAX_RATE_SECTION_NUM] + [CHANNEL_MAX_NUMBER_2G] + [MAX_RF_PATH]; + + // Power Limit Table for 5G + s1Byte TxPwrLimit_5G[MAX_REGULATION_NUM] + [MAX_5G_BANDWITH_NUM] + [MAX_RATE_SECTION_NUM] + [CHANNEL_MAX_NUMBER_5G] + [MAX_RF_PATH]; + + u1Byte Regulation2_4G; + u1Byte Regulation5G; + + // Store the original power by rate value of the base of each rate section of rf path A & B + u1Byte TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; + u1Byte TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; + + // Used for TX power setting shadow map. + u1Byte TxPwrShadow[MAX_RF_PATH][DESC_RATEMAX]; + + // For power group + u1Byte PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; + u1Byte PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; + + u1Byte LegacyHTTxPowerDiff; // Legacy to HT rate power diff + + // Read/write are allow for following hardware information variables + u1Byte DefaultInitialGain[4]; + u1Byte pwrGroupCnt; + u4Byte MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; + u4Byte CCKTxPowerLevelOriginalOffset; + u1Byte TxPowerLevelCCK[14]; // CCK channel 1~14 + u1Byte TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 + u1Byte TxPowerLevelOFDM5G[14]; // OFDM 5G + u1Byte AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D + + u4Byte AntennaTxPath; // Antenna path Tx (Used in MP driver) + u4Byte AntennaRxPath; // Antenna path Rx (Used in MP driver) + u4Byte ValidTxPath; // Valid Antenna path Tx (Used in Normal driver) + u4Byte ValidRxPath; // Valid Antenna path Tx (Used in Normal driver) + u1Byte CCKRxPath; //Back CCX Rx Path + u1Byte CCKTxPath; //Back CCX Tx Path + + u4Byte LedControlNum; + u4Byte LedControlMode; + + // The current Tx Power Level + u1Byte CurrentCckTxPwrIdx; + u1Byte CurrentOfdm24GTxPwrIdx; + u1Byte CurrentBW2024GTxPwrIdx; + u1Byte CurrentBW4024GTxPwrIdx; + u1Byte OriginalCckTxPwrIdx; + u1Byte OriginalOfdm24GTxPwrIdx; + + u1Byte EEPROMC9; + u1Byte EEPROMCC; + u1Byte PAMode; + + u1Byte InternalPA5G[2]; //pathA / pathB + u1Byte Delta_IQK; + u1Byte Delta_LCK; + + // For compatiable compile for 92D. + u4Byte RegA24; + u1Byte RegC04; + u4Byte RegD04; + u4Byte RegRF3C[2]; //pathA / pathB + u4Byte RegRF36; + + HAL92C_P2P_PS_OFFLOAD p2pFwPsOffload; + + // + // Read/write are allow for following hardware information variables + // + RF_TYPE_E RFChipID; + + + // Customer-defined power by rate / power limit table loading status + u1Byte CustomPwrByRateFileStatus; + u1Byte CustomPwrLimitFileStatus; + + u1Byte CurrentPwrLimitTableSel; // Primary = 0/Secondary = 1 + + u1Byte DynamicTxPwrLoadingInfo; // Dynamic Tx Power Table Loading info + u1Byte TxPwrTableDumpInfo; // Tx Power Table Dump info + + //2 Management related + WIRELESS_MODE CurrentWirelessMode; //For 8185 + u1Byte CurrentChannel; + RT_TIMER SwChnlTimer; +#if USE_WORKITEM + RT_WORK_ITEM SwChnlWorkItem; +#endif + BOOLEAN SwChnlInProgress; + u1Byte SwChnlStage; + u1Byte SwChnlStep; + + // bandwidth mode + CHANNEL_WIDTH CurrentChannelBW; + RT_TIMER SetBWModeTimer; + u1Byte SetBWModeInProgress; +#if USE_WORKITEM + RT_WORK_ITEM SetBWModeWorkItem; + RT_WORK_ITEM RtCheckForHangWorkItem; + RT_WORK_ITEM RtCheckResetWorkItem; +#endif + + BOOLEAN RFOff; + BOOLEAN bIntolerantAC; + BOOLEAN AdhocLinkState; + BOOLEAN SetRFPowerStateInProgress; + + //2 Tx Related variables + u2Byte ShortRetryLimit; + u2Byte LongRetryLimit; + + //2 Rx Related variables + u2Byte EarlyRxThreshold; + u4Byte ReceiveConfig; + u2Byte RxTag; + + //2 QoS Related variable + u1Byte AcmControl; + + u4Byte FWChannelSwitchComplete; + BOOLEAN bSwChnlAndSetBWInProgress; + u1Byte CurrentCenterFrequencyIndex1; + BOOLEAN bSwChnl; + BOOLEAN bSetChnlBW; + RT_WORK_ITEM SwChnlAndSetBWModeWorkItem; + + //2 Led Related variable + LED_STRATEGY_SDIO LedStrategy; + LED_SDIO SwLed0; + LED_SDIO SwLed1; + LED_SDIO SwLed2; + LED_SDIO SwLed3; + LED_SDIO SwLedAll; + BOOLEAN bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. + + + // RF power state: on, sleep, off. + RT_RF_POWER_STATE eRFPowerState; + + // Channel Access related register. + u1Byte SlotTime; + u4Byte SifsTime; + + // Command + u1Byte Command; + + // Data Rate Config. Added by Annie, 2006-04-13. + u2Byte BasicRateSet; + BOOLEAN bShortPreamble; + // + // CCX Radio Measurement; + // + u1Byte LastClmDur; + u1Byte LastNhmDur; + u4Byte ClmAcc; + u4Byte ClmDurAcc; + u4Byte NhmAcc[8]; + u4Byte NhmDurAcc; + + + // + // Default setting (initialized from registry). + // + BOOLEAN bRegUseLed; // 0: disable LED, 1: eanble LED. + + + // + // High Power Mechanism. + // + // For Default UI Tx power modification + s4Byte DefaultTxPwrDbm; + s4Byte MinCCKDbm; + s4Byte MinLOFDMDbm; + s4Byte MinHOFDMDbm; + s4Byte MinPwrDbm; + s4Byte MaxCCKDbm; + s4Byte MaxLOFDMDbm; + s4Byte MaxHOFDMDbm; + s4Byte MaxPwrDbm; + + // + // Turbo Mode Mechanism. Added by Roger, 2006.12.15. + // + BOOLEAN bInTurboMode; + + // Interface selection. Added by Annie, 2005-11-18. + u1Byte InterfaceSel; + u1Byte PackageType; + u1Byte RFEType; + BOOLEAN bIsMPChip; + + s1Byte BufOfLines[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + + + BOOLEAN bSendingBeacon; // TRUE if we are sending beacon to host control and not yet completed. + + // Sw Antenna Diversity + //20070103 porting by David + BOOLEAN bRegSwAntennaDiversityMechanism; // TRUE if S/W antenna diversity mechanism is allowed, see also EEPROMSwAntennaDiversity and bSwAntennaDiverity. + BOOLEAN bAntennaDiversityTimerIssued; + RT_WORK_ITEM SwAntennaWorkItem; + u1Byte CurrAntennaIndex; // Index to current Antenna (both Tx and Rx). + u1Byte AdTickCount; // Times of SwAntennaDiversityTimer happened. + u1Byte AdCheckPeriod; // # of period SwAntennaDiversityTimer to check Rx signal strength for SW Antenna Diversity. + u1Byte AdMinCheckPeriod; // Min value of AdCheckPeriod. + u1Byte AdMaxCheckPeriod; // Max value of AdCheckPeriod. + BOOLEAN bSwAntennaDiverity; // TRUE if we want to enable SW Antenna Diversity mechanism. + RT_TIMER SwAntennaDiversityTimer; // Timer object for SW Antenna Diversity mechanism. + u4Byte AdRxOkCnt; // ROK packet count from current BSS in ANTENNA_DIVERSITY_TIMER_PERIOD. + s4Byte AdRxSignalStrength; // Rx signal strength for Antenna Diversity, which had been smoothing, its valid range is [0,100]. + s4Byte AdRxSsThreshold; // Signal strength threshold to switch antenna. + s4Byte AdMaxRxSsThreshold; // Max value of AdRxSsThreshold. + BOOLEAN bAdSwitchedChecking; // TRUE if we shall shall check Rx signal strength for last time switching antenna. + s4Byte AdRxSsBeforeSwitched; // Rx signal strength before we swithed antenna. + // + //1 The following was added for 8192sUsb + + /* Firmware related */ + PRT_FIRMWARE pFirmware; + u1Byte RegFWOffload; + u4Byte RsvdBitMap; + + // Beamforming RF path number + u1Byte RegBeamformerCapRfNum; + u1Byte RegBeamformeeCapRfNum; + + /*PHY related*/ + BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D + + u1Byte NumTotalRFPath; + + /*Last RxDesc TSF value*/ + u4Byte LastRxDescTSFHigh; + u4Byte LastRxDescTSFLow; + + + // + // 8190 40MHz mode + // + u1Byte nCur40MhzPrimeSC; // Control channel sub-carrier + u1Byte nCur80MhzPrimeSC; //used for primary 40MHz of 80MHz mode + + /* Rx Descriptor Debug message for aggregation related histogram */ + u1Byte nRxAMPDU_AggrNum; + u2Byte nRxAMPDU_Size; + + + // + // Joseph test for Silent Reset + // Driver cannot open file when it is not in initialization state. + // So we need a buffer to save the content of configuration file for reset use. + // + s1Byte BufOfLines1[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufOfLines2[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufOfLines3[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufOfLines4[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufOfLines5[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufOfLines6[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + + s4Byte nLinesRead1; + s4Byte nLinesRead2; + s4Byte nLinesRead3; + s4Byte nLinesRead4; + s4Byte nLinesRead5; + s4Byte nLinesRead6; + + s1Byte BufOfLinesPwrLmt[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s4Byte nLinesReadPwrLmt; + s1Byte BufOfLinesPwrByRate[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s4Byte nLinesReadPwrByRate; + + s1Byte BufRadioA[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufRadioB[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufRadioC[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufRadioD[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s4Byte nLinesBufRadioA; + s4Byte nLinesBufRadioB; + s4Byte nLinesBufRadioC; + s4Byte nLinesBufRadioD; + + BOOLEAN bCCKinCH14; + s1Byte CCK_index; + s1Byte OFDM_index[2]; + u4Byte TXPowerTrackingCallbackCnt; //debug only + + + //cosa add for 2T4R/1T2R software control 10/24/2007 + u1Byte RF_Type;// 1 means 2T4R, 0 means 1T2R + + // For EDCA Turbo mode + BOOLEAN bIsAnyNonBEPkts; + + u8Byte SystemStartTime; + u8Byte SystemCurrTime; + + // Use to calculate PWBD. + s4Byte UndecoratedSmoothedPWDB; + s4Byte UndecoratedSmoothedCCK; + s4Byte UndecoratedSmoothedOFDM; + s4Byte UndecoratedSmoothedBeacon; + u4Byte RxRate; + u8Byte PacketMap; + u4Byte OFDM_pkt; + u1Byte ValidBit; + s4Byte EntryMinUndecoratedSmoothedPWDB; + s4Byte EntryMaxUndecoratedSmoothedPWDB; + s4Byte BT_EntryMinUndecoratedSmoothedPWDB; + s4Byte BT_EntryMaxUndecoratedSmoothedPWDB; + + //SW Antenna Switch + s4Byte RSSI_sum_A; + s4Byte RSSI_cnt_A; + s4Byte RSSI_sum_B; + s4Byte RSSI_cnt_B; + BOOLEAN RSSI_test; + PRT_WLAN_STA RSSI_target; + + u1Byte AntDivCfg; + u1Byte AntDetection; + u1Byte PathDivCfg; + u1Byte TRxAntDivType; // RF type, Read from 88E EFUSE 0xC9 + u1Byte ReverseDPDT; + u4Byte OFDM_Pkt_Cnt; + u4Byte CCK_Pkt_Cnt; + + RT_WORK_ITEM PSDMonitorWorkitem; + + //WLAN PSD for BT AFH + BOOLEAN bPSDinProcess; + RT_TIMER PSDTimer; + u1Byte RSSI_BT; + RT_TIMER PSDTriggerTimer; + //---------------2011.08.24 ------------------ + + // 2008/01/10 MH HW Trun on/off RF according to GPIO1 + RT_WORK_ITEM GPIOChangeRFWorkItem; + // TRUE if RF is turned to OFF by HW (e.g. GPIO1), FALSE otherwise. + BOOLEAN bHwRadioOff; + + // 2010/11/25 Check PBC GPIO + RT_WORK_ITEM GPIOCheckPBCWorkItem; + + // Ratr table used bitmap + u1Byte RATRTableBitmap; + + BOOLEAN bInMonitorMode; // Indicate if underlying h/w is configured in monitor mode. + + //Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 + u1Byte DynamicTxHighPowerLvl; //Tx High power level + u1Byte LastDTPLvl; + + SCAN_OPERATION_BACKUP_OPT ScanOperationBackupOtpType; + RT_WORK_ITEM ScanOperationBackupWorkItem; + + + // RF and BB simple mechanism for synchronizing access. Added by Roger, 2009.06.29. + u4Byte bChangeBBInProgress; // BaseBand RW is still in progress. + u4Byte bChangeRFInProgress; // RF RW is still in progress. + + + RT_WORK_ITEM IOWorkItem; + IO_TYPE CurrentIOType; + BOOLEAN SetIOInProgress; + u1Byte NumOfPipes; + QUEUE_INDEX_LIST OutPipeToTxQueueMap[MAX_NUM_SDIO_TX_QUEUE]; + u1Byte TxQueueToOutPipeMap[MAX_TX_QUEUE]; + + u1Byte DMFlag; // Indicate if each dynamic mechanism's status. + + u1Byte PreRpwmVal; // by tynli. For recording the previous RPWM value. + u1Byte LastHCPWM1Val; + + u4Byte RfRegChnlVal[MAX_RF_PATH]; + + + u1Byte PbcGPIOCnt; + + BOOLEAN bRegUsbInTokenRev; //For Intel ATOM CPU utilization, 2009.06.04. + + + //---------------------------------------------------------------------------- + // RTL8192C USB Tx/Rx Aggregation + //---------------------------------------------------------------------------- + u4Byte TxTransferSize; + +#if TX_AGGREGATION + BOOLEAN UsbTxAggMode; + u1Byte UsbTxAggTotalNum; + u1Byte UsbTxAggDescNum; + //u1Byte UsbTxAggPerBulkNum; +#endif +#if RX_AGGREGATION + + u2Byte HwRxPageSize; // Hardware setting + u4Byte MaxRxAggBlock; + + RX_AGG_MODE RxAggMode; + u1Byte RegRxAggBlockCount; + u1Byte RxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed + u1Byte RegRxAggBlockTimeout; + u1Byte RxAggBlockTimeout; + u1Byte RegRxAggPageCount; + u1Byte RxAggPageCount; // 8192C DMA page count + u1Byte RegRxAggPageTimeout; + u1Byte RxAggPageTimeout; + RT_WORK_ITEM RxAggrSettingWorkItem; +#endif + // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. + BOOLEAN UsbRxHighSpeedMode; + + u1Byte RegTxPause; + + //Add for maintain H2C box number. by tynli. 2009.10.06. + u1Byte LastHMEBoxNum; + u4Byte lastFwCmdElementId; + + RT_WORK_ITEM FillH2CCmdWorkItem; + BOOLEAN bH2CSetInProgress; + RT_TIMER FillH2CCmdTimer; + BOOLEAN H2CStopInsertQueue; //by tynli. 2010.10.07. +#if(FW_QUEME_MECHANISM_NEW != 1) + H2C_CMD_8192C H2CCmd[MAX_H2C_QUEUE_NUM]; //for queuing the h2c cmds which are sent in dispatch level. + u1Byte H2CQueueHead; + u1Byte H2CQueueTail; +#endif + u4Byte h2cStatistics[H2C_STATUS_MAX]; + u1Byte lastSuccessH2cEid; + u1Byte firstFailedH2cEid; + + RT_TIMER DualMacSetOperationForAnotherMacTimer; + + + // Record Fw PS mode status. Added by tynli. 2010.04.19. + u1Byte FwPSState; + BOOLEAN bFwClkChangeInProgress; + BOOLEAN bFwDwRsvdPageInProgress; + // For 32k power save. 2011.03.22. by tynli. + RT_TIMER FwClockOffTimer; + RT_WORK_ITEM HandleH2CJoinBssRptWorkItem; + BOOLEAN bAllowSwToChangeHwClock; //by tynli. for 32k. + BOOLEAN bKeepInPSPeriod; // by tynli. for 32k. + RT_WORK_ITEM FwClockOffWorkItem; + u1Byte HwClkOnExceptionReason; + u1Byte ForceHwClkOnExceptionReason; + +#if RT_PLATFORM == PLATFORM_MACOSX + u1Byte RegBcnCtrlVal; +#else + u4Byte RegBcnCtrlVal; +#endif + + RT_WORK_ITEM ResumeTxBeaconWorkItem; + + // Beacon function related global variable. + u1Byte RegFwHwTxQCtrl; + u1Byte RegReg542; + u1Byte RegCR_1; + BOOLEAN bRegUsbSS; + //Record if Card Disable by HW auto SM. + BOOLEAN bCardDisableHWSM; + + //For check TxDMA error status. + BOOLEAN bClearTxDMAErrorFlag; + u1Byte USBResetTxHangEanble; + + // Record Fw PS mode status. Added by tynli. 2010.04.19. + BOOLEAN bFwCurrentInPSMode; + u2Byte FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. + + // 2010/08/09 MH Add CU power down mode. + BOOLEAN pwrdown; + BOOLEAN bRfOnOffInt;// HW RF on/off interrupt + + // Add Tx Feedback for SDIO, by Hana, 2015.02.10 + // TxFeedback Context Place Holder for Private Data: --------------------------- + // + Only access this private data inside the module by TxFeedbackGetContext() + PRIVATE_DATA_ZONE TxFeedback[TX_FEEDBACK_SIZE_OF_CONTEXT]; + // ---------------------------------------------------------------------- + + BOOLEAN bHostSuspend; // To check Host suspend status on FPGA platform, added by Roger, 2010.09.28. + u2Byte HostSuspendCnt; // Suspend counter for FPGA host, added by Roger, 2010.09.28. + + // 2010/11/22 MH Add for slim combo debug mode selective. + // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. + BOOLEAN SlimComboDbg; + + u1Byte RTSInitRate; // 2010.11.24.by tynli. + RT_WORK_ITEM SetRTSRateWorkItem; + + RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully + RT_AMPDU_BRUST AMPDUBurstModebackup; + u1Byte AMPDUBurstNum; + BOOLEAN bAutoAMPDUBurstMode; + u2Byte AutoAMPDUBurstModeThreshold; + + u2Byte TxHignTPThreshold; + u2Byte RxHignTPThreshold; + + u1Byte SwBeaconType; // The Beacon type defined by BACON_SEND_XX. + + BOOLEAN bMACFuncEnable; + + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + + RT_WORK_ITEM IQKTriggerWorkItem; + RT_WORK_ITEM LCKTriggerWorkItem; + RT_WORK_ITEM DPKTriggerWorkItem; + + s4Byte MinUndecoratedPWDBForDM; + s4Byte LastMinUndecoratedPWDBForDM; + + s1Byte BufOfLinesAGC2_4G[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + s1Byte BufOfLinesAGC5G[MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + + s4Byte nLinesReadAGC2_4G; + s4Byte nLinesReadAGC5G; + +//To reduce stack in phy_SwChnlStepByStep, 20110719 by sherry + SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; + SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; + SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; + + BOOLEAN bPathDiv_Enable; //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19 + + BOOLEAN bPreEdccaEnable; // 2011.11.25. by tynli. + + // FW common structure + FW_COM_STR fwComStr; + + // + // 2011/09/22 MH Add for common PHy intergration interface. + // + DM_ODM_T DM_OutSrc; + BOOLEAN bLinked; + + u1Byte CurrentRARate; + + u1Byte u1RsvdPageLoc[MAX_H2C_CMD_DATA_SIZE]; + u1Byte u1RsvdPageLoc2[MAX_H2C_CMD_DATA_SIZE]; + u1Byte u1RsvdPageLoc3[MAX_H2C_CMD_DATA_SIZE]; + u1Byte u1RsvdPageLocREALWOW[MAX_H2C_CMD_DATA_SIZE]; + u1Byte u1FwPatternRsvdPageLoc[MAX_H2C_CMD_DATA_SIZE]; + u1Byte u1RsvdPageLocScanOffload[MAX_H2C_CMD_DATA_SIZE]; + u1Byte u1RsvdPageFcsLoc[MAX_H2C_CMD_DATA_SIZE]; + + BOOLEAN bReInitLLTTable; + + u1Byte SdioTxSequence; + BOOLEAN bSpurCalComplete; // <20130515, VincentLan> To make sure spur calibration be execute only once + + BOOLEAN bPhyValueInitReady; + + BOOLEAN bNeedIQK; + BOOLEAN bNeedQueuePacketInIQKProgress; + + u1Byte ExternalPA_2G; + u1Byte ExternalLNA_2G; + u1Byte ExternalPA_5G; + u1Byte ExternalLNA_5G; + u2Byte TypeGLNA; + u2Byte TypeGPA; + u2Byte TypeALNA; + u2Byte TypeAPA; + + s1Byte TxBBSwing_2G; + s1Byte TxBBSwing_5G; + + u1Byte RTSEN; + + u1Byte CurrScanOffloadType; //Current scan offload type + + // <VincentL, 130102> add for RfBbGain + u1Byte RfBbGain; + // <VincentL, 131119> Add for KFree Feature Requested by RF David. + u1Byte RfKFreeEnable; + + // <VincentL, 131231> Add to determine IQK ON/OFF in certain case, Suggested by Cheng. + u1Byte IQK_MP_Switch; + + // <VincentL> for FW IQK time measurement + u8Byte IQK_StartTimer; + u8Byte IQK_EndTimer; + + // Rate Adaptive Mask control + BOOLEAN bUseRAMask; + + u1Byte u1ForcedIgiLb; // forced IGI lower bound + u4Byte MacIdPktSleep; + + RT_ADCSMP ADCSmp; + RT_WORK_ITEM ADCSmpWorkItem; + + u1Byte RomDLFwEnable; + u1Byte bP2PInProcess; + u1Byte RxDetectorBackUp; + + BOOLEAN bDropRxPacket; + + BB_INIT_REGISTER RegForRecover[5]; + + RT_WORK_ITEM MacIdSleepWorkItem; + + BOOLEAN bDynTxPwrTblLoadingInProgress; + + SMBIOS_DATA SmbiosData; + u4Byte BackUp_BB_REG_4_2nd_CCA[3]; + BOOLEAN bSWToBW40M; + + //8723D LPS 32K Close Power of IO + LPS_DEEP_SLEEP_CONTEXT LPSDeepSleepContext; +}HAL_DATA_SDIO, *PHAL_DATA_SDIO; + + +#define HAL_DATA_TYPE HAL_DATA_SDIO +#define PHAL_DATA_TYPE PHAL_DATA_SDIO +#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) +#define IS_BOOT_FROM_EFUSE(_Adapter) (!((PHAL_DATA_TYPE)(_Adapter->HalData))->EepromOrEfuse) + +//================================================================================ +// Prototype of functions to export. +//================================================================================ +// +// SDIO Initialization and DeInitialization interfaces. +// +BOOLEAN +HalSdioAllocResource( + IN PADAPTER pAdapter, + IN s4Byte TxQueueCnt, + IN s4Byte RxQueueCnt + ); + +VOID +HalSdioFreeResource( + IN PADAPTER pAdapter + ); + +u1Byte +MapTxQueueToOutPipe( + IN PADAPTER pAdapter, + IN u1Byte SpecifiedQueueID +); + + +// +// SDIO Rx Transfer +// +PSDIO_IN_CONTEXT +HalSdioGetInContext( + IN PADAPTER pAdapter + ); + +VOID +HalSdioReturnInContext( + IN PADAPTER pAdapter, + IN PSDIO_IN_CONTEXT pContext + ); + + +// +// SDIO Tx Transfer +// +PSDIO_OUT_CONTEXT +HalSdioGetTxContext( + IN PADAPTER pAdapter + ); + +VOID +HalSdioReturnTxContext( + IN PADAPTER pAdapter, + IN PSDIO_OUT_CONTEXT pContext + ); + +VOID +HalSdioTxComplete( + IN PADAPTER pAdapter, + IN PSDIO_OUT_CONTEXT pContext, + IN u4Byte status + ); + +VOID +HalSdioUdtDefSet( + IN PADAPTER pAdapter + ); + +#endif//__INC_HALUSB_H diff --git a/network/wlan/WDI/HAL/HalTxFeedback.h b/network/wlan/WDI/HAL/HalTxFeedback.h new file mode 100644 index 00000000..2f66eead --- /dev/null +++ b/network/wlan/WDI/HAL/HalTxFeedback.h @@ -0,0 +1,189 @@ + +#ifndef __INC_HAL_TX_FEEDBACK_H +#define __INC_HAL_TX_FEEDBACK_H + + +// The identifier/reason of the tx feedback +#define RT_TX_FEEDBACK_ID_AP_WMM_PS_PKT BIT0 +#define RT_TX_FEEDBACK_ID_AP_WMM_EOSP_ENDING BIT1 +#define RT_TX_FEEDBACK_ID_TDLS_TEARDOWN_PKT BIT2 +#define RT_TX_FEEDBACK_ID_TDLS_CHNLSWITCH BIT3 +#define RT_TX_FEEDBACK_ID_TDLS_NULL_PKT BIT4 +#define RT_TX_FEEDBACK_ID_TDLS_CS_DATA_PKT BIT5 +#define RT_TX_FEEDBACK_ID_TDLS_CHNLSWITCH_REQ BIT6 +#define RT_TX_FEEDBACK_ID_TDLS_PTR BIT7 +#define RT_TX_FEEDBACK_ID_SCAN_TX_NULL BIT8 // Send Null frame when starting scan process +#define RT_TX_FEEDBACK_ID_P2P_NEGO_TX BIT9 +#define RT_TX_FEEDBACK_ID_CCX_TSM BIT10 +#define RT_TX_FEEDBACK_ID_CCX_LINK_TEST BIT11 +#define RT_TX_FEEDBACK_ID_P2P_PD_RSP_TX BIT12 +#define RT_TX_FEEDBACK_ID_OFF_CHNL_TX BIT13 + + +#define RT_TX_FEEDBACK_ID_MULTICHANNEL_NULL_PKT BIT31 + +typedef struct _RT_TX_FEEDBACK_INFO RT_TX_FEEDBACK_INFO, *PRT_TX_FEEDBACK_INFO; + +typedef VOID +(*RtTxFeedbackCallbackHandler)( + PADAPTER pAdapter, + const RT_TX_FEEDBACK_INFO * const pTxFeedbackInfo +); + +typedef struct _RT_TX_FEEDBACK_INFO_TX_PROFILE +{ + RT_VALID_PAIR_BOOLEAN bPktOk; + RT_VALID_PAIR_BOOLEAN bRetryOver; + RT_VALID_PAIR_BOOLEAN bLifeTimeOver; + RT_VALID_PAIR_BOOLEAN bUnicast; + RT_VALID_PAIR_U4BYTE uQueueID; + RT_VALID_PAIR_U4BYTE uMacID; + RT_VALID_PAIR_U4BYTE uDataRetryCount; + RT_VALID_PAIR_U4BYTE uQueueTimeUs; + RT_VALID_PAIR_U4BYTE uFinalDataRateIndex; + +} RT_TX_FEEDBACK_INFO_TX_PROFILE, *PRT_TX_FEEDBACK_INFO_TX_PROFILE; + +#define GET_TX_PROFILE_PKT_OK(_pTxProfile) (((_pTxProfile)->bPktOk.bVaild) ? ((_pTxProfile)->bPktOk.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_RETRY_OVER(_pTxProfile) (((_pTxProfile)->bRetryOver.bVaild) ? ((_pTxProfile)->bRetryOver.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_LEFE_TIME_OVER(_pTxProfile) (((_pTxProfile)->bLifeTimeOver.bVaild) ? ((_pTxProfile)->bLifeTimeOver.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_IS_UNICAST(_pTxProfile) (((_pTxProfile)->bUnicast.bVaild) ? ((_pTxProfile)->bUnicast.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_QUEUE_ID(_pTxProfile) (((_pTxProfile)->uQueueID.bVaild) ? ((_pTxProfile)->uQueueID.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_MAC_ID(_pTxProfile) (((_pTxProfile)->uMacID.bVaild) ? ((_pTxProfile)->uMacID.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_DATA_RETRY_COUNT(_pTxProfile) (((_pTxProfile)->uDataRetryCount.bVaild) ? ((_pTxProfile)->uDataRetryCount.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_QUEUE_TIME_US(_pTxProfile) (((_pTxProfile)->uQueueTimeUs.bVaild) ? ((_pTxProfile)->uQueueTimeUs.Data) : TxFeedbackAssertForInvalidData()) +#define GET_TX_PROFILE_FINAL_DATA_RATE_INDEX(_pTxProfile) (((_pTxProfile)->uFinalDataRateIndex.bVaild) ? ((_pTxProfile)->uFinalDataRateIndex.Data) : TxFeedbackAssertForInvalidData()) + + +typedef struct _RT_TX_FEEDBACK_INFO +{ + // User Configuration Part ------------------------------------------------------ + RT_LIST_ENTRY List; // The linked list pointer. + u4Byte Identifier; // The ID to identify this tx feedback. + u4Byte Reason; // The reason for this packet. + PADAPTER pAdapter; // The adapter address. + RtTxFeedbackCallbackHandler Callback; // The callback function. + PVOID pContext; // The context address. + // -------------------------------------------------------------------------- + + // Packet Tx Profile ----------------------------------------------------------- + RT_TX_FEEDBACK_INFO_TX_PROFILE TxProfile; + // -------------------------------------------------------------------------- + +}RT_TX_FEEDBACK_INFO, *PRT_TX_FEEDBACK_INFO; + + +#define HAL_MAX_TX_FEEDBACK_INFO_NUM 16 // The same number with TID. +#define HAL_MAX_TX_FEEDBACK_QUEUE_NUM 7 // The number of the edca (TID) queue for the tx feedback information + + +typedef struct _TX_FEEDBACK_CONTEXT{ + + BOOLEAN bSupportTxFeedBack; + RT_TX_FEEDBACK_INFO TxFeedbackArray[HAL_MAX_TX_FEEDBACK_INFO_NUM]; + + // Use RT_TX_SPINLOCK to protect the queue context ------------------------------------------------------------ + RT_LIST_ENTRY TxFeedbackIdleQueue; + RT_LIST_ENTRY TxFeedbackEDCAQueue[HAL_MAX_TX_FEEDBACK_QUEUE_NUM]; // The number of TID. + // -------------------------------------------------------------------------------------------------------- + +} TX_FEEDBACK_CONTEXT, *PTX_FEEDBACK_CONTEXT; + +#define TX_FEEDBACK_SIZE_OF_CONTEXT sizeof(TX_FEEDBACK_CONTEXT) + + + +typedef struct _TX_FEEDBACK_TCB_ZONE{ + + PRT_TX_FEEDBACK_INFO pTxFeedbackInfo; + +} TX_FEEDBACK_TCB_ZONE, *PTX_FEEDBACK_TCB_ZONE; + +#define TX_FEEDBACK_SIZE_OF_TCB_ZONE sizeof(TX_FEEDBACK_TCB_ZONE) + + + + + +VOID +TxFeedbackInitialize( + PADAPTER pAdapter +); + +BOOLEAN +TxFeedbackExistActiveTxFeedbackInfo( + PADAPTER pAdapter +); + +PRT_TX_FEEDBACK_INFO +TxFeedbackGetMatchedTxFeedbackInfoFromSpecificQueue( + PADAPTER pAdapter, + u1Byte QueueID, + u4Byte TxFeedbackID +); + +static VOID +TxFeedbackReturnTxFeedbackInfo( + PADAPTER pAdapter, + PRT_TX_FEEDBACK_INFO pTxFeedbackInfo +); + +VOID +TxFeedbackSetActiveTxFeedbackInfo( + PADAPTER pAdapter, + u1Byte QueueID, + PRT_TCB pTcb +); + +VOID +TxFeedbackSetTxFeedbackInfoID( + PADAPTER pAdapter, + PRT_TCB pTcb +); + +VOID +TxFeedbackExecuteCallbackAndReturnTxFeedbackInfo( + PADAPTER pAdapter, + PRT_TX_FEEDBACK_INFO pTxFeedbackInfo +); + + +BOOLEAN +TxFeedbackInstallTxFeedbackInfoForTcb( + PADAPTER pAdapter, + PRT_TCB pTcb +); + +VOID +TxFeedbackDeInstallTxFeedbackInfoForTcb( + PADAPTER pAdapter, + PRT_TCB pTcb +); + +VOID +TxFeedbackFillTxFeedbackInfoUserConfiguration( + PRT_TCB pTcb, + u4Byte Reason, + PADAPTER pAdapter, + RtTxFeedbackCallbackHandler Callback, + PVOID pContext +); + +BOOLEAN +TxFeedbackIsTxFeedbackInfoInstalled( + PRT_TCB pTcb +); + +BOOLEAN +TxFeedbackCheckCurrentFunctionality( + PADAPTER pAdapter +); + +BOOLEAN +TxFeedbackAssertForInvalidData( +); + + + + +#endif diff --git a/network/wlan/WDI/HAL/HalWoWLAN.h b/network/wlan/WDI/HAL/HalWoWLAN.h new file mode 100644 index 00000000..2d40cb10 --- /dev/null +++ b/network/wlan/WDI/HAL/HalWoWLAN.h @@ -0,0 +1,46 @@ +#ifndef __INC_HAL_WOWLAN_H +#define __INC_HAL_WOWLAN_H + +VOID +HALWOWL_DisableMACRxDMA( + IN PADAPTER Adapter + ); + +VOID +HALWOWL_EnableMACRxDMA( + IN PADAPTER Adapter + ); + + +VOID +HALWOWL_EnablePowerSave( + IN PADAPTER Adapter + ); + +VOID +HALWOWL_DisablePowerSave( + IN PADAPTER Adapter + ); + +VOID +HALWOWL_HWPowerSettings( + IN PADAPTER Adapter + ); + +RT_STATUS +HALWOWL_FuncEnable( + IN PADAPTER Adapter + ); + +VOID +HALWOWL_FuncDisable( + IN PADAPTER Adapter, + IN BOOLEAN bSimpleInit + ); + +VOID +HALWOWL_ResetVar( + IN PADAPTER Adapter + ); + +#endif diff --git a/network/wlan/WDI/HAL/halCmdPkt.h b/network/wlan/WDI/HAL/halCmdPkt.h new file mode 100644 index 00000000..0af6c441 --- /dev/null +++ b/network/wlan/WDI/HAL/halCmdPkt.h @@ -0,0 +1,375 @@ +/***************************************************************************** + * Copyright(c) 2006, RealTEK Technology Inc. All Right Reserved. + * + * Module: hal90cmdpkt.h (RTL8190 TX/RX command packet handler Header H File) + * + * + * Note: We define different command packets' structure and defintion. + * Please refer to doc ws-06-0063-rtl8190-command-packet-specification. + * 1. The defintiion and structure will be the same in DRV and FW. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: SZ : Size + * .....For example. + * + * History: + * Data Who Remark + * 01/15/2007 MHC Create initial version. Define comadn packet + * structure and element definition. + * 01/16/2007 MHC According to document, we add defintion in dedicated + * field and corresponding structure. + * 07/05/2007 MHC Change tx feedback packet structure to fit format + * from firmware. + * 10/09/2007 MHC Accept all USB/PCI structure and enum. Nerge the + * same structure or constant definition. + * + *****************************************************************************/ + /* Check to see if the file has been included already. */ +#ifndef __HAL90_CMD_PKT_H__ +#define __HAL90_CMD_PKT_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +/* 2007/01/15 MH Define some constant for comand packet handler module. */ +#define KB 1024 +#define MByte KB*KB + + +/* Define frequently used type definition. */ +/* INT8 is defined in WINDDK/3790/inc/wxp/basetsd.h:30. */ +//typedef char INT8; +typedef short INT16; +//typedef long INT32; + +#if (RT_PLATFORM != PLATFORM_LINUX) && (RT_PLATFORM != PLATFORM_MACOSX) +typedef unsigned char UINT8; +typedef unsigned short UINT16; +//typedef unsigned long UINT32; +#endif + +typedef void (*VOIDFUNCPTR) (void); +typedef int (*INTFUNCPTR) (void); + +/* Different command packet have dedicated message length and definition. */ +#define CMPK_RX_TX_FB_SIZE sizeof(CMPK_TXFB_T) //20 +#define CMPK_RX_BEACON_STATE_SIZE sizeof(CMPK_BCN_STA_T) //4 +#define CMPK_TX_SET_CONFIG_SIZE sizeof(CMPK_SET_CFG_T) //16 +#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(CMPK_SET_CFG_T) //16 +#define CMPK_RX_TX_STS_SIZE sizeof(CMPK_TX_STATUS_T)// +#define CMPK_RX_DBG_MSG_SIZE sizeof(CMPK_RX_DBGINFO_T)// +#define CMPK_TX_RAHIS_SIZE sizeof(CMPK_TX_RAHIS_T)// + + +/* Feedback info field. */ +/* 1. Fail Reason encoding. */ +#define CMPK_RETRY_TIME_OUT 0x00 /* */ +#define CMPK_RETRY_MSDU_TIME_OUT 0x01 /* */ +#define CMPK_RETRY_DELAY_TIME_OUT 0x02 /* */ + +/* 2. TID : VO/VI/BE/BK, ... */ + +/* 3. Rate Mapping*/ +#define CMPK_CCK_1M 0x00 /* */ +#define CMPK_CCK_2M 0x01 /* */ +#define CMPK_CCK_5P5M 0x02 /* */ +#define CMPK_CCK_11M 0x03 /* */ +#define CMPK_OFDM_6M 0x04 /* */ +#define CMPK_OFDM_9M 0x05 /* */ +#define CMPK_OFDM_12M 0x06 /* */ +#define CMPK_OFDM_18M 0x07 /* */ +#define CMPK_OFDM_24M 0x08 /* */ +#define CMPK_OFDM_36M 0x09 /* */ +#define CMPK_OFDM_48M 0x0A /* */ +#define CMPK_OFDM_54M 0x0B /* */ +#define CMPK_HT_MCS0 0x80 /* */ +#define CMPK_HT_MCS1 0x81 /* */ +#define CMPK_HT_MCS2 0x82 /* */ +#define CMPK_HT_MCS3 0x83 /* */ +#define CMPK_HT_MCS4 0x84 /* */ +#define CMPK_HT_MCS5 0x85 /* */ +#define CMPK_HT_MCS6 0x86 /* */ +#define CMPK_HT_MCS7 0x87 /* */ +#define CMPK_HT_MCS8 0x88 /* */ +#define CMPK_HT_MCS9 0x89 /* */ +#define CMPK_HT_MCS10 0x8A /* */ +#define CMPK_HT_MCS11 0x8B /* */ +#define CMPK_HT_MCS12 0x8C /* */ +#define CMPK_HT_MCS13 0x8D /* */ +#define CMPK_HT_MCS14 0x8E /* */ +#define CMPK_HT_MCS15 0x8F /* */ +#define CMPK_HT_MCS32 0xA0 /* */ + +/* Configuration info field. */ +/* 1. Type definition of Query/Set Configuration Element. */ +#define CMPK_CFG_MAC_REG 0x00 +#define CMPK_CFG_BB_REG 0x01 +#define CMPK_CFG_FW_ARG 0x02 +#define CMPK_CFG_TP_REV 0x03 /* Type reserve bit. */ + +/* 2. Size definition of Query/Set Configuration Element. */ +#define CMPK_CFG_SZ_REV 0x00 /* Size reserve bit. */ +#define CMPK_CFG_BYTE 0x01 +#define CMPK_CFG_WORD 0x02 +#define CMPK_CFG_DWORD 0x03 + +/* Define RX command queue ID. */ +#define CMPK_RX_QUEUE_ID 1 + +/* 2007/10/09 MH For USB consatnt. */ +#define ISR_TxBcnOk BIT27 // Transmit Beacon OK +#define ISR_TxBcnErr BIT26 // Transmit Beacon Error +#define ISR_BcnTimerIntr BIT13 // Beacon Timer Interrupt +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ +/* Define different command packet structure. */ +/* 1. RX side: TX feedback packet. */ + +#ifdef REMOVE_PACK +#pragma pack(1) +#endif + +typedef struct tag_Cmd_Pkt_Tx_Feedback +{ + // DWORD 0 + UINT8 Element_ID; /* Command packet type. */ + UINT8 Length; /* Command packet length. */ + /* 2007/07/05 MH Change tx feedback info field. */ + /*------TX Feedback Info Field */ + UINT8 TID:4; /* */ + UINT8 Fail_Reason:3; /* */ + UINT8 TOK:1; /* Transmit ok. */ + UINT8 Reserve1:4; /* */ + UINT8 Pkt_Type:2; /* */ + UINT8 Bandwidth:1; /* */ + UINT8 Qos_Pkt:1; /* */ + + // DWORD 1 + UINT8 Reserve2; /* */ + /*------TX Feedback Info Field */ + UINT8 Retry_Cnt; /* */ + UINT16 Pkt_ID; /* */ + + // DWORD 3 + UINT16 Seq_Num; /* */ + UINT8 S_Rate; /* Start rate. */ + UINT8 F_Rate; /* Final rate. */ + + // DWORD 4 + UINT8 S_RTS_Rate; /* */ + UINT8 F_RTS_Rate; /* */ + UINT16 pkt_length; /* */ + + // DWORD 5 + UINT16 Reserve3; /* */ + UINT16 Duration; /* */ +}CMPK_TXFB_T; + +// For USB +/* 2. RX side: Interrupt status packet. It includes Beacon State, + Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */ +typedef struct tag_Cmd_Pkt_Interrupt_Status +{ + UINT8 Element_ID; /* Command packet type. */ + UINT8 Length; /* Command packet length. */ + UINT16 Reserve; + UINT32 InterruptStatus; /* Interrupt Status. */ +}CMPK_INTR_STA_T; + +// For PCI +/* 2. RX side: Beacon state packet. */ +typedef struct tag_Cmd_Pkt_Beacon_State +{ + UINT8 Element_ID; /* Command packet type. */ + UINT8 Length; /* Command packet length. */ + UINT16 BOK:1; /* Beacon info. */ + UINT16 Reserve:15; /* Beacon info. */ +}CMPK_BCN_STA_T; + + +/* 3. TX side: Set configuration packet. */ +typedef struct tag_Cmd_Pkt_Set_Configuration +{ + UINT8 Element_ID; /* Command packet type. */ + UINT8 Length; /* Command packet length. */ + UINT16 Reserve1; /* */ + + UINT32 Cfg_Action:1; /* Configuration info. */ + UINT32 Cfg_Type:2; /* Configuration info. */ + UINT32 Cfg_Size:2; /* Configuration info. */ + UINT32 Cfg_Reserve2:15; /* Configuration info. */ + UINT32 Cfg_Page:4; /* Configuration info. */ + UINT32 Cfg_Offset:8; /* Configuration info. */ + + UINT32 Value; /* */ + UINT32 Mask; /* */ +}CMPK_SET_CFG_T; + +#ifdef REMOVE_PACK +#pragma pack() +#endif + + + +/* 4. Both side : TX/RX query configuraton packet. The query structure is the + same as set configuration. */ +#define CMPK_QUERY_CFG_T CMPK_SET_CFG_T + + +/* 5. Multi packet feedback status. */ +typedef struct tag_Tx_Stats_Feedback // PJ quick rxcmd 09042007 +{ + // For endian transfer --> Driver will not the same as firmware structure. + // DW 0 + UINT16 Reserve1; + UINT8 Length; // Command packet length + UINT8 Element_ID; // Command packet type + + // DW 1 + UINT16 TxFail; // Tx Fail count + UINT16 TxOK; // Tx ok count + + // DW 2 + UINT16 TxMCOK; // tx multicast + UINT16 TxRetry; // Tx Retry count + + // DW 3 + UINT16 TxUCOK; // tx unicast + UINT16 TxBCOK; // tx broadcast + + // DW 4 + UINT16 TxBCFail; // + UINT16 TxMCFail; // + + // DW 5 + UINT16 Reserve2; // + UINT16 TxUCFail; // + + // DW 6-8 + UINT32 TxMCLength; + UINT32 TxBCLength; + UINT32 TxUCLength; + + // DW 9 + UINT16 Reserve3_23; + UINT8 Reserve3_1; + UINT8 Rate; +}CMPK_TX_STATUS_T; + + +/* 6. Debug feedback message. */ +/* 2007/10/23 MH Define RX debug message */ +typedef struct tag_Rx_Debug_Message_Feedback +{ + // For endian transfer --> for driver + // DW 0 + UINT16 Reserve1; + UINT8 Length; // Command packet length + UINT8 Element_ID; // Command packet type + + // DW 1-?? + // Variable debug message. + +}CMPK_RX_DBGINFO_T; + + +/* 2008/03/20 MH Define transmit rate history. For big endian format. */ +typedef struct tag_Tx_Rate_History +{ + // For endian transfer --> for driver + // DW 0 + UINT8 Element_ID; // Command packet type + UINT8 Length; // Command packet length + UINT16 Reserved1; + + // DW 1-2 CCK rate counter + UINT16 CCK[4]; + + // DW 3-6 + UINT16 OFDM[8]; + + // DW 7-14 + //UINT16 MCS_BW0_SG0[16]; + + // DW 15-22 + //UINT16 MCS_BW1_SG0[16]; + + // DW 23-30 + //UINT16 MCS_BW0_SG1[16]; + + // DW 31-38 + //UINT16 MCS_BW1_SG1[16]; + + // DW 7-14 BW=0 SG=0 + // DW 15-22 BW=1 SG=0 + // DW 23-30 BW=0 SG=1 + // DW 31-38 BW=1 SG=1 + UINT16 HT_MCS[4][16]; + +}CMPK_TX_RAHIS_T; + +/* Define element ID of command packet. */ +typedef enum tag_Command_Packet_Directories +{ + RX_TX_FEEDBACK = 0, + + RX_BEACON_STATE = 1, + TX_SET_CONFIG = 2, + BOTH_QUERY_CONFIG = 3, + RX_TX_STATUS = 4, + RX_DBGINFO_FEEDBACK = 5, + RX_TX_PER_PKT_FEEDBACK = 6, + RX_TX_RATE_HISTORY = 7, + RX_TX_TSSI_MEAN_BACK = 8, + RX_CMD_ELE_MAX +}CMPK_ELEMENT_E; + + +/* Define packet type. */ +typedef enum tag_Packet_Type +{ + TYPE_PACKET_BROADCAST = 0, + TYPE_PACKET_MULTICAST, + TYPE_PACKET_UNICAST, + TYPE_PACKET_TYPE_MAX +}CMPK_PKT_TYPE_E; +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ + +extern RT_STATUS +SendTxCommandPacket( + IN PADAPTER pAdapter, + IN PVOID pData, + IN u4Byte DataLen + ); + +extern RT_STATUS CMPK_Message_Handle_Tx( + IN PADAPTER pAdapter, + IN pu1Byte CodeVirtualAddrress, + IN u4Byte PacketType, + IN u4Byte BufferLen); +extern UINT32 CMPK_Message_Handle_Rx(PADAPTER pAdapter, PRT_RFD pRfd); + + +/* Temporarily extern for debug utility. */ +extern void cmpk_DisplayTxStatistic(PADAPTER Adapter); +/*--------------------------Exported Function prototype---------------------*/ + + +#endif /* __HAL90_CMD_PKT_H__ */ + + +/* End of hal90cmdpkt.h */ diff --git a/network/wlan/WDI/HAL/halDbgCmd.h b/network/wlan/WDI/HAL/halDbgCmd.h new file mode 100644 index 00000000..4d1aca04 --- /dev/null +++ b/network/wlan/WDI/HAL/halDbgCmd.h @@ -0,0 +1,331 @@ +/***************************************************************************** + * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved. + * + * Module: hal90DbgCmd.h (RTL8190 Header H File) + * + * + * Note: The header file records the command format between UI and + * driver. And necessary constant for debug command handler. + * + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * 05/30/2007 MHC Create initial version. + * 05/30/2007 MHC 1. Support debug command from UI. We define command + * format between driver and UI. + * 2. We copy debug command definition from firmware. + * 06/07/2007 MHC We do not use MIPS GNU header file to support sprintf. + * 06/08/2007 MHC Add RX command format structure. + * 06/11/2007 MHC 1. Copy debug command strcuture from MP UI. Programmer + * must main the table when they add command. + * 06/15/2007 MHC 1. Define current debug command index and do test. We do + * not need to send the header files to UI and UI can + * support the new command immediately. + * 2. Add directory definition for driver. + * 07/13/2007 MHC 1. Define debug print macro which is controlled by + * different debug flag. + * 2. Define different debug flag. + * 07/31/2007 MHC 1. Add debug command to count ISR time. + * 08/15/2007 MHC Add debug command index for other commands. + * 08/16/2007 MHC Extern global variable and API for debug command betwen + * UI and firmware. + * +******************************************************************************/ + /* Check to see if the file has been included already. */ +#ifndef __HAL90_DEBUG_COMMAND_H__ +#define __HAL90_DEBUG_COMMAND_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +#define DBG_MODE_EVENT 0x00000001 +#define DCMD_MAX_DIRECTORY 1000 +#define DCMD_STRING_LENGTHH 32 +#define DCMD_MAX_NUM 1000 + + +/* 2007/03/13 MH Support byte/word/long R/W check. */ +#define DCMD_BYTE 1 +#define DCMD_WORD 2 +#define DCMD_LONG 4 + + + +/* 2007/05/30 MH Define constatn for debug command from UI. */ +#define DCMD_DRIVER_CMD 0 +#define DCMD_FIRMWARE_CMD 1 + +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ +typedef struct tag_Debug_CoMmanD +{ + char *name; /* Command string */ + char *desc; /* Description */ + char *usage; /* Usage of the command */ + int directory; /* Directory */ + int usage_counter; /* Usage counter for optimization */ + int (*cmd_func)(IN PADAPTER pAdapter, + IN INT32 Cmd_Idx, + IN INT32 Argc, + IN INT8 *pArgs[]); + /* Command function pointer */ +}DCMD_T; + +/* 2007/06/15 MH Define driver debug command's directory. */ +typedef enum tag_CMD_Directories +{ + /* General command. */ + COMMON = 1, + DYNAMIC_SCHEME = 2, + //Add for 92S shared commands + CMD_92S = 3, + TX_PROCESS_CMD, + RX_PROCESS_CMD, + SECURITY_CMD, + /* Private command. You can add according your requirement. */ + PRIVATE = 11, + MY_LOVELY_CMD, + MY_DISLIKE_CMD, + + /* Directory to display all command index. */ + CMD_INDEX_DISPLAY = 100, + + /* Last directory definition. */ + OTHERS +}DCMD_DIRECTORY_E; + +typedef enum tag_DCMD_Status_Code +{ + CMD_EXECUTE_OK = 0, + CMD_EXECUTE_FAIL, + CMD_PASSWORD_OK, + CMD_PASSWORD_FAIL, + CMD_ARGUMENT_FAIL, + CMD_NO_MATCH_COMMAND, + CMD_NOT_COMMAND, + CMD_NEW_COMMAND, + CMD_PREVIOUS_COMMAND +}DCMD_STATUS_E; + +/* 2006/11/28 MH We only support below three type for scanf. */ +typedef enum tag_DCMD_Scanf_Type_Definition +{ + DCMD_DECIMAL = 1, + DCMD_HEX, + DCMD_CHAR, + DCMD_SCAN_LIMIT = 10 +}DCMD_STP_DEF_E; + +/* 2007/05/30 MH Define TX command format from UI to driver. */ +#define MAX_ARGC 20 // Only used here. +#define MAX_ARGV 16 // Only used here. +typedef struct tag_Cmd_Format_UI_To_Driver +{ + INT32 Op; /* Command packet type. */ + INT32 Length; /* Command packet length. */ + INT32 Cmd_Idx; /* Command index. */ + INT32 Argc; /* Argument counter. */ + INT8 Argv[MAX_ARGC][MAX_ARGV]; /* Argument value array. */ +}DCMD_TMSG_T, *PDCMD_TMSG_T; + +/* 2007/06/08 MH Define RX command format from driver to UI. */ +#define MAX_RETURN_INFO_SIZE 240 // Only used here. +#define RX_HEADER_SIZE 16 //OP+status+segment+length +typedef struct tag_Cmd_Format_Driver_To_UI +{ + INT32 Op; /* Command packet type. */ + INT32 Status; /* Command status0/1/2. */ + INT32 Segment; /* Command segment num. */ + INT32 Length; /* Return info size. */ + INT8 ReturnInfo[MAX_RETURN_INFO_SIZE]; /* Argument value array. */ +}DCMD_RMSG_T; + +/* The debug command table is used for UI to do parser. */ +typedef enum _DBG_DRIVER_CMD_INDEX{ + DBG_CMD_HELP = 0 , + DBG_CMD_REG_READ = 1 , + DBG_CMD_REG_WRITE = 2 , + DBG_CMD_ADAPTER_READ = 3 , + DBG_CMD_ADAPTER_WRITE = 4 , + DBG_CMD_RF_READ = 5 , + DBG_CMD_UI_DEBUG = 6 , + DBG_CMD_FLAG_CTRL = 7 , + DBG_CMD_RF_WRITE = 8 , + DBG_CMD_REG_R_2BYTE = 9 , + DBG_CMD_REG_W_2BYTE = 10, + DBG_CMD_REG_R_1BYTE = 11, + DBG_CMD_REG_W_1BYTE = 12, + DBG_CMD_DYNAMIC_CTRL = 13, + DBG_CMD_BANDWIDTH_SWITCH = 14, + DBG_CMD_TX_RATE_HISTORY = 15, + DBG_CMD_TX_FW_CTRL = 16, + DBG_CMD_FORCE_TX_FW_INFO = 17, + DBG_CMD_FW_DYNAMIC_CTRL = 18 , + DBG_CMD_RX_PATH_SELECTION = 19, + DBG_CMD_92SE_FPGA_TEST = 20, + DBG_CMD_INFO_DUMP = 21, + DBG_CMD_92S_FWBUF_DUMP = 22, + DBG_CMD_SEC_CTRL = 23, + DBG_CMD_REG_DUMP = 24, + DBG_CMD_92S_RESET = 25, + DBG_CMD_EEPROM_READ = 26, + DBG_CMD_EFUSE_READ = 27, + DBG_CMD_SHADOW_OPERATE = 28, + DBG_CMD_DBG_CONTROL = 29, + DBG_CMD_USB_PHYR = 30, + DBG_CMD_USB_PHYW = 31, + DBG_CMD_SHORTCUT = 32, + DBG_CMD_INDICATE_SETTING = 33, + DBG_CMD_MAX_IDX +}DBG_DRIVER_CMD_INDEX; + +typedef enum _DBG_CONTROL_TYPE +{ + DBG_CTRL_PWRSAVE_DISABLE = 0, + DBG_CTRL_INBANDNOISE = 1, + DBG_CTRL_LINK_QUALITY = 2, + DBG_CTRL_SIGNAL_STRENGTH = 3, + DBG_CTRL_PSD_MONITOR = 4, + DBG_CTRL_BT_PROFILE = 5, + DBG_CTRL_BT_COEX_ENABLE = 6, + DBG_CTRL_TEST = 7, + DBG_CTRL_BT_HCI_INFO = 8, + DBG_CTRL_BT_HS_INFO = 9, + DBG_CTRL_RESET_BT_DBG = 10, + DBG_CTRL_BT_COEX_INFO = 11, + DBG_CTRL_BT_LOGO_TEST = 12, + DBG_CTRL_SEND_H2C = 13, + DBG_CTRL_SET_EDCA = 14, + DBG_CTRL_SET_COEX_MODE = 15, + DBG_CTRL_DEC_BT_PWR = 16, + DBG_CTRL_CTRL_AGGREGATION = 17, + DBG_CTRL_AGGREGATE_BUF_SIZE = 18, + DBG_CTRL_RX_RATE_INFO = 19, + DBG_CTRL_SET_DIG = 20, + DBG_CTRL_BT_AFH_MAP = 21, + DBG_CTRL_BT_IGNORE_WLAN_ACT = 22, + DBG_CTRL_BB_INFO = 23, + DBG_CTRL_SET_DBG_MON_COMP = 24, + DBG_CTRL_SHOW_WIFI_BASIC = 25, + DBG_CTRL_SHOW_TX_INFO = 26, + DBG_CTRL_SHOW_NDIS_INFO = 27, + DBG_CTRL_SHOW_RX_INFO = 28, + DBG_CTRL_SHOW_BASIC_PROFILE = 29, + DBG_CTRL_SHOW_WOL_INFO = 30, + DBG_CTRL_SHOW_PWR_SVG_INFO = 31, + DBG_CTRL_SHOW_antdet_INFO = 32, + DBG_CTRL_SHOW_SKU_INFO = 33, + + DBG_CTRL_SET_RX_REORDER = 34, //2015/01/21 gary add + DBG_CTRL_SET_TX_HT_SUPPORT_CAP = 35, //2015/01/22 gary add + DBG_CTRL_SET_TX_VHT_SUPPORT_CAP = 36, + DBG_CTRL_SET_RX_HT_SUPPORT_CAP = 37, + DBG_CTRL_SET_RX_VHT_SUPPORT_CAP = 38, + DBG_CTRL_SHOW_TX_USB_AGG_INFO = 39, + DBG_CTRL_SHOW_RX_USB_AGG_INFO = 40, + DBG_CTRL_SET_TX_USB_AGG = 41, + DBG_CTRL_SET_RX_USB_AGG = 42, + + DBG_CTRL_BB_RXHANG_INFO = 43, + DBG_CTRL_SET_PWR_TABLE = 44, + DBG_CTRL_SHOW_CHANNELPLAN_INFO = 45, + DBG_CTRL_DUMP_PWR_TABLE = 46, + DBG_CTRL_SHOW_RSSI_INFO = 47, + /** in order to work with Sigma Console ** + ************use value 29,30,31***********/ + DBG_CTRL_NAN_OPERATION = 48,//29, + DBG_CTRL_NAN_STATE = 49,//30, + DBG_CTRL_NAN_VARIABLE = 50,//31, + /***********************************/ + + DBG_CTRL_MAX +}DBG_CONTROL_TYPE; + +#define DCMD_EFUSE_MAP_MAX_LEN 1024 +#define DCMD_EFUSE_MAX_SECTION_NUM 128 + + + +// 2008/03/26 MH We define a simple tx command format for 92 series. No dbg support. +typedef struct tag_Tx_Config_Cmd_Format +{ + UINT32 Op; /* Command packet type. */ + UINT32 Length; /* Command packet length. */ + UINT32 Value; +}DCMD_TXCMD_T, *PDCMD_TXCMD_T; + +/* The simple tx command OP code. */ +typedef enum _tag_TxCmd_Config_Index{ + TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, + TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, + TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, + TXCMD_SET_TX_DURATION = 0xFF900003, + TXCMD_SET_RX_RSSI = 0xFF900004, + TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, + TXCMD_XXXX_CTRL, +}DCMD_TXCMD_OP; +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +//extern DCMD_T dcmd_Commands[]; +#if 0 // Move to debug.h +extern UINT32 DBGP_Type[DBGP_TYPE_MAX]; +extern DBGP_HEAD_T DBGP_Head; +#endif +extern INT32 DCMD_OP_Type; + +// for test +//extern UINT8 nheader[100][24]; +//extern UINT8 llcheader[100][24]; + + +// Declare for 92S debug, delete later !!! +extern u4Byte usb_speed; +/*------------------------Export global variable----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ +#define dcmd_sprintf RtlStringCchVPrintfW + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +extern INT32 DCMD_Message_Handler_Tx(IN PADAPTER pAdapter, + IN ULONG length, + IN PVOID pBuffer); +extern INT32 DCMD_Message_Handler_Check( IN ULONG Length, + OUT PVOID pBuffer, + OUT ULONG *pLength); +extern INT32 DCMD_Message_Handler_Rx(IN INT32 DbgType, + IN ULONG Length, + OUT PVOID pBuffer, + OUT ULONG *pLength); +extern INT32 DCMD_Save_FW_Dbg_Info( IN ULONG Length, + IN PVOID pBuffer); + + +void +DbgCmdWorkItemCallBack( + IN PVOID pContext +); + + +#define DCMD_Printf(_pMsg) +#define DCMD_Scanf(_pInput, _Type, _pOutput) + + + +/*--------------------------Exported Function prototype---------------------*/ + + +#endif /* __HAL90_DEBUG_COMMAND_H__ */ + + +/* End of hal90DbgCmd.h */ diff --git a/network/wlan/WDI/HAL/phydm/FileEnc.exe b/network/wlan/WDI/HAL/phydm/FileEnc.exe Binary files differnew file mode 100644 index 00000000..ef3d43e1 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/FileEnc.exe diff --git a/network/wlan/WDI/HAL/phydm/development_note.txt b/network/wlan/WDI/HAL/phydm/development_note.txt new file mode 100644 index 00000000..f83d166b --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/development_note.txt @@ -0,0 +1,1667 @@ +-------------------------------------------------------------------------------- +<01/05/2015 23:10 Dino Reviewer: > +New Files: +Modified Files: + HAL/OUTSRC/HalPhyRf.c + HAL/OUTSRC/phydm.c + HAL/OUTSRC/phydm.h + HAL/OUTSRC/PhyDM_Adaptivity.c + HAL/OUTSRC/phydm_debug.c + HAL/OUTSRC/phydm_HWConfig.c + HAL/OUTSRC/phydm_PowerTracking.h + HAL/OUTSRC/phydm_types.h + +Change Notes: + 1.Merge MERGE_TEMP to RTWLAN_TRUNK + +Verification Before Checked-In: + 1. N62 buildall ok. +-------------------------------------------------------------------------------- +<01/05/2015 15:20 Dino Reviewer: Luke > +New Files: +Modified Files: + HAL/HalH2cIOCmd.h + HAL/OUTSRC/development_note2012.txt + HAL/OUTSRC/phydm.c + HAL/OUTSRC/phydm.h + HAL/OUTSRC/phydm_debug.c + HAL/OUTSRC/phydm_HWConfig.h + HAL/OUTSRC/phydm_interface.c + HAL/OUTSRC/phydm_interface.h + HAL/OUTSRC/phydm_PathDiv.c + HAL/OUTSRC/phydm_PowerTracking.c + HAL/OUTSRC/phydm_PowerTracking.h + HAL/OUTSRC/phydm_precomp.h + HAL/OUTSRC/phydm_RaInfo.c + HAL/OUTSRC/phydm_RaInfo.h + HAL/OUTSRC/phydm_types.h + HAL/rtl8814A/Hal8814AFirmware.h + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + +Change Notes: + 1.Merge MERGE_TEMP to RTWLAN_TRUNK + +Verification Before Checked-In: + 1. N62 buildall ok. +-------------------------------------------------------------------------------- +<12/31/2014 15:20 Dino Reviewer: Luke > +New Files: +Modified Files: + HAL/OUTSRC/phydm_AntDiv.c + HEADER/TypeDef.h + +Change Notes: + 1.Remove BuddyAdapter + +Verification Before Checked-In: + 1. N62 buildall ok. +-------------------------------------------------------------------------------- +<12/31/2014 14:40 Dino Reviewer: Luke > +New Files: +Modified Files: + HAL/OUTSRC/HalPhyRf.h + HAL/OUTSRC/phydm.c + HAL/OUTSRC/phydm.h + HAL/OUTSRC/phydm_AntDiv.c + HAL/OUTSRC/phydm_AntDiv.h + HAL/OUTSRC/phydm_debug.c + HAL/OUTSRC/phydm_HWConfig.c + HAL/OUTSRC/phydm_PathDiv.c + HAL/OUTSRC/phydm_PathDiv.h + HAL/OUTSRC/phydm_precomp.h + HAL/OUTSRC/phydm_types.h + HAL/OUTSRC/rtl8192c/phydm_RTL8192C.c + HAL/OUTSRC/rtl8192c/phydm_RTL8192C.h + HAL/OUTSRC/rtl8812a/phydm_RTL8812A.c + HEADER/TypeDef.h + +Change Notes: + 1.Merge MERGE_TEMP to RTWLAN_TRUNK + +Issue Tracking: + [PHYDM-3] + +Verification Before Checked-In: + 1. N62 buildall ok. +-------------------------------------------------------------------------------- +<2014/12/30 11:25 Stanley Reviewer: Luke > +Modified Files: + HAL/OUTSRC/phydm_CfoTracking.c + +Change Notes: + 1. Disable CFO tracking for all IC + +Verification Before Checked-In: + 1.N62 build all ok + +-------------------------------------------------------------------------------- +<2014/12/29 18:50 Luke.Lee Reviewer: Wilson > +Modified Files: + HAL/OUTSRC/phydm_debug.c + HAL/OUTSRC/phydm_DynamicTxPower.c + HAL/OUTSRC/phydm_DynamicTxPower.h + +Change Notes: + 1. Merged from MERGE_TEMP + +Verification Before Checked-In: + 1.N63 build all ok + +-------------------------------------------------------------------------------- +<2014/12/26 18:50 Luke.Lee Reviewer: Stanley > +Modified Files: + HAL/OUTSRC/phydm_debug.c + HAL/OUTSRC/phydm_debug.h + HAL/OUTSRC/phydm_DIG.c + HAL/OUTSRC/phydm_DIG.h + HAL/OUTSRC/phydm_DynamicBBPowerSaving.h + HAL/OUTSRC/phydm_pre_define.h + HAL/OUTSRC/phydm_reg.h + +Change Notes: + 1. Merged from MERGE_TEMP + +Verification Before Checked-In: + 1.N63 build all ok + +-------------------------------------------------------------------------------- +<2014/12/24 17:20 Luke.Lee Reviewer: Dino > +Modified Files: + HAL/HalCommon.c + HAL/OUTSRC/phydm.c + HAL/OUTSRC/phydm.h + HAL/OUTSRC/PhyDM_Adaptivity.c + HAL/OUTSRC/phydm_CfoTracking.c + HAL/OUTSRC/phydm_CfoTracking.h + HAL/OUTSRC/phydm_RegDefine11AC.h + HAL/OUTSRC/phydm_RegDefine11N.h + HAL/OUTSRC/phydm_types.h + HAL/rtl8192C/rtl8192ce/Hal8192CEGen.c + HAL/rtl8723B/rtl8723be/Hal8723BEGen.c + HAL/rtl8723B/rtl8723bs/Hal8723BSdioGen.c + HAL/rtl8723B/rtl8723bu/Hal8723BUsbGen.c + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + PLATFORM/NDIS6/N6C_Req.c + +Change Notes: + 1. Merged from MERGE_TEMP + +Verification Before Checked-In: + 1.N63 build all ok + +-------------------------------------------------------------------------------- +<2014/12/24 21:00 Luke.Lee Reviewer: Stanley > +Modified Files: + HAL/halDbgCmd.c + HAL/halDbgCmd.h + HAL/HalDM.c + HAL/OUTSRC/phydm.c + HAL/OUTSRC/phydm.h + HAL/OUTSRC/phydm_debug.c + HAL/OUTSRC/phydm_debug.h + HAL/OUTSRC/phydm_interface.h + HEADER/PrecompInc.h + +Change Notes: + 1. Merged from MERGE_TEMP + +Verification Before Checked-In: + 1.N62/N63 build all ok + 2.8812AU ping OK + 3. CLI echo cmd test OK +-------------------------------------------------------------------------------- +<2014/12/23 21:00 Luke.Lee Reviewer: Dino > +Modified Files: + HAL/OUTSRC/phydm_ACS.c + HAL/OUTSRC/phydm_ACS.h + +New Files: + HAL/OUTSRC/phydm_AntDect.c + HAL/OUTSRC/phydm_AntDect.h + HAL/OUTSRC/phydm_NoiseMonitor.c + HAL/OUTSRC/phydm_NoiseMonitor.h + HAL/OUTSRC/phydm_PowerTracking.c + HAL/OUTSRC/phydm_PowerTracking.h + HAL/OUTSRC/phydm_pre_define.h + HAL/OUTSRC/phydm_RXHP.c + HAL/OUTSRC/phydm_RXHP.h + +Change Notes: + 1. Merged from MERGE_TEMP + +Verification Before Checked-In: + 1.N62 build all ok + +-------------------------------------------------------------------------------- +<2014/12/23 20:20 Luke.Lee Reviewer: Stanley > +Modified Files: + HAL/OUTSRC/phydm_EdcaTurboCheck.c + HAL/OUTSRC/phydm_EdcaTurboCheck.h + +Deleted Files: + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_FW.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_FW.h + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_MAC.c + +Change Notes: + 1. Merged from MERGE_TEMP + +Verification Before Checked-In: + 1.N62 build all ok + +-------------------------------------------------------------------------------- +<2014/12/17 19:40 YuChen Reviewer: Stanley > +Modified Files: + HAL/OUTSRC/phydm.h + HAL/OUTSRC/PhyDM_Adaptivity.c + HAL/OUTSRC/PhyDM_Adaptivity.h + HEADER/RegCommon.h + HEADER/TypeDef.h + PLATFORM/NDIS5/N5C_Init.c + PLATFORM/NDIS5/Ndis5Common.h + PLATFORM/NDIS6/N6C_Init.c + PLATFORM/NDIS6/Ndis6Common.h + +Change Notes: + 1. update AdaptivityV8.3 add DCbackoff registry + +Verification Before Checked-In: + 1.N62/N63 build all ok + +-------------------------------------------------------------------------------- +<2014/12/16 19:50 Stanley Reviewer: YuChen > +Modified Files: + HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.h + HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.h + HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.h + +Change Notes: + 1. Update RTL8723B_MP_Parameter_D-cut_v16_20141216 + - Set 0x421=0xf. Do not report tx-report of MGNT or Hi queue packet + 2. Update WaxApple_V2.13.2.3 + +Verification Before Checked-In: + 1. N62 build all ok + +-------------------------------------------------------------------------------- +<2014/12/09 22:00 Luke.Lee Reviewer: Wilson > +Modified Files: + +Change Notes: + 1. Rename PHYDM files + 2. Clear compilation errors due to renaming + +Verification Before Checked-In: + 1. build Win8.1 x64 ok +-------------------------------------------------------------------------------- +<2014/12/09 20:30 Luke.Lee Reviewer: Wilson > +Modified Files: + +Change Notes: + 1. Remove unnessary files + +Verification Before Checked-In: + 1. build Win7X86 ok +-------------------------------------------------------------------------------- +<2014/12/09 12:40 James Reviewer: Luke > +Modified Files: + HAL/OUTSRC/rtl8723b/HalPhyRf_8723B.c + +Change Notes: + 1. modify the boundary of IQK result for 8723B F-cut + +Verification Before Checked-In: + 1. build ok +-------------------------------------------------------------------------------- +<2014/11/26 14:30 YuChen Reviewer: Luke > +Modified Files: + hal/OUTSRC/PhyDM_Adaptivity.c + hal/OUTSRC/PhyDM_Adaptivity.h + +Change Notes: + 1. Update Adaptivity V8.2 + 2. Set Forgetting factor = 0x0 for ac series IC + +Verification Before Checked-In: + 1. build ok +-------------------------------------------------------------------------------- +<2014/11/19 10:00 YuChen Reviewer: Luke > +Modified Files: + HAL/halDbgCmd.c + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_RegDefine11AC.h + HAL/OUTSRC/PhyDM_Adaptivity.c + HAL/OUTSRC/PhyDM_Adaptivity.h + +Change Notes: + 1. Update Adaptivity V8.1 + 2. Sync with Merge temp + +Verification Before Checked-In: + 1. build ok +-------------------------------------------------------------------------------- +<2014/11/17 11:00 YuChen> +Modified Files: + HAL/halDbgCmd.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/PhyDM_Adaptivity.c + HAL/OUTSRC/PhyDM_Adaptivity.h + +Change Notes: + 1. Refine IGI upperBound for 8723B B-cut + 2. Only use BB reg to Control EDCCA + +Verification Before Checked-In: + 1. N62 build all ok +-------------------------------------------------------------------------------- +<2014/11/11 14:00 Stanley Reviewer: Luke > +Modified Files: + HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.c + HAL/OUTSRC/rtl8723b/MPChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8723b/MPChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8723b/MPChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8723b/MPChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/RadioA.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_SDIO.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TXPWR_LMT.txt + +Change Notes: + 1. Update RTL8723B MP Parameter v14 + 2. Remove 0xe0 setting in MP Parameter for LED + +Verification Before Checked-In: + 1. N62 build all ok +-------------------------------------------------------------------------------- +<2014/10/29 17:00 YuChen> +Modified Files: + HAL/OUTSRC/PhyDM_Adaptivity.c + +Change Notes: + 1. Set EDCCA lambda forgetting factor = 0 + +Verification Before Checked-In: + 1. N62 build all ok + 2. TP ok +-------------------------------------------------------------------------------- +<2014/10/15 18:15 Stanley Reviewer: YuChen> +Modified Files: + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + +Change Notes: + 1. Modify DIG flow for adaptivity (sync from merge temp v31757) + 2. Remove dummy prototype + +Verification Before Checked-In: + 1. N62 build all ok +-------------------------------------------------------------------------------- +<2014/10/14 11:10 YuChen Reviewer: Luke> +Modified Files: + HAL/OUTSRC/PhyDM_Adaptivity.c + HAL/OUTSRC/PhyDM_Adaptivity.h + +Change Notes: + 1. sync SD7 adaptivity_BSOD function to prevent BSOD + 2. Bug Fix, disable enable adc_mask to prevent 8812 EDCCA hang + +Verification Before Checked-In: + 1. build all ok +-------------------------------------------------------------------------------- +<2014/10/13 15:15 Stanley Reviewer: Luke> +Modified Files: + HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.c + HAL/OUTSRC/rtl8723b/MPChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8723b/MPChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8723b/MPChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8723b/MPChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/RadioA.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_SDIO.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/TXPWR_LMT.txt + +Change Notes: + 1. [8723B]Update RTL8723B_MP_Parameter_D-cut_v13_20141013 + +Verification Before Checked-In: + 1. N62 build all ok +-------------------------------------------------------------------------------- +<2014/10/03 16:15 Jenyu> +Modified Files: + HAL/OUTSRC/rtl8723b/HalPhyRf_8723B.c + +Change Notes: + 1. IQK version:V2.8 20141002 + 2. modify IQK flow + 3. PA all off at IQK + 4. 8723B D-cut still run IQK + +Verification Before Checked-In: + 1. N62 build all ok +-------------------------------------------------------------------------------- +<2014/10/03 14:50 YuChen> +Modified Files: + OUTSRC/PhyDM_Adaptivity.c + OUTSRC/PhyDM_Adaptivity.h + OUTSRC/odm_DIG.c + +Change Notes: + 1. Update Adaptivity V7.2 + 2. Adaptivity : + 2.1 Remove unnecessary condition(don't concern Band4 condition for ac series IC(only NIC)) + 2.2 Remove NHM function and other dummy code + 3. DIG + 3.1 Add LPS write DIG condition + +Verification Before Checked-In: + 1. N62/N63 build all ok +-------------------------------------------------------------------------------- +<2014/10/03 11:15 YuChen> +Modified Files: + +HAL/OUTSRC/PhyDM_Adaptivity.c + +Change Notes: + 1.fix regulation judgement error + 2.fix band 4 problem + +Verification Before Checked-In: + 1. N62/N63 build all ok +-------------------------------------------------------------------------------- +<2014/09/18 20:40 James Reviewer: Luke > +Modified Files: + HAL/Jaguar/Hal8812Firmware.c + HAL/Jaguar/Hal8812Firmware.h + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_interface.c + HAL/OUTSRC/odm_interface.h + HAL/OUTSRC/rtl8812a/HalHWImg8812A_FW.c + HAL/OUTSRC/rtl8812a/HalHWImg8812A_FW.h + HAL/OUTSRC/rtl8812a/HalPhyRf_8812A.c + HAL/OUTSRC/rtl8812a/MPChip/FW/FW_NIC.BIN + HAL/OUTSRC/rtl8812a/MPChip/FW/FW_NIC_BT.BIN + HAL/OUTSRC/rtl8812a/MPChip/FW/FW_WoWLAN.BIN + +Change Notes: + 1. update IQK v2.1 + 2. update FW v36 + 3. open FW IQK + 4. fix LCK bug + +Verification Before Checked-In: + 1. N62/N63 build all ok +--------------------------------------------------------------------------- +<2014/08/12 10:20 YuChen Reviewer:Stanley > +Modified Files: + OUTSRC/PhyDM_Adaptivity.c + +Change Notes: + Fix SearchPwdBLowerBound() in MPdriver + +Verification Before Checked-In: + 1.make all ok +--------------------------------------------------------------------------- +<2014/08/06 18:00 YuChen Reviewer:Stanley > +Modified Files: + HAL/halDbgCmd.c + OUTSRC/odm_debug.c + OUTSRC/odm_debug.h + OUTSRC/PhyDM_Adaptivity.c + +Change Notes: + Add Adaptivity debug message + cmd 13 0 1 a + +Verification Before Checked-In: + 1.N62/N63 build all ok +--------------------------------------------------------------------------- +<2014/08/04 17:00 YuChen Reviewer:Luke.Lee > +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_ACS.c + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + HAL/OUTSRC/odm_precomp.h + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + +Add Files: + HAL/OUTSRC/PhyDM_Adaptivity.c + HAL/OUTSRC/PhyDM_Adaptivity.h + +Change Notes: + 1. Moving adaptivity function from odm_DIG.c to PhyDM_Adaptivity.c + +Verification Before Checked-In: + 1.N62/N63 build all ok + +--------------------------------------------------------------------------- +<2014/07/22 11:55 Stanley Reviewer:James > +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + +Change Notes: + 1. Ignore DIG mechanism if IGI has been changed by other mechanism + 2. bSTA flag need to be reset when STA mode + +Verification Before Checked-In: + 1.N62 build all ok + +-------------------------------------------------------------------------------- +<2014/07/21 17:30 YuChen Reviewer: Luke.Lee > +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + HEADER/RegCommon.h + HEADER/TypeDef.h + PLATFORM/NDIS5/N5C_Init.c + PLATFORM/NDIS5/Ndis5Common.h + PLATFORM/NDIS6/N6C_Init.c + PLATFORM/NDIS6/Ndis6Common.h + +Change Notes: + 1. update Adaptivity V7.1 + 2. total legal version + +Verification Before Checked-In: + 1.N62/N63 build all ok +-------------------------------------------------------------------------------- +<2014/07/11 16:20 YuChen Reviewer: Stanley > +Modified Files: + HAL/halDbgCmd.c + HAL/HalDM.c + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + HEADER/RegCommon.h + HEADER/TypeDef.h + PLATFORM/NDIS5/N5C_Init.c + PLATFORM/NDIS5/Ndis5Common.h + PLATFORM/NDIS6/N6C_Init.c + PLATFORM/NDIS6/Ndis6Common.h + + +Change Notes: + 1. update Adaptivity V7.0 + 2. add Registry NHM_enable for performance improve(default off) + 3. temporary turn off updatePowerTrainingStatus + +Verification Before Checked-In: + 1.N62/N63 build all ok + +-------------------------------------------------------------------------------- +<2014/07/08 10:05 YuChen Reviewer: Stanley > +Modified Files: + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_ACS.c + HAL/OUTSRC/odm_ACS.h + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + +Change Notes: + 1. update Adaptivity V6.2 + 2. Support Repeater mode(for AP) + 3. Fix some unexpected error + 4. increase lab test possibility + +Verification Before Checked-In: + 1.N62 & N63 build all ok +-------------------------------------------------------------------------------- +<2014/07/01 13:30 YuChen Reviewer: Stanley > +Modified Files: + OUTSRC/odm_DIG.c + +Change Notes: + 1. Adjust Adaptivity threshold from -69dBm to -72dBm incase of shortcontrol + signal fail problem. + +Verification Before Checked-In: + 1.N62/N63 buildall ok +-------------------------------------------------------------------------------- +<2014/06/27 14:40 YuChen Reviewer: Stanley > +Modified Files: + OUTSRC/odm.c + OUTSRC/odm.h + OUTSRC/odm_DIG.c + OUTSRC/odm_DIG.h + +Change Notes: +Update Adaptivity V6.1 + 1. Support Reapeater mode( for lab test only) + 2. Refine test condition, we can't reset EDCCA threshold + when interference is exist + +Verification Before Checked-In: + 1.N62/N63 buildall ok +-------------------------------------------------------------------------------- +<2014/06/20 19:40 James Reviewer: LukeLee > +Modified Files: + HAL/OUTSRC/rtl8812a/HalPhyRf_8812A.c + HAL/OUTSRC/rtl8821a/HalPhyRf_8821A.c + +Change Notes: + 1. IQK remove PMAC for MAC TX hang + +Verification Before Checked-In: + 1.N62 build all ok + +-------------------------------------------------------------------------------- +<2014/06/19 18:40 Stanley Reviewer: Dino > +Modified Files: + HAL/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c + +Change Notes: + 1. Add dynamic power training mechanism for 8188E + +Verification Before Checked-In: + 1.N62 build all ok + +-------------------------------------------------------------------------------- +<2014/06/19 13:20 YuChen Reviewer: LukeLee > +Modified Files: + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_DIG.c + +Change Notes: + 1. Refine Adaptivity to V6.0, fix can't link problem + +Verification Before Checked-In: + 1.make all ok +-------------------------------------------------------------------------------- +<2014/06/18 14:45 YuChen Reviewer:Luke > +Modified Files: + OUTSRC/odm.h + OUTSRC/odm_DIG.c + OUTSRC/odm_DIG.h + OUTSRC/odm_RegDefine11AC.h + OUTSRC/odm_RegDefine11N.h + +Change Notes: + 1. Update Adaptivity V6.0 fix SearchPwdBlowerBound() + +Verification Before Checked-In: + 1.make all ok +-------------------------------------------------------------------------------- +<2014/06/17 18:10 Dino Reviewer:Luke > +Modified Files: + HAL/OUTSRC/odm_AntDiv.c +Change Notes: + 1. Update the mapping table for 88E antenna diversity + +Verification Before Checked-In: + 1.N62 buildall ok +-------------------------------------------------------------------------------- +<2014/06/13 18:00 Stanley Reviewer: James> +Modified Files: +Change Notes: + HAL/halDbgCmd.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_ACS.c + HAL/OUTSRC/odm_ACS.h + 1. Sync. odm_ACS.c with linux driver + - Add compile flag for linux driver + - Check support ability + + HAL/OUTSRC/odm_DIG.c + 1. Sync. odm_DIG.c with linux driver + - Fix DIG upper bound before link + - Disable forbidden IGI mechanism before link + + HAL/OUTSRC/odm_AntDiv.c + HAL/OUTSRC/odm_interface.c + HAL/OUTSRC/odm_interface.h + HAL/OUTSRC/odm_PathDiv.c + HAL/OUTSRC/odm_RaInfo.c + HAL/OUTSRC/odm_RaInfo.h + 1. Sync. odm_interface.c + - Add ODM_FillH2CCmd interface for linux driver + +Verification Before Checked-In: + 1.N62 buildall ok + +-------------------------------------------------------------------------------- +<2014/06/12 16:45 YuChen> +Modified Files: + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DynamicTxPower.c + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/odm_PathDiv.c + HAL/OUTSRC/odm_precomp.h + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + +Change Notes: + [ODM Reorganization] + 1. Update Adaptivity to V5.3 sync with sd4 + 2. Remove 8723B and 8812A testchip hwimg file + +Verification Before Checked-In: + 1.N62/N63 buildall ok +-------------------------------------------------------------------------------- +<2014/06/10 18:16 YuChen> +Modified Files: + HAL/OUTSRC/rtl8188e/HalHWImg8188E_BB.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_RF.c + HAL/OUTSRC/rtl8188e/MPChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8188e/MPChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/RadioA.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/TXPWR_LMT.txt + +Change Notes: + [8188E] + 1. Update PHY REG V51 + Same content with V50, fix CSV logical error +Verification Before Checked-In: + 1.N62/N63 buildAll ok +-------------------------------------------------------------------------------- +<2014/06/06 10:35 YuChen> +Modified Files: + HAL/OUTSRC/rtl8821a/HalHWImg8821A_BB.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_MAC.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_RF.c + HAL/OUTSRC/rtl8821a/MPChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8821a/MPChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8821a/MPChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8821a/MPChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/RadioA.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8811AU_FEM.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8811AU_IPA.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8821A.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8821A_SAR_5mm.txt + HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8821A_SAR_8mm.txt + +Change Notes: + [8821A] + 1. Update PHY REG V41 + 0x1F = 0x00064, RC BW for 80M (for better TX mask) +Verification Before Checked-In: + 1.N62/N63 buildAll ok +-------------------------------------------------------------------------------- +<2014/06/04 21:10 Stanley> +Modified Files: +Change Notes: + HAL/OUTSRC/odm_AntDiv.c + HAL/OUTSRC/odm_AntDiv.h + HAL/OUTSRC/odm_interface.c + HAL/OUTSRC/odm_interface.h + + 1. Modify SW antenna diversity method of 8723B to avoid antenna switch when BT IQK + +Verification Before Checked-In: + 1.N62 buildall ok + +-------------------------------------------------------------------------------- +<2014/06/04 12:35 YuChen> +Modified Files: +Change Notes: + HAL/OUTSRC/odm_DIG.c + 1. Refine Adaptivity to V5.1 + +Verification Before Checked-In: + 1.N62/N63 buildall ok +-------------------------------------------------------------------------------- +<2014/05/27 21:30 Stanley> +Modified Files: +Change Notes: + HAL/OUTSRC/odm_RaInfo.c + 1. Update BT 3.0 HS mode Rssi in odm_RSSIMonitorCheckMP + +Verification Before Checked-In: + 1.N62/N63 buildall ok + +-------------------------------------------------------------------------------- +<2014/05/27 10:10 YuChen> +Modified Files: +Change Notes: + HAL/HalDM.c + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + HEADER/RegCommon.h + + 1. Refine check channel plan to enable Adaptivity + +Verification Before Checked-In: + 1.N62/N63 buildall ok +----------------------------------------------------------------------------------------------------- +<2014/05/26 19:20 Stanley> +New Files: +Modified Files: +Change Notes: + HAL/OUTSRC/odm_Beamforming.c + HAL/OUTSRC/odm_Beamforming.h + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_BB.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_BB.h + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_FW.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_FW.h + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_MAC.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_MAC.h + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_RF.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_TestChip_RF.h + HAL/OUTSRC/rtl8188e/MPChip/BB/AGC_TAB_1T.txt + HAL/OUTSRC/rtl8188e/MPChip/BB/AGC_TAB_1T_ICUT.txt + HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG_1T.txt + HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG_1T_ICUT.txt + HAL/OUTSRC/rtl8188e/MPChip/MAC/MAC_REG_ICUT.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/RadioA_1T.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/RadioA_1T_ICUT.txt + HAL/OUTSRC/rtl8188e/MPChip/RF/TxPowerTrack.txt + HAL/OUTSRC/rtl8188e/MPChip/Version.txt + HAL/OUTSRC/rtl8188e/TestChip + HAL/OUTSRC/rtl8188e/TestChip/BB + HAL/OUTSRC/rtl8188e/TestChip/BB/AGC_TAB_1T.txt + HAL/OUTSRC/rtl8188e/TestChip/BB/AGC_TAB_1T_ICUT.txt + HAL/OUTSRC/rtl8188e/TestChip/BB/PHY_REG_1T.txt + HAL/OUTSRC/rtl8188e/TestChip/BB/PHY_REG_1T_ICUT.txt + HAL/OUTSRC/rtl8188e/TestChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8188e/TestChip/FW + HAL/OUTSRC/rtl8188e/TestChip/FW/FW_AP.BIN + HAL/OUTSRC/rtl8188e/TestChip/FW/FW_NIC.BIN + HAL/OUTSRC/rtl8188e/TestChip/FW/FW_WoWLAN.BIN + HAL/OUTSRC/rtl8188e/TestChip/MAC + HAL/OUTSRC/rtl8188e/TestChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8188e/TestChip/RF + HAL/OUTSRC/rtl8188e/TestChip/RF/RadioA_1T.txt + HAL/OUTSRC/rtl8188e/TestChip/RF/TxPowerTrack.txt + HAL/OUTSRC/rtl8188e/TestChip/RF/TXPWR_LMT.txt + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_BB.c + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_BB.h + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_FW.c + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_FW.h + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_MAC.c + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_MAC.h + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_RF.c + HAL/OUTSRC/rtl8192e/HalHWImg8192E_TestChip_RF.h + HAL/OUTSRC/rtl8192e/TestChip + HAL/OUTSRC/rtl8192e/TestChip/BB + HAL/OUTSRC/rtl8192e/TestChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8192e/TestChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8192e/TestChip/FW + HAL/OUTSRC/rtl8192e/TestChip/FW/FW_AP.BIN + HAL/OUTSRC/rtl8192e/TestChip/FW/FW_NIC.BIN + HAL/OUTSRC/rtl8192e/TestChip/FW/FW_WoWLAN.BIN + HAL/OUTSRC/rtl8192e/TestChip/MAC + HAL/OUTSRC/rtl8192e/TestChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8192e/TestChip/RF + HAL/OUTSRC/rtl8192e/TestChip/RF/RadioA.txt + HAL/OUTSRC/rtl8192e/TestChip/RF/RadioB.txt + HAL/OUTSRC/rtl8192e/TestChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8192e/TestChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8192e/TestChip/RF/TxPowerTrack_SDIO.txt + HAL/OUTSRC/rtl8192e/TestChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_BB.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_BB.h + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_MAC.h + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_RF.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_RF.h + HAL/OUTSRC/rtl8821a/MPChip/Version.txt + HAL/OUTSRC/rtl8821a/TestChip + HAL/OUTSRC/rtl8821a/TestChip/BB + HAL/OUTSRC/rtl8821a/TestChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8821a/TestChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8821a/TestChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8821a/TestChip/BB/PHY_REG_PG_DNI.txt + HAL/OUTSRC/rtl8821a/TestChip/BB/PHY_REG_PG_Sercomm.txt + HAL/OUTSRC/rtl8821a/TestChip/FW + HAL/OUTSRC/rtl8821a/TestChip/FW/FW_AP.BIN + HAL/OUTSRC/rtl8821a/TestChip/FW/FW_NIC.BIN + HAL/OUTSRC/rtl8821a/TestChip/FW/FW_NIC_WOWLAN.BIN + HAL/OUTSRC/rtl8821a/TestChip/FW/FW_WoWLAN.BIN + HAL/OUTSRC/rtl8821a/TestChip/MAC + HAL/OUTSRC/rtl8821a/TestChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8821a/TestChip/RF + HAL/OUTSRC/rtl8821a/TestChip/RF/RadioA.txt + HAL/OUTSRC/rtl8821a/TestChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8821a/TestChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8821a/TestChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8821a/TestChip/RF/TXPWR_LMT.txt + HAL/OUTSRC/rtl8821a/TestChip/RF/TXPWR_LMT_8811AU_FEM.txt + HAL/OUTSRC/rtl8821a/TestChip/RF/TXPWR_LMT_8811AU_IPA.txt + HAL/OUTSRC/rtl8821a/TestChip/RF/TXPWR_LMT_8821A.txt + HAL/OUTSRC/rtl8821a/TestChip/Version.txt + 1. Remove dummy files + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- +<05/26/2014 17:00 Stanley> +New Files: +Modified Files: +Change Notes: + +Buildrtwe.bat +Buildrtws.bat +Buildrtwu.bat +COMMON/sources.list +HEADER/PrecompInc.h +COMMON/Beamforming.c +COMMON/Beamforming.h +HAL/Jaguar/rtl8812ae/Hal8812EDef.h +HAL/Jaguar/rtl8812ae/Hal8812EGen.c +HAL/Jaguar/rtl8812au/Hal8812AUsbGen.c +HAL/TXBF +HAL/TXBF/HalTxbf8192E.c +HAL/TXBF/HalTxbf8192E.h +HAL/TXBF/HalTxbf8814A.c +HAL/TXBF/HalTxbf8814A.h +HAL/TXBF/HalTxbf8821B.c +HAL/TXBF/HalTxbf8821B.h +HAL/TXBF/HalTxbfJaguar.c +HAL/TXBF/HalTxbfJaguar.h +HAL/OUTSRC/rtl8812a/HalPhyRf_8812A.c +HAL/OUTSRC/rtl8812a/HalPhyRf_8812A.h +HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.c +HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.h +HAL/OUTSRC/rtl8821b/HalPhyRf_8821B.c +HAL/OUTSRC/rtl8821b/HalPhyRf_8821B.h +HAL/PHY/Hal8812PhyCfg.c +HAL/rtl8192E/rtl8192ee/Hal8192EEGen.c +HAL/rtl8192E/rtl8192eu/Hal8192EUsbGen.c +HAL/rtl8814A/rtl8814ae/Hal8814AEGen.c +HAL/rtl8814A/rtl8814au/Hal8814AUsbGen.c +HAL/rtl8821B/rtl8821be/Hal8821BEGen.c +HAL/rtl8821B/rtl8821bu/Hal8821BUsbGen.c +1. Sync. TXBF architecture from merge_temp + +HAL/halDbgCmd.c +HAL/HalDM.c +HAL/OUTSRC/HalPhyRf.c +HAL/OUTSRC/odm.c +HAL/OUTSRC/odm.h +HAL/OUTSRC/odm_AntDiv.c +HAL/OUTSRC/odm_AntDiv.h +HAL/OUTSRC/odm_debug.c +HAL/OUTSRC/odm_debug.h +HAL/OUTSRC/odm_DIG.c +HAL/OUTSRC/odm_DIG.h +HAL/OUTSRC/odm_DynamicBBPowerSaving.c +HAL/OUTSRC/odm_EdcaTurboCheck.c +HAL/OUTSRC/odm_HWConfig.c +HAL/OUTSRC/odm_PathDiv.c +HAL/OUTSRC/odm_PathDiv.h +HAL/OUTSRC/odm_precomp.h +HAL/OUTSRC/odm_RegDefine11AC.h +HAL/OUTSRC/odm_RegDefine11N.h +HAL/OUTSRC/odm_types.h +HAL/OUTSRC/OutputHWImg.bat +HAL/PHY/Hal8188EPhyCfg.h +HAL/PHY/HalComPhyCfg.c +HAL/PHY/HalComPhyCfg.h +HAL/rtl8814A/Hal8814ACom.c +HAL/rtl8814A/rtl8814as/Hal8814ASdioGen.c +HAL/MPT/MPT_Main.c +HAL/MPT/MPT_Req.c +HAL/OUTSRC/rtl8821a/odm_RTL8821A.c +HAL/OUTSRC/rtl8821a/odm_RTL8821A.h +1. Sync. odm function with merge temp + +HAL/OUTSRC/rtl8188e/HalHWImg8188E_BB.c +HAL/OUTSRC/rtl8188e/HalHWImg8188E_BB.h +HAL/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c +HAL/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h +HAL/OUTSRC/rtl8188e/HalHWImg8188E_RF.c +HAL/OUTSRC/rtl8188e/HalHWImg8188E_RF.h +HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.c +HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.h +HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG_PG.txt +HAL/OUTSRC/rtl8188e/MPChip/MAC/MAC_REG.txt +HAL/OUTSRC/rtl8188e/MPChip/RF/TxPowerTrack_AP.txt +HAL/OUTSRC/rtl8188e/MPChip/RF/TxPowerTrack_PCIE.txt +HAL/OUTSRC/rtl8188e/MPChip/RF/TxPowerTrack_USB.txt +HAL/OUTSRC/rtl8188e/MPChip/RF/TXPWR_LMT.txt +HAL/OUTSRC/rtl8188e/odm_RTL8188E.c +HAL/OUTSRC/rtl8192e/HalHWImg8192E_BB.c +HAL/OUTSRC/rtl8192e/HalHWImg8192E_BB.h +HAL/OUTSRC/rtl8192e/HalHWImg8192E_MAC.c +HAL/OUTSRC/rtl8192e/HalHWImg8192E_MAC.h +HAL/OUTSRC/rtl8192e/HalHWImg8192E_RF.c +HAL/OUTSRC/rtl8192e/HalHWImg8192E_RF.h +HAL/OUTSRC/rtl8192e/HalPhyRf_8192e.c +HAL/OUTSRC/rtl8192e/HalPhyRf_8192e.h +HAL/OUTSRC/rtl8192e/MPChip/BB/AGC_TAB.txt +HAL/OUTSRC/rtl8192e/MPChip/BB/PHY_REG.txt +HAL/OUTSRC/rtl8192e/MPChip/BB/PHY_REG_PG.txt +HAL/OUTSRC/rtl8192e/MPChip/MAC/MAC_REG.txt +HAL/OUTSRC/rtl8192e/MPChip/RF/RadioA.txt +HAL/OUTSRC/rtl8192e/MPChip/RF/RadioB.txt +HAL/OUTSRC/rtl8192e/MPChip/RF/TxPowerTrack_AP.txt +HAL/OUTSRC/rtl8192e/MPChip/RF/TxPowerTrack_PCIE.txt +HAL/OUTSRC/rtl8192e/MPChip/RF/TxPowerTrack_USB.txt +HAL/OUTSRC/rtl8192e/MPChip/RF/TXPWR_LMT.txt +HAL/OUTSRC/rtl8192e/odm_RTL8192E.c +HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.c +HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.h +HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.c +HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.h +HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.c +HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.h +HAL/OUTSRC/rtl8723b/MPChip/BB/AGC_TAB.txt +HAL/OUTSRC/rtl8723b/MPChip/BB/PHY_REG.txt +HAL/OUTSRC/rtl8723b/MPChip/BB/PHY_REG_PG.txt +HAL/OUTSRC/rtl8723b/MPChip/MAC/MAC_REG.txt +HAL/OUTSRC/rtl8723b/MPChip/RF/RadioA.txt +HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_AP.txt +HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_PCIE.txt +HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_SDIO.txt +HAL/OUTSRC/rtl8723b/MPChip/RF/TxPowerTrack_USB.txt +HAL/OUTSRC/rtl8723b/MPChip/RF/TXPWR_LMT.txt +HAL/OUTSRC/rtl8821a/HalHWImg8821A_BB.c +HAL/OUTSRC/rtl8821a/HalHWImg8821A_BB.h +HAL/OUTSRC/rtl8821a/HalHWImg8821A_MAC.c +HAL/OUTSRC/rtl8821a/HalHWImg8821A_MAC.h +HAL/OUTSRC/rtl8821a/HalHWImg8821A_RF.c +HAL/OUTSRC/rtl8821a/HalHWImg8821A_RF.h +HAL/OUTSRC/rtl8821a/MPChip/BB/AGC_TAB.txt +HAL/OUTSRC/rtl8821a/MPChip/BB/PHY_REG.txt +HAL/OUTSRC/rtl8821a/MPChip/BB/PHY_REG_PG.txt +HAL/OUTSRC/rtl8821a/MPChip/MAC/MAC_REG.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/RadioA.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TxPowerTrack_AP.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TxPowerTrack_PCIE.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TxPowerTrack_USB.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8811AU_FEM.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8811AU_IPA.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8821A.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8821A_SAR_5mm.txt +HAL/OUTSRC/rtl8821a/MPChip/RF/TXPWR_LMT_8821A_SAR_8mm.txt +HAL/OUTSRC/rtl8821b/MPChip/RF/RadioA.txt +HAL/OUTSRC/rtl8821b/TestChip/FW/FW_NIC.BIN +1. Sync. all parameter files from merge_temp + +HAL/sources.list.WlanE +HAL/sources.list.WlanS +HAL/sources.list.WlanU +1. Add new file in odm +2. Sync. TXBF architecture from merge_temp +3. Move all parameter files to HAL/OUTSRC + +HEADER/HalDef.h +HAL/rtl8192E/Hal8192EFirmware.c +HAL/rtl8814A/Hal8814AFirmware.c +HAL/rtl8821B/Hal8821BFirmware.c +1. Move all parameter files to HAL/OUTSRC + +Add files: +HAL/OUTSRC/rtl8188e/MPChip/BB/AGC_TAB.txt +HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG.txt +HAL/OUTSRC/rtl8188e/MPChip/RF/RadioA.txt +HAL/OUTSRC/rtl8192c/Hal8192CEHWImg.c +HAL/OUTSRC/rtl8192c/Hal8192CEHWImg.h +HAL/OUTSRC/rtl8192c/Hal8192CHWImgForWoWLAN.c +HAL/OUTSRC/rtl8192c/Hal8192CHWImgForWoWLAN.h +HAL/OUTSRC/rtl8192c/Hal8192CUHWImg.c +HAL/OUTSRC/rtl8192c/Hal8192CUHWImg.h +HAL/OUTSRC/rtl8192d/Hal8192DEHWImg.c +HAL/OUTSRC/rtl8192d/Hal8192DEHWImg.h +HAL/OUTSRC/rtl8192d/Hal8192DUHWImg.c +HAL/OUTSRC/rtl8192d/Hal8192DUHWImg.h +HAL/OUTSRC/rtl8723a/Hal8723AHWImgForWoWLAN.c +HAL/OUTSRC/rtl8723a/Hal8723AHWImgForWoWLAN.h +HAL/OUTSRC/rtl8723a/Hal8723EHWImg.c +HAL/OUTSRC/rtl8723a/Hal8723EHWImg.h +HAL/OUTSRC/rtl8723a/Hal8723EMPHWImg.c +HAL/OUTSRC/rtl8723a/Hal8723EMPHWImg.h +HAL/OUTSRC/rtl8723a/Hal8723SHWImg.c +HAL/OUTSRC/rtl8723a/Hal8723SHWImg.h +HAL/OUTSRC/rtl8723a/Hal8723SMPHWImg.c +HAL/OUTSRC/rtl8723a/Hal8723SMPHWImg.h +HAL/OUTSRC/rtl8723a/Hal8723UHWImg.c +HAL/OUTSRC/rtl8723a/Hal8723UHWImg.h +HAL/OUTSRC/rtl8723a/Hal8723UMPHWImg.c +HAL/OUTSRC/rtl8723a/Hal8723UMPHWImg.h +1. Move all parameter files to HAL/OUTSRC + +Delete folder: +HAL/HWIMG +1. Move all parameter files to HAL/OUTSRC + +Verification Before Checked-In: + 1. N62 buildall OK + 2. MP buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/05/23 20:20 Stanley> +Modified Files: +Change Notes: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_ACS.c + HAL/OUTSRC/odm_ACS.h + HAL/OUTSRC/odm_debug.c + HAL/OUTSRC/odm_debug.h + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + HAL/OUTSRC/odm_precomp.h + HAL/OUTSRC/odm_types.h + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + + 1. Sync. auto channel selection function with merge_temp + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/04/16 13:35 YuChen> +Modified Files: +Change Notes: + OUTSRC/odm_EdcaTurboCheck.c + + 1. Sync EdcaTurboCheck function with sd8 and sd4 + +Verification Before Checked-In: + 1. N62/N63 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/15 19:30 Luke.Lee> +Modified Files: + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/rtl8723a/HalHWImg8723A_BB.c + HAL/OUTSRC/rtl8723a/HalHWImg8723A_BB.h + HAL/OUTSRC/rtl8723a/HalHWImg8723A_MAC.c + HAL/OUTSRC/rtl8723a/HalHWImg8723A_MAC.h + HAL/OUTSRC/rtl8723a/HalHWImg8723A_RF.c + HAL/OUTSRC/rtl8723a/HalHWImg8723A_RF.h + HAL/OUTSRC/rtl8723a/MPChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8723a/MPChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8723a/odm_RegConfig8723A.c + HAL/OUTSRC/rtl8723a/odm_RegConfig8723A.h + +Change Notes: + [8723A] + 1. Update PHY REG V5 format to support Img2HeaderV2 + 2. Remove dummy files + +Verification Before Checked-In: + 1. N62/N63 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/11 18:15 YuChen> +Modified Files: + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.c + HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.h + +Change Notes: + 1. Refine Power Tracking-> RFreg0x55 upper bound is 10, BBSW upper bound is 2dB + 2. sync sd4 and sd7 odm_DIG + +Verification Before Checked-In: + 1. N62/N63 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/10 13:30 Stanley> +Modified Files: + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_AntDiv.c + HAL/OUTSRC/odm_AntDiv.h + HAL/OUTSRC/odm_HWConfig.c + +Change Notes: + 1. Refine SW antenna diversity mechanism + 2. Add antenna diversity by control frame mechanism for RTL8723B\RTL8821A + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/09 23:45 Luke.Lee> +Modified Files: + HAL/halDbgCmd.c + HAL/halDbgCmd.h + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm_debug.c + HAL/OUTSRC/odm_debug.h + HAL/OUTSRC/odm_HWConfig.c + +Change Notes: + 1. Add debug message about PHY Reg version, FW version, etc. (cmd 29 29) + 2. revise GET_VERSION macro + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/09 20:50 Stanley> +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_AntDiv.c + HAL/OUTSRC/odm_AntDiv.h + +Change Notes: + 1. Add reset mechanism for all DM + 2. Add reset mechanism for antenna diversity + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/09 14:12 YuChen> +Modified Files: + HAL/OUTSRC/odm_EdcaTurboCheck.c + +Change Notes: + 1. Remove dummy code + +Verification Before Checked-In: + 1. N62/N63 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/09 10:10 YuChen> +Modified Files: + HAL/OUTSRC/HalPhyRf.c + +Change Notes: + 1. return power tracking if efuse thermal base = 0xff + +Verification Before Checked-In: + 1. N62/N63 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/08 15:50 YuChen> +Modified Files: + HAL/OUTSRC/odm_EdcaTurboCheck.c + HAL/OUTSRC/odm_EdcaTurboCheck.h + +Change Notes: + 1. Sync odm_EdcaTurboCheck to exactly same with SD4 + + +Verification Before Checked-In: + 1. N62/N63 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/07 09:45 YuChen> +Modified Files: + HAL/OUTSRC/HalPhyRf.c + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_precomp.h + HAL/OUTSRC/odm_DynamicBBPowerSaving.c + HAL/OUTSRC/odm_DynamicBBPowerSaving.h + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + +Change Notes: + 1. Seperate odm_DynamicBBPowerSaving and related function from odm.c + 2. Refine HalPhyRf.c, remove wrong mask + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- +<2014/04/03 20:10 Luke.Lee> +Modified Files: + HAL/DESC/Hal8192EETxDesc.c + HAL/DESC/Hal8192EUsbTxDesc.c + HAL/DESC/Hal8723BETxDesc.c + HAL/DESC/Hal8723BUsbTxDesc.c + HAL/DESC/Hal8812AUsbTxDesc.c + HAL/DESC/Hal8812ETxDesc.c + HAL/DESC/Hal8814AUsbTxDesc.c + HAL/DESC/Hal8821BETxDesc.c + HAL/DESC/Hal8821BUsbTxDesc.c + +Change Notes: + 1. [TxBF] disable BW signaling of VHT NPDA to prevent from IOT issue with BCM + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- + +<2014/04/03 17:00 YuChen> +Modified Files: + HAL/OUTSRC/HalPhyRf.c + HAL/OUTSRC/HalPhyRf.h + HAL/OUTSRC/odm.h + HAL/OUTSRC/rtl8814a/HalHWImg8814A_TestChip_BB.c + HAL/OUTSRC/rtl8814a/HalHWImg8814A_TestChip_MAC.c + HAL/OUTSRC/rtl8814a/HalHWImg8814A_TestChip_RF.c + HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.c + HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.h + HAL/OUTSRC/rtl8814a/TestChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/RadioB.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/RadioC.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/RadioD.txt + HAL/OUTSRC/rtl8814a/TestChip/Version.txt + HAL/PHY/HalComPhyCfg.c + HAL/PHY/HalComPhyCfg.h + HAL/PHY/HalJaguarPhyReg.h + +Change Notes: + 1. update 8814 test chip PHY_REG v30 + 2. update 8814 power tracking function + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- +<2014/03/31 13:40 YuChen> +Modified Files: + HAL/OUTSRC/odm_DIG.c + +Change Notes: + 1. Refine adaptivity condition + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------- +<2014/03/28 20:55 Luke.Lee> +Modified Files: + HAL/EFUSE/Hal8814AEfuse.c + HAL/HalDM.c + HAL/OUTSRC/development_note.txt + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/rtl8814a/HalHWImg8814A_TestChip_BB.c + HAL/OUTSRC/rtl8814a/HalHWImg8814A_TestChip_MAC.c + HAL/OUTSRC/rtl8814a/HalHWImg8814A_TestChip_RF.c + HAL/OUTSRC/rtl8814a/HalHWImg8814A_TestChip_RF.h + HAL/OUTSRC/rtl8814a/TestChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8814a/TestChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8814a/TestChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/RadioA.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/RadioB.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/RadioC.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/RadioD.txt +Removed Files: + HAL/OUTSRC/rtl8814a/TestChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8814a/TestChip/RF/TxPowerTrack_PCIE.txt +New Files: + HAL/OUTSRC/rtl8814a/TestChip/RF/TxPowerTrack.txt + HAL/OUTSRC/rtl8814a/TestChip/Version.txt + +Change Notes: + [8814A] + 1. Update PHY Reg V29 + 2. PHY init From Header + +Verification Before Checked-In: + 1.N62 buildall OK + 2. 8814AU test OK + +-------------------------------------------------------------------------------- +<2014/03/28 13:40 James> +Modified Files: + HAL/OUTSRC/rtl8812a/HalPhyRf_8812A.c + 1. Update IQK flow for 2% fail(open RXIQK AGC function & Gain setting & RXIQC Fill) + +Change Notes: + +Verification Before Checked-In: + 1.N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/03/25 17:00 RS_James> +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + +add files: + HAL/OUTSRC/odm_PathDiv.c + HAL/OUTSRC/odm_PathDiv.h + + 1. Seperate odm_PathDiversity and related function from odm.c + +Change Notes: + +Verification Before Checked-In: + 1.N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/03/24 16:40 James> +Modified Files: + HAL/OUTSRC/rtl8821a/HalPhyRf_8821A.c + 1. Update IQK flow for 2% fail(average two LNA result for RXIQK) + +Change Notes: + +Verification Before Checked-In: + 1.N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/03/24 11:50 Stanley> +Modified Files: + HAL/OUTSRC/OutputHWImg.bat + 1. RTL8723B use Image2HeaderV2.exe + + HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_BB.h + HAL/OUTSRC/rtl8723b/HalHWImg8723B_FW.h + HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_MAC.h + HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.c + HAL/OUTSRC/rtl8723b/HalHWImg8723B_RF.h + HAL/OUTSRC/rtl8723b/MPChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8723b/MPChip/RF/RadioA.txt + HAL/OUTSRC/rtl8723b/MPChip/Version.txt + 1. Update MP Parameter to RTL8723B_MP_Parameter_D-cut_v10_20140324 + +Change Notes: + +Verification Before Checked-In: + 1.N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/03/20 22:10 Luke> +Modified Files: + HAL/HalDM.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/rtl8821b/HalHWImg8821B_BB.c + HAL/OUTSRC/rtl8821b/HalHWImg8821B_BB.h + HAL/OUTSRC/rtl8821b/HalHWImg8821B_MAC.c + HAL/OUTSRC/rtl8821b/HalHWImg8821B_MAC.h + HAL/OUTSRC/rtl8821b/HalHWImg8821B_RF.c + HAL/OUTSRC/rtl8821b/HalHWImg8821B_RF.h + HAL/OUTSRC/rtl8821b/HalHWImg8821B_TestChip_BB.c + HAL/OUTSRC/rtl8821b/HalHWImg8821B_TestChip_BB.h + HAL/OUTSRC/rtl8821b/HalHWImg8821B_TestChip_MAC.c + HAL/OUTSRC/rtl8821b/HalHWImg8821B_TestChip_MAC.h + HAL/OUTSRC/rtl8821b/HalHWImg8821B_TestChip_RF.c + HAL/OUTSRC/rtl8821b/HalHWImg8821B_TestChip_RF.h + HAL/OUTSRC/rtl8821b/MPChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8821b/MPChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8821b/MPChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8821b/MPChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8821b/MPChip/RF/RadioA.txt + HAL/OUTSRC/rtl8821b/MPChip/RF/TXPWR_LMT.txt + HAL/OUTSRC/rtl8821b/MPChip/Version.txt + HAL/OUTSRC/rtl8821b/TestChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8821b/TestChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8821b/TestChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8821b/TestChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/RadioA.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TXPWR_LMT.txt + HAL/OUTSRC/rtl8821b/TestChip/Version.txt + +Added Files: + HAL/OUTSRC/rtl8821b/MPChip/BB/PHY_REG_MP.txt + HAL/OUTSRC/rtl8821b/MPChip/RF/TxPowerTrack.txt + HAL/OUTSRC/rtl8821b/TestChip/BB/PHY_REG_MP.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TxPowerTrack.txt + +Remove Files: + HAL/OUTSRC/rtl8821b/MPChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8821b/MPChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8821b/MPChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8821b/TestChip/BB/PHY_REG_PG_DNI.txt + HAL/OUTSRC/rtl8821b/TestChip/BB/PHY_REG_PG_Sercomm.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TXPWR_LMT_8811AU_FEM.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TXPWR_LMT_8811AU_IPA.txt + HAL/OUTSRC/rtl8821b/TestChip/RF/TXPWR_LMT_8821A.txt + +Change Notes: + [8821B] + 1. Update Testchip PHY Reg V14 + 2. Disable DM + +Verification Before Checked-In: + 1.N62 buildall OK + +----------------------------------------------------------------------------------------------------- + +<2014/03/14 17:50 James> +Modified Files: + HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.c +Change Notes: + 1.Lanch to Stand-by mode when IQK in porgessing + + +Verification Before Checked-In: + 1.N62 buildall OK + +----------------------------------------------------------------------------------------------------- + +<2014/03/12 17:50 Stanley> +Modified Files: +Change Notes: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + 1.Add odm_UpdatePowerTrainingState() to disable power training when noisy environment + 2.Retransmit H2C command when power training state is changed + + HAL/halDbgCmd.c + 1.Add debug command to force power training state + + HAL/OUTSRC/odm_DIG.c + HAL/OUTSRC/odm_DIG.h + HAL/OUTSRC/odm_RegDefine11AC.h + 1.Seperate NHM setting and report from odm_NHMBBInit() and NHMBB() + 2.Add CCA conuter report in odm_FalseAlarmCounterStatistics() for 11ac series + + HAL/Jaguar/Hal8812MultiRate.c + HAL/rtl8188E/Hal8188ECom.c + HAL/rtl8192C/Hal8192CCom.c + HAL/rtl8192E/Hal8192ECom.c + HAL/rtl8723B/Hal8723BCom.c + HAL/rtl8814A/Hal8814ACom.c + HAL/rtl8821B/Hal8821BMultiRate.c + 1.Disable power training when noisy environment + +Verification Before Checked-In: + 1.N62 buildall OK + +----------------------------------------------------------------------------------------------------- + +<2014/03/12 11:00 YuChen> +Modified Files: +Change Notes: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_precomp.h + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU +add files + HAL/OUTSRC/odm_EdcaTurboCheck.c + HAL/OUTSRC/odm_EdcaTurboCheck.h + + 1. Seperate odm_EdcaTurboCheck function from odm.c + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- + +<2014/03/07 10:39 James> +Modified Files: +Change Notes: + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_BB.c + HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG_1T.txt + HAL/OUTSRC/rtl8188e/MPChip/BB/PHY_REG_1T_ICUT.txt + HAL/OUTSRC/rtl8188e/MPChip/Version.txt + HAL/OUTSRC/rtl8192e/HalHWImg8192E_BB.c + HAL/OUTSRC/rtl8192e/HalHWImg8192E_RF.c + HAL/OUTSRC/rtl8192e/HalHWImg8192E_RF.h + HAL/OUTSRC/rtl8192e/MPChip/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8192e/MPChip/BB/PHY_REG.txt + HAL/OUTSRC/rtl8192e/MPChip/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8192e/MPChip/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8192e/MPChip/RF/RadioA.txt + HAL/OUTSRC/rtl8192e/MPChip/RF/RadioB.txt + HAL/OUTSRC/rtl8192e/MPChip/RF/TxPowerTrack_AP.txt + HAL/OUTSRC/rtl8192e/MPChip/RF/TxPowerTrack_PCIE.txt + HAL/OUTSRC/rtl8192e/MPChip/RF/TxPowerTrack_USB.txt + HAL/OUTSRC/rtl8192e/MPChip/RF/TXPWR_LMT.txt + + 1. Update 92E PHY reg pacakge to v28 + 2. Using 92E_PCIE power tracking table on 92E_SDIO interface + 3. Update 88E PHY reg pacakge to v48 + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- + +<2014/03/04 21:19 James> +Modified Files: +Change Notes: + OUTSRC/rtl8814a/HalPhyRf_8814A.c + 1. [8814A] add Path B/C/D RF Backup in IQK + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- + +<2014/03/04 11:30 YuChen> +Modified Files: +Change Notes: + HAL/OUTSRC/odm_DIG.c + HAL/OutSRC/odm.h + 1. [ODM] Adaptivity Refine + a.rename odm_DynamicAdjustAdaptivtiyThreshold to odm_SearchPwdBLowerBound + b.remove False alarm detect in odm_NHMBB() + c.refine odm_PauseDIG() to prevent scan insert during adaptivity odm_SearchPwdBLowerBound processing + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/02/26 15:20 Lanhsin> +Modified Files: +Change Notes: + HAL/PHY/Hal8814APhyCfg.c + 1. Update to WB-20140226-YN-RLE0572B+user+guide+for+BB+functions-R18. + +Verification Before Checked-In: + 1. N63/MP buildall OK +----------------------------------------------------------------------------------------------------- +<2014/02/26 13:30 James> +Modified Files: + odm_HWConfig.c + +Change Notes: + 1. [8189ES] Add power tracking table for 8189ES + (the table is same as PCIE & USB table, suggest by RF Dennis) + +Verification Before Checked-In: + 1. N62 buildall OK +----------------------------------------------------------------------------------------------------- +<2014/02/24 20:45 Stanley> +Modified Files: + HAL/OUTSRC/odm.c + +Change Notes: + 1. [8814A] Modify the offset of crystal cap. for ATC + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<2014/02/07 17:00 MH_C> +Modified Files: +Change Notes: + 1. Allow ODM group to check in trunk code. + +Verification Before Checked-In: + 1. NA + +----------------------------------------------------------------------------------------------------- diff --git a/network/wlan/WDI/HAL/phydm/development_note2012.txt b/network/wlan/WDI/HAL/phydm/development_note2012.txt new file mode 100644 index 00000000..a5b3b057 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/development_note2012.txt @@ -0,0 +1,5272 @@ + +----------------------------------------------------------------------------------------------------- +<2014/09/03 14:15 Dino Reviewer:Luke > +Modified Files: + HAL/OUTSRC/rtl8192e/HalPhyRf_8192e.c + +Change Notes: + 1. Fix the coding error of 92E Power tracking in assigning pathA/B CCK-11M TX power + +Verification Before Checked-In: + 1. N62 build all ok + +----------------------------------------------------------------------------------------------------- +<2014/04/18 19:00 James> +Modified Files: +Change Notes: + HAL/OUTSRC/odm_debug.c + HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.c + HAL/OUTSRC/rtl8814a/HalPhyRf_8814A.h + HAL/PHY/HalComPhyCfg.c + HAL/PHY/HalComPhyCfg.h + HAL/rtl8814A/Hal8814ACom.c + HAL/rtl8814A/rtl8814as/Hal8814ASdioGen.c + 1. Refine 8814A IQK function + +Verification Before Checked-In: + 1. N62/N63 buildall OK + 2. Mp buildall OK + +----------------------------------------------------------------------------------------------------- +<08/08/2012 19:50 LukeLee> +Modified Files: + + +Change Notes: + + 1. Merge WIN Trunk v2908 + 2. [8812A] Update MAC_PHY Reg V021 for MP chip + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<08/08/2012 13:45 LukeLee> +Modified Files: + + HAL/OUTSRC/odm_debug.c + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/OutputHWImg.bat + HAL/OUTSRC/rtl8723a/BB/AGC_TAB_1T.TXT + HAL/OUTSRC/rtl8723a/BB/PHY_REG_1T.txt + HAL/OUTSRC/rtl8723a/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8723a/HalHWImg8723A_BB.c + HAL/OUTSRC/rtl8723a/HalHWImg8723A_BB.h + HAL/OUTSRC/rtl8723a/HalHWImg8723A_MAC.c + HAL/OUTSRC/rtl8723a/HalHWImg8723A_RF.c + HAL/OUTSRC/rtl8723a/HalHWImg8723A_RF.h + HAL/OUTSRC/rtl8723a/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8723a/RF/RadioA_1T.txt + HAL/OUTSRC/rtl8821a/HalHWImg8821A_FW.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_FW.h + HAL/rtl8188E/Hal8812Firmware.c + + +Change Notes: + + 1. [8723A] Update MAC_PHY_REG v001 + 2. [8821A] Update FW v001 + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<08/07/2012 20:55 LukeLee> +Modified Files: + + HAL/OUTSRC/rtl8188e/BB/AGC_TAB_1T.txt + HAL/OUTSRC/rtl8188e/BB/PHY_REG_1T.txt + HAL/OUTSRC/rtl8188e/BB/PHY_REG_PG.txt + HAL/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c + HAL/OUTSRC/rtl8188e/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8188e/RF/RadioA_1T.txt + +Change Notes: + + 1. [8188E] Update MAC_PHY_REG v035 + +Verification Before Checked-In: + 1. N62 buildall OK + +----------------------------------------------------------------------------------------------------- +<08/07/2012 19:50 LukeLee> +Modified Files: + + HAL/OUTSRC/rtl8812a/BB/AGC_TAB.txt + HAL/OUTSRC/rtl8812a/BB/PHY_REG.txt + HAL/OUTSRC/rtl8812a/HalHWImg8812A_TestChip_BB.c + HAL/OUTSRC/rtl8812a/HalHWImg8812A_TestChip_MAC.c + HAL/OUTSRC/rtl8812a/HalHWImg8812A_TestChip_RF.c + HAL/OUTSRC/rtl8812a/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8812a/RF/RadioA.txt + HAL/OUTSRC/rtl8812a/RF/RadioB.txt + HAL/OUTSRC/rtl8821a/BB/PHY_REG.txt + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_BB.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_MAC.c + HAL/OUTSRC/rtl8821a/HalHWImg8821A_TestChip_RF.c + HAL/OUTSRC/rtl8821a/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8821a/RF/RadioA.txt + +Change Notes: + + 1. [8812A] Update MAC_PHY_REG v021 + 2. [8821A] Update MAC_PHY_REG v006 + +Verification Before Checked-In: + 1. N62 buildall OK +----------------------------------------------------------------------------------------------------- +<08/06/2012 11:40 LukeLee> +Modified Files: + +Change Notes: + + 1. Merge WIN Trunk v2897 + 2. Update Img2Header.exe + +Verification Before Checked-In: + 1. N62/N5 buildall OK + +----------------------------------------------------------------------------------------------------- +<07/31/2012 17:10 LukeLee> +Modified Files: + + \rtl8812a\BB\AGC_TAB.c + \rtl8812a\BB\PHY_REG.txt + \rtl8812a\MAC\MAC_REG.txt + \rtl8812a\RF\RadioA.txt + \rtl8812a\RF\RadioB.txt + \rtl8812a\HalHWImg8812A_TestChip_BB.c + \rtl8812a\HalHWImg8812A_TestChip_RF.c + +Change Notes: + + 1. [8812A] Update MAC_PHY_REG v20 + +Verification Before Checked-In: + 1. N62 buildall OK + 2. Img2Header.exe has problem with FW transformation + +---------------------------------------------------------------------------------------------- +<07/31/2012 17:00 JueYang> +New Files: +Modified Files: + HAL\PHY\Hal8188EPhyCfg.c + +Change Notes: + 1. Fix 20M TxPower Error for TPLINK. + +Verification Before Checked-In: + 1. N63 buildall ok. +----------------------------------------------------------------------------------------------------- +<07/31/2012 11:35 Georgia> +Modified Files: + +Change Notes: + + 1. Fixed incorrect data rate in wireless BG mode. + +Verification Before Checked-In: + 1. 8188EUS CE driver test OK. +----------------------------------------------------------------------------------------------------- +<07/30/2012 12:25 LukeLee> +Modified Files: + +Change Notes: + + 1. Fix compile error of ODM v364 + +Verification Before Checked-In: + 1. N62/N5 buildall OK. + +----------------------------------------------------------------------------------------------------- +<07/30/2012 13:50 LukeLee> +Modified Files: + +Change Notes: + + 1. Merge Trunk V2285 + +Verification Before Checked-In: + 1. N62/N5 buildall OK. + +----------------------------------------------------------------------------------------------------- +<07/23/2012 15:50 Kordan> +Modified Files: +Change Notes: + 1. Update Image2Header: + a. A single-line comment is now allowable with if-else body. + b. Bug fixed: #endif is missed when translating FW_AP.bin. + c. '/' is allowed with FILE_NAME. + +Verification Before Checked-In: + 1. Translation OK. + + +----------------------------------------------------------------------------------------------------- +<07/23/2012 15:50 Kordan> +Modified Files: +Change Notes: + 1. Update Image2Header: + a. A single-line comment is now allowable with if-else body. + b. Bug fixed: #endif is missed when translating FW_AP.bin. + c. '/' is allowed with FILE_NAME. + +Verification Before Checked-In: + 1. Translation OK. + +----------------------------------------------------------------------------------------------------- +<07/19/2012 16:06 LukeLee> +Modified Files: + + /rtl8188e/Hal8188ERateAdaptive.c + /rtl8188e/Hal8188ERateAdaptive.h + /rtl8188e/HalPhyRf_8188e.c + /rtl8188e/odm_RTL8188E.c + /rtl8188e/odm_RTL8188E.h + /rtl8192c/Hal8192CEFWImg_AP.h + /rtl8192c/Hal8192CEMACImg_AP.h + /rtl8192c/Hal8192CEPHYImg.h + /rtl8192c/Hal8192CEPHYImg_AP.h + /rtl8192c/Hal8192CUPHYImg.h + /rtl8192c/odm_RTL8192C.c + /rtl8192c/odm_RTL8192C.h + /rtl8192d/odm_RTL8192D.c + /rtl8192d/odm_RTL8192D.h + /rtl8812a/HalPhyRf_8812A.c + HalPhyRf.c + HalPhyRf.h + odm.c + odm.h + odm_debug.h + odm_HWConfig.c + odm_HWConfig.h + odm_interface.c + odm_interface.h + odm_precomp.h + odm_types.h + +Removed Files: + + Hal8188EDMOutSrc.c + Hal8188EDMOutSrc.h + Hal8192CDMOutSrc.c + Hal8192CDMOutSrc.h + Hal8812DMOutSrc.c + Hal8812DMOutSrc.h + HalComDMOutSrc.c + HalComDMOutSrc.h + +Change Notes: + + 1. Replace ODM_MP with ODM_WIN + 2. Remove redundancy files + +Verification Before Checked-In: + 1. N62 buildall OK. + +----------------------------------------------------------------------------------------------------- +<07/18/2012 15:45 LukeLee> +Modified Files: + + /rtl8188e/BB/AGC_TAB_1T.txt + /rtl8188e/BB/PHY_REG_1T.txt + /rtl8188e/BB/PHY_REG_PG.txt + /rtl8188e/MAC/MAC_REG.txt + /rtl8188e/RF/RadioA_1T.txt + /rtl8812a/HalHWImg8188E_BB.c + /rtl8812a/HalHWImg8188E_FW.c + +Change Notes: + + 1. [8188E] Release MAC_PHY_Reg V033 + 2. Img2Header.exe has problem, must add #endif in the end of HalHWImg8188E_FW.c + +Verification Before Checked-In: + 1. N62 buildall OK. + + +----------------------------------------------------------------------------------------------------- +<07/17/2012 23:15 LukeLee> +Modified Files: + + /rtl8812a/BB/AGC_TAB.txt + /rtl8812a/BB/PHY_REG.txt + /rtl8812a/MAC/MAC_REG.txt + /rtl8812a/RF/RadioA.txt + /rtl8812a/RF/RadioB.txt + /rtl8812a/HalHWImg8812A_BB.c + /rtl8812a/HalHWImg8812A_RF.c + /rtl8812a/HalHWImg8812A_BB_testchip.c + /rtl8812a/HalHWImg8812A_RF_testhcip.c + +Change Notes: + + 1. [8812A] Release MAC_PHY_Reg V019 + +Verification Before Checked-In: + 1. N62 buildall OK. + +----------------------------------------------------------------------------------------------------- +<07/17/2012 17:47 NeilChen> +Modified Files: + + odm.c + odm_interface.c +Change Notes: + + 1. Initialize SW Antenna diversity ANT flag by efuse PG Setting for all + 8723A Series IC MP + 2. Fix H2C cmd Issue in odm_interface.c + +Verification Before Checked-In: + 1. N62 buildall OK. + +----------------------------------------------------------------------------------------------------- +<07/11/2012 19:18 NeilChen> +Modified Files: + + odm.c + hal\rtl8192c\rtl8192ce\hal8192CEGen.c +Change Notes: + + 1.Fix 8723A SW ANT DIV Bug in MP temporality + +Verification Before Checked-In: + 1. N62 buildall OK. + 2. 8723AS_VAU testing OK +------------------------------------------------------------------------------------------------------ +<07/11/2012 17:45 Luke.Lee> +Modified Files: + + /rtl8812a/RF/RadioA.txt + /rtl8812a/RF/RadioB.txt + /rtl8812a/HalHWImg8812A_RF.c + /rtl8812a/HalHWImg8812A_TestChip_RF.c + odm_HWConfig.c + odm_precomp.h + odm_types.h + +Change Notes: + + /OUTSRC/*.c, *.h + 1.[8812A] revise PHY Reg files + + /HAL/rtl8188E/Hal8812Firmware.c + 2.[8812A] enable DL FW from header + + /HAL/rtl8192C/Hal8192CFirmware.c + 3.[8723A] add back ODM v344 feature + +Verification Before Checked-In: + 1. N62 buildall OK. + 2. 8812AE vs 8812AP DL:280Mbps, UL:330Mbps + 3. 8812AE vs 8812AE AdHoc 400Mbps(force 2SS MCS6) + + +------------------------------------------------------------------------------------------------------ +<07/10/2012 16:40 Luke.Lee> +Modified Files: + +Change Notes: + + 1.Copy Merge_Temp v2836 except OUTSRC + +Verification Before Checked-In: + 1. N62 buildall OK. + +------------------------------------------------------------------------------------------------------ +<07/09/2012 14:30 Luke.Lee> +Modified Files: + + /8812a/HalHWImg8812A_BB.c + /8812a/HalHWImg8812A_BB.h + /8812a/HalHWImg8812A_FW.c + /8812a/HalHWImg8812A_FW.h + /8812a/HalHWImg8812A_RF.c + /8812a/HalHWImg8812A_TestChip_BB.c + /8812a/HalHWImg8812A_TestChip_BB.h + /8812a/HalHWImg8812A_TestChip_MAC.c + /8812a/HalHWImg8812A_TestChip_RF.c + /8812a/HalHWImg8812A_TestChip_RF.h + odm_debug.c + odm_HWConfig.c + odm_precomp.h + odm_types.h + + +Change Notes: + + 1.[8812A] Modify Reg Init Flow (Currently is TestChip only) + +Verification Before Checked-In: + 1. N62 buildall OK. + +------------------------------------------------------------------------------------------------------ +<07/06/2012 15:00 Luke.Lee> +Modified Files: + + HAL/OUTSRC/HalPhyRf.c + HAL/OUTSRC/HalPhyRf.h + HAL/OUTSRC/odm_precomp.h + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.h + +Change Notes: + + 1.Remove AP compile error + +Verification Before Checked-In: + 1. N5/N62 buildall OK. + 2. AP compile OK + +---------------------------------------------------------------------------------------------- +<07/06/2012 15:00 lena_yang> +New Files: +Modified Files: +Change Notes: + 1. Fix 92DU VC BSOD When UNinstall One MAC + +Verification Before Checked-In: + 1. N5/N62 buildall OK. + + +------------------------------------------------------------------------------------------------------ +<07/06/2012 14:30 Cherry> +Modified Files: +Change Notes: + + HAL\HalDM.c + HAL\OUTSRC\odm.c + 1. Enable 8812 EDCA TUREBO mode. + +Verification Before Checked-In: + 1. N5/N62 buildall OK. + + +------------------------------------------------------------------------------------------------------ +<07/06/2012 10:40 Mingzhi> +New Files: +Modified Files: + odm.c + +Change Notes: + 1. modify EDCA turbo for MP + +Verification Before Checked-In: + 1. WIN N5/N62 buildall ok. +---------------------------------------------------------------------------------------------- +<07/04/2012 14:30 Kordan> +New Files: +Modified Files: + HAL/rtl8188E/rtl8188ee/Hal8188EEGen.c + HAL/rtl8188E/rtl8188es/Hal8188ESdioGen.c + +Change Notes: + 1. Fix compilation error. + +Verification Before Checked-In: + 1. WIN N5/N62 buildall ok. + +------------------------------------------------------------------------------------------- +<07/03/2012 17:00 Kordan> +Modified Files: + HAL/OUTSRC/HalPhyRf.c + HAL/OUTSRC/HalPhyRf.h + HAL/OUTSRC/rtl8812a/HalPhyRf_8812A.c + HAL/OUTSRC/rtl8812a/HalPhyRf_8812A.h + HAL/rtl8188E/Hal8812Com.c + HAL/rtl8188E/rtl8188ee/Hal8188EEGen.c + HAL/rtl8188E/rtl8188es/Hal8188ESdioGen.c + PLATFORM/NDIS5/N5C_Req.c + +Change Notes: + 1. Implement 8812A IQK prototype. + +Verification Before Checked-In: + 1. MP Buildall ok. + 2. For test only. + +------------------------------------------------------------------------------------------- +<06/25/2012 21:25 LukeLee> Modified Files: + odm.c + +Change Notes: + 1. [8723A]modify odm_CommonInfoSelfInit() to enable SW AntDiv + +Verification Before Checked-In: + 1. WIN N62 Buildall ok. + +------------------------------------------------------------------------------------------- +<06/22/2012 18:30 LukeLee> Modified Files: + rtl8188e\HalHWImg8188E_BB.c + rtl8188e\HalHWImg8188E_FW.c + rtl8188e\HalHWImg8188E_FW.h + rtl8188e\HalHWImg8188E_MAC.c + rtl8188e\HalHWImg8188E_RF.c + rtl8188e\BB\PHY_REG_1T.txt + +Change Notes: + 1. [88E]release 88E MAC_PHY_REG v032 for default ant setting + +Verification Before Checked-In: + 1. WIN N62 Buildall ok. + +------------------------------------------------------------------------------------------- +<06/22/2012 14:36 NeilChen> Modified Files: + odm.c + odm.h + Hal8192CFirmware.c +Change Notes: + 1. Fix PSD for BT3.0 TP issue + 2. if BT3.0 is running, PSD scan times will be to decrease + +Verification Before Checked-In: + 1. WIN N5 Buildall ok. + 2. 8723AE Testing OK. +------------------------------------------------------------------------------------------- +<06/22/2012 14:25 button> +Modified Files: + OUTSRC/rtl8188e/HalPhyRf_8188e.c + OUTSRC/Hal8188ERateAdaptive.c +Change Notes: + 1. Use Common macro to parse Tx report + 2. Resolve compile error in AP platform + +Verification Before Checked-In: + 1. AP platform compile ok. +------------------------------------------------------------------------------------------ +<06/19/2012 19:40 Alexchou> +Modified Files: + + OUTSRC/rtl8812a/FW/FW_NIC.BIN + OUTSRC/rtl8812a/FW/FW_WoWLAN.BIN + OUTSRC/rtl8812a/HalHWImg8812A_FW.c + OUTSRC/rtl8812a/HalHWImg8812A_FW.h + +Change Notes: + 1. Update 8812 testchip formal firmware V0003. + +Verification Before Checked-In: + 1. ImgTransfer ok. + +------------------------------------------------------------------------------------------- +<06/18/2012 16:50 NeilChen> +Modified Files: + odm.c + odm.h + odm_RTL8188E.h + HalDMOutSrc8192C_AP.c + HalDMOutSrc8192C_CE.c + +Change Notes: + 1. To integrate ANT definition for SW ANT DIV and ANT detect of ODM + mechanism + 2. MAIN_ANT is use to replace Antenna_A and ANT_Main + 3. AUX_ANT is use to replace Antenna_B and ANT_Aux + +Verification Before Checked-In: + 1.WIN N5 Buildall ok. + +------------------------------------------------------------------------------------------- +<06/13/2012 16:30 Georgia> +Modified Files: + rtl8188e/HalHWImg8188E_FW.c + +Change Notes: + 1. Fixed symbol:Array_8188E_FW_NIC undefine error for 88E. + +Verification Before Checked-In: + 1.CE DRV make all ok. + 1.WIN N5 buildall ok. + +------------------------------------------------------------------------------------------- +<06/13/2012 15:30 Georgia> +Modified Files: + rtl8188e/HalPhyRf_8188e.c +Change Notes: + 1. Fixed compile error for CE Platform. + +Verification Before Checked-In: + 1.CE DRV make all ok. + +-------------------------------------------------------------------------------------------- +<06/11/2012 21:00 LukeLee> +Deleted Files: +Change Notes: + HAL\OUTSRC\odm.c + 1. Revise Single/Dual Ant Detection for 88C + +Verification Before Checked-In: + 1. WIN N62 buildall ok. + 2. 88CE ant detection OK + +-------------------------------------------------------------------------------------------- +<06/08/2012 16:12 James> +Deleted Files: +Change Notes: + 1. Update 8812 BB/MAC/RF parameters to V13 + +Verification Before Checked-In: + 1. WIN N5/N62 buildall ok. + 2. 8812AU XP scan ok. 8812AU link with WPA-2 AES AP ok. + +-------------------------------------------------------------------------------------------- +<06/07/2012 16:04 MH_Chen> +Deleted Files: +Change Notes: + HAL\OUTSRC\odm.c + 1. Remove 8812 DM init return. + +Verification Before Checked-In: + 1. WIN N5/N62 buildall ok. + 2. 8812AU win7 scan ok. 8812AU signal strength display ok. + +-------------------------------------------------------------------------------------------- +<06/06/2012 19:04 MH_Chen> +Deleted Files: +Change Notes: + COMMON &\HAL\Non-ODM & PLATFORM + 1. Merge from windows driver trunk v2764-2766. Support 8812AU dual band scan. + + +Verification Before Checked-In: + 1. WIN N5/N62 buildall ok. + 2. 8812AE/AU win7 scan ok. 8812AU reload test for 100 rounds ok. + 3. 88CU win7 simple test ok. S3/S4/Reload/ Unlpg ok. + +-------------------------------------------------------------------------------------------- +<06/06/2012 20:10 Georgia> +Modified Files: + odm.c + rtl8188e/Hal8188ERateAdaptive.c + rtl8188e/HalHWImg8188E_BB.c + rtl8188e/HalHWImg8188E_FW.c + rtl8188e/HalHWImg8188E_MAC.c + rtl8188e/HalHWImg8188E_RF.c + rtl8188e/HalPhyRf_8188e.c + rtl8188e/odm_RegConfig8188E.c + rtl8188e/odm_RTL8188E.c + rtl8192c/odm_RTL8192C.c + rtl8192d/odm_RTL8192D.c + rtl8723a/HalHWImg8723A_BB.c + rtl8723a/HalHWImg8723A_FW.c + rtl8723a/HalHWImg8723A_MAC.c + rtl8723a/HalHWImg8723A_RF.c + rtl8723a/odm_RegConfig8723A.c + +Change Notes: + 1. Fix compile error. + +Verification Before Checked-In: + 1. CE Platform ,make all ok. + +-------------------------------------------------------------------------------------------- +<06/06/2012 19:04 MH_Chen> +Deleted Files: +Change Notes: + COMMON &\HAL\Non-ODM & PLATFORM + 1. Merge from windows driver trunk v2744-2763. + ODM + 1. Revise compile error for windows driver. + +Verification Before Checked-In: + 1. WIN N5/N62 buildall ok. + 2. 8812AE/AU win7 scan ok. 8812AU reload test for 100 rounds ok. + 3. 88EE win7 ping test ok. + 4. 88EU win7 simple test ok. S3/S4/Reload/ Unlpg ok. + 4. 88CU win7 simple test ok. S3/S4/Reload/ Unlpg ok. + +-------------------------------------------------------------------------------------------- +<06/06/2012 15:44 Georgia> +Modified Files: + HalPhyRf.c + odm.c + odm.h + odm_HWConfig.c + odm_HWConfig.h + odm_types.h + rtl8188e/Hal8188EFWImg_CE.c + rtl8188e/Hal8188EFWImg_CE.h + rtl8188e/Hal8188ERateAdaptive.c + rtl8188e/Hal8188ERateAdaptive.h + rtl8188e/HalHWImg8188E_BB.c + rtl8188e/HalHWImg8188E_FW.c + rtl8188e/HalHWImg8188E_MAC.c + rtl8188e/HalHWImg8188E_RF.c + rtl8188e/HalPhyRf_8188e.c + rtl8188e/odm_RegConfig8188E.c + rtl8188e/odm_RTL8188E.c + rtl8188e/odm_RTL8188E.h + rtl8192c/odm_RTL8192C.c + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/odm_RTL8192D.c + rtl8723a/HalHWImg8723A_BB.c + rtl8723a/HalHWImg8723A_FW.c + rtl8723a/HalHWImg8723A_MAC.c + rtl8723a/HalHWImg8723A_RF.c + rtl8723a/odm_RegConfig8723A.c + +Change Notes: + 1. Add RefreshRAMask for CE platform. + 2. Move releated marco of TX_RPT prasing to Hal8188ERateAdaptive.h. + 3. Change data type of ODM_PHY_INFO_T - RxPWDBAll to u1Byte. + 3. Fix compile error for CE Platform. + +Verification Before Checked-In: + 1. Make all chip drv ok on CE Platform. + 2. 88EUS/89ES auto-test ok. +-------------------------------------------------------------------------------------------- +<06/06/2012 14:35 MH_Chen> +Modified Files: +Change Notes: + Merge from 2718 to 2743. + +Verification Before Checked-In: + 1. N5/N62 buildall. + 2. 88EE ping ok. But s4/reload fail!!?. + +-------------------------------------------------------------------------------------------- +<06/06/2012 14:15 MH_Chen> +Deleted Files: +Change Notes: + COMMON &\HAL\Non-ODM & PLATFORM + 1. Merge from windows driver trunk v2718-2743. + HAL\OUTSRC\rtl8812a\BB\AGC_TAB.txt.... + 1. Use MP trunk driver HW parameters to replace ODM\MP parameters and scan ok. + 2. Use new img2header to transfer MP trunk 8812 parametes. + 3. RF delay pattern change back to 0xFE?? or 0xFFE?? + +Verification Before Checked-In: + 1. WIN N5/N62 buildall ok. + 2. 8812AE/AU win7 scan ok. + 3. 88EE win7 ping test ok. + 4. 88EU win7 simple test ok. S3/S4/Reload/ Unlpg ok. + 4. 88C2U win7 simple test ok. + +-------------------------------------------------------------------------------------------- +<06/04/2012 21:55 Gimmy> +Deleted Files: + \HAL\OUTSRC\rtl8188e\FW\RTL8188EFW_A_CUT_T.BIN + +Change Notes: + 1. delete \HAL\OUTSRC\rtl8188e\FW\RTL8188EFW_A_CUT_T.BIN + +Verification Before Checked-In: + 1. NONE. + 2. ImgTransfer ok. + +-------------------------------------------------------------------------------------------- +<06/04/2012 20:35 LukeLee> +Modified Files: + \rtl8188e\BB\PHY_REG_1T.txt + \rtl8188e\HalHWImg8188E_BB.c + \rtl8188e\HalHWImg8188E_FW.c + \rtl8188e\HalHWImg8188E_FW.h + \rtl8812a\HalHWImg8812A_BB.c + +Change Notes: + 1. [88E]Release MAC_PHY_REG v031 for BB swing issue + 2. [8812A] manually add "0" to patch Img2Header.exe bug + +Verification Before Checked-In: + 1. N62 buildall OK + 2. 88EE BB QC test OK + +--------------------------------------------------------------------------------------------- +<06/04/2012 14:45 Gimmy> +New Files: + HAL/OUTSRC/rtl8188e/FW/FW_AP.BIN + +Modified Files: + HAL/OUTSRC/rtl8188e/FW/FW_NIC.BIN + HAL/OUTSRC/rtl8188e/FW/FW_WoWLAN.BIN + HAL/OUTSRC/rtl8188e/HalHWImg8188E_FW.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_FW.h + HAL/OUTSRC/rtl8812a/HalHWImg8812A_BB.c + +Change Notes: + 1. Update 88E formal firmware. V004. + +Verification Before Checked-In: + 1. NONE. + 2. ImgTransfer ok. + +-------------------------------------------------------------------------------------------- +<06/01/2012 20:00 LukeLee> +Modified Files: + HAL/OUTSRC/odm.c + +Change Notes: + 1. [88E]Fix TP bad issue caused by V321 + +Verification Before Checked-In: + 1. N62 buildall OK + 2. 88EE TP test OK + +-------------------------------------------------------------------------------------------- +<06/01/2012 18:50 LukeLee> +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_RegDefine11AC.h + HAL/OUTSRC/odm_RegDefine11N.h + +Change Notes: + 1. Define bCckHighPower & RFPathRxEnable for Jaguar series + 2. Revise if/else conidition of odm_HwAntDiv and odm_SwAntDivChkAntSwitch + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------------------- +<05/30/2012 22:10 LukeLee> +Modified Files: + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/odm.c + +Change Notes: + 1. Modify odm_RxPhyStatusJaguarSeries_Parsing() + 2. Add Back compile flag in Odm.c for CE team + + +Verification Before Checked-In: + 1. N62 buildall OK + 2. 88EE Ad-Hoc ping OK, RSSI report OK + +-------------------------------------------------------------------------------------------- +<05/30/2012 21:26 Alexchou> +Modified Files: +Change Notes: + + rtl8812a/FW/FW_NIC.BIN + rtl8812a/HalHWImg8812A_FW.c + rtl8812a/HalHWImg8812A_FW.h + rtl8812a/FW/FW_WoWLAN.BIN + 1. update 8812 testchip fw v0002 for new Img2header.exe + + rtl8812a/FW/RTL8812FW_Test_T.BIN + rtl8812a/HalHWImg8812A_TestChip_FW.c + rtl8812a/HalHWImg8812A_TestChip_FW.h + 1. remove unused files + + +Verification Before Checked-In: + 1. None +-------------------------------------------------------------------------------------------- +<05/30/2012 20:17 MH_Chen> +Modified Files: +Change Notes: + COMMON\TransmitDesc.c + 1. Support new ODM relative AID for luke. + HAL\DESC + 1. Revise raw data input and ODM RSSI parsing with required MACID. + HAL\ODM + 1. Revise for PHY query inRX side and TX side TXFILLDESC. + HAL\HalDM.c + + +Verification Before Checked-In: + 1. N5/N62 buildall. + 2. 88EU simple test ok. AP mode RSSI parsing ok. But vwifi fail. + +-------------------------------------------------------------------------------------------- +<05/30/2012 17:40 Kordan> +Modified Files: +Change Notes: + 1. Support 8188E/8812A MAC, BB, RF, and FW configuration. + Buildrtwe.bat + Buildrtws.bat + Buildrtwu.bat + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/odm_HWConfig.h + HAL/OUTSRC/odm_interface.c + HAL/OUTSRC/odm_interface.h + HAL/OUTSRC/odm_precomp.h + HAL/OUTSRC/OutputHWImg.bat + HAL/rtl8188E/Hal8188EFirmware.c + HAL/rtl8188E/Hal8812Firmware.c + HAL/rtl8188E/rtl8188ee/Hal8188EEGen.c + HAL/rtl8188E/rtl8188ee/Hal8812EGen.c + HAL/rtl8188E/rtl8188es/Hal8188ESdioGen.c + HAL/rtl8188E/rtl8188eu/Hal8188EUsbGen.c + HAL/rtl8188E/rtl8188eu/Hal8812AUsbGen.c + HAL/sources.list.WlanE + HAL/sources.list.WlanS + HAL/sources.list.WlanU + + 2. Minor bug fixed and some improvement on Image2Header. + 3. Supports batch conversion. + HAL/OUTSRC/Image2Header.exe + HAL/OUTSRC/rtl8188e/* + HAL/OUTSRC/rtl8723a/* + HAL/PHY/Hal8188EPhyCfg.c + HAL/PHY/Hal8192CPhyCfg.c + HAL/OUTSRC/OutputHWImg.bat + + 4. Fix compilation error and revise the code of 88E ODM power tracking. + HAL/MPT/MPT_Bt.c + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.c + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.h + +Verification Before Checked-In: + 1. N5/N62/MP buildall OK. + 2. 88EE MP T/Rx ok. + 3. The PHY reg package of both 8188E and 8812A might be wrong, + please update the PHY reg and convert again from scratch. + +-------------------------------------------------------------------------------------------- +<05/30/2012 17:05 Alexchou> +Modified Files: +Change Notes: + + rtl8812a/FW/RTL8812FW_Test_T.BIN + rtl8812a/HalHWImg8812A_TestChip_FW.c + 1. update 8812 testchip fw v0002 + +Verification Before Checked-In: + 1. None +-------------------------------------------------------------------------------------------- +<05/30/2012 15:05 MH_Chen> +Modified Files: +Change Notes: + 1. DESC relative code to fix PHY query status. + 2. ODM DIG MP abort case revise. + +Verification Before Checked-In: + 1. N5/N62 buildall. + 2. 88EU simple test ok. + +-------------------------------------------------------------------------------------------- +<05/30/2012 13:10 MH_Chen> +Modified Files: +Change Notes: + Remove MP relative cofr out of ODM folder. + +Verification Before Checked-In: + 1. N5/N62 buildall. + 2. 88EU ping ok. + +-------------------------------------------------------------------------------------------- +<05/29/2012 21:10 MH_Chen> +Modified Files: +Change Notes: + Windows Driver relative RXdesc resive + 1. ODM pHY status query must input raw data. + 2. Add GPL declaration for MP_Precomp.h + 3. Revise ODM data structure defintion. + +Verification Before Checked-In: + 1. N5/N62 buildall. + 2. 88EU ping ok. + +-------------------------------------------------------------------------------------------- +<05/29/2012 17:00 Alexchou> +Modified Files: +Change Notes: + rtl8195/ + 1. deleted rtl8195 folder + + rtl8812a/ + rtl8812a/BB/ + rtl8812a/FW/ + rtl8812a/FW/RTL8812FW_Test_T.BIN + rtl8812a/HalHWImg8812A_TestChip_FW.c + rtl8812a/HalHWImg8812A_TestChip_FW.h + rtl8812a/MAC/ + rtl8812a/RF/ + + 1. Create rtl8812a relative folders. + 2. update 8812 testchip fw v0001 + +Verification Before Checked-In: + 1. None +-------------------------------------------------------------------------------------------- +<05/23/2012 17:28 MH_Chen> +Modified Files: +Change Notes: + ODM relative file. + 1. Add MP driver MP_Precomp.h to increase compile speed. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 92CU/92DU/8723AU/88EU simple test ok. + +-------------------------------------------------------------------------------------------- +<05/23/2012 14:54 MH_Chen> +Modified Files: +Change Notes: + HAL\DESC\Hal8192CRxDesc.c + 1. Fix ODM PHY & packet info strcucture for 92C &8812 seies. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 92CU simple test ok. + +-------------------------------------------------------------------------------------------- +<05/22/2012 22:40 MH_Chen> +Modified Files: +Change Notes: + HAL\DESC\Hal8188ERxDesc.c + HAL\DESC\Hal8812Desc.c + HAL\OUTSRC\odm_HWConfig.c + 1. Revise ODM PHY & packet info strcucture to fix 88E serries PHy query. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88EU simple test ok. + +-------------------------------------------------------------------------------------------- +<05/17/2012 19:40 Georgia> +Modified Files: + HalPhyRf.h + odm.c + odm.h + odm_debug.h + odm_HWConfig.c + odm_HWConfig.h + odm_interface.h + odm_precomp.h + odm_reg.h + odm_RegDefine11AC.h + odm_RegDefine11N.h + odm_types.h + +Change Notes: + 1. Prevent from "warning: no newline at end of file" + 2. Fix comile error for CE Platform + +Verification Before Checked-In: + 1. Make all ok. + 2. 88EU auto-test ok. + +-------------------------------------------------------------------------------------------- +<05/17/2012 11:40 LukeLee> +Modified Files: + odm.c + \rtl8188e\odm_RTL8188E.c + \rtl8192c\odm_RTL8192C.c + \rtl8192d\odm_RTL8192D.c + +Change Notes: + 1. Add IC comile flag for each IC subfolder + 2. revise ODM_DMInit() and ODM_DMWatchdog() + 3. Remove ODM_RF_Saving_8188E() + +Verification Before Checked-In: + 1. N62 buildall OK + 2. set RTL8192C_SUPPORT/ RTL8192D_SUPPORT/ RTL8188E_SUPPORT to 0 buildall OK + +-------------------------------------------------------------------------------------------- +<05/16/2012 23:55 LukeLee> +Modified Files: + odm.c + +Change Notes: + 1. Revise AntDivType Init + +Verification Before Checked-In: + 1. None + +-------------------------------------------------------------------------------------------- +<05/16/2012 23:10 LukeLee> +Modified Files: + odm_HWConfig.c + odm_types.h + odm.c + odm.h + rtl8188e\odm_RTL8188E.c + rtl8188e\odm_RTL8188E.h + +Change Notes: + 1. Add compile flag for SW and HW antenna diveristy + +Verification Before Checked-In: + 1. N62 buildall OK + 2. 88EU, 88CE TP test OK + +-------------------------------------------------------------------------------------------- +<05/16/2012 16:25 LukeLee> +Modified Files: + odm_HWConfig.c + odm.c + odm.h + rtl8188e\HalPhyRf_8188e.c + rtl8188e\odm_RTL8188E.c + +Change Notes: + 1. Fix comile error + 2. Merge HW AntDiv for all platform + 3. Disable ODM_SwAntDivCheckBeforeLink8192C() + +Verification Before Checked-In: + 1. 88CE vs DIR855 TX:94Mbps RX:92Mbps + 2. 88EU vs DIR855 TX:83Mbps RX:95Mbps + +-------------------------------------------------------------------------------------------- +<05/14/2012 11:21 button> +Modified Files: + odm_precomp.h + odm.c + odm.h + HalPhyRf.c + rtl8188e/Hal8188ERateAdaptive.c + rtl8188e/HalPhyRf_8188e.c + rtl8188e/HalPhyRf_8188e.h + +Change Notes: + 1. Support power tracking in AP platform + 2. Refine RA threshold for AP + 3. Fix STA array number + +Verification Before Checked-In: + 1. AP buildall OK. + +-------------------------------------------------------------------------------------------- +<05/12/2012 12:30 LukeLee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\rtl8188e\odm_RTL8188E.c + HAL\OUTSRC\rtl8188e\odm_RTL8188E.h + HAL\OUTSRC\odm_HWConfig.c + HAL\OUTSRC\odm_RegDefine11N.h + HAL\DESC\Hal8188EETxDesc.c + HAL\DESC\Hal8188EUsbTxDesc.c + HAL\DESC\Hal8188ESdioTxDesc.c + +Change Notes: + 1. [88E]Enable CCK AntDiv and fix some AntDiv bugs + +Verification Before Checked-In: + 1. N62 buildall OK. + 2. 88EE DL:53Mbps UL:49Mbps 88EU DL:51Mbps UL:47Mbps + +-------------------------------------------------------------------------------------------- +<05/10/2012 16:00 MH_Chen> +New Files: +Modified Files: +Change Notes: + 1. Merge from MP driver V2680 to V2685. + +Verification Before Checked-In: + 1. N5/N62 buildall OK. + 2. 88EU ping ok S3/S4/reload/unplug ok. + +-------------------------------------------------------------------------------------------- +<05/08/2012 23:00 MH_Chen> +New Files: +Modified Files: +Change Notes: + 1. Merge from MP driver V2560 to V2671. Many modification hard to describe.~~!! Please refer + to MP driver lable v2560-2671. + +Verification Before Checked-In: + 1. N5/N6/N62 buildall OK. + 2. 88EU ping ok S3/S4/reload/unplug ok. + +-------------------------------------------------------------------------------------------- +<05/08/2012 16:55 LukeLee> +Modified Files: + HAL\OUTSRC\odm_HWConfig.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + +Change Notes: + 1. remove compile error + 2. [88E] Update MAC_PHY_REG V030 for change RX default ant to CG + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------------------- +<05/07/2012 14:05 Kordan> +Modified Files: + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/odm_types.h + +Change Notes: + 1. Add two definitions in RT_SPINLOCK_TYPE. + 2. [88E] Support PHY_REG_MP.txt configuration.(But disabled now) + +Verification Before Checked-In: + 1. None + +-------------------------------------------------------------------------------------------- +<05/07/2012 11:40 LukeLee> +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.h + +Removed Files: + HAL\OUTSRC\rtl8188e\BB\PHY_REG_MP.txt + +Change Notes: + 1. [88E]Update right MAC_PHY_REG V029 (remove PHY_REG_MP.txt) + +Verification Before Checked-In: + 1. N62 buildall OK + +-------------------------------------------------------------------------------------------- +<05/07/2012 11:20 LukeLee> +New Files: + HAL\OUTSRC\rtl8188e\BB\PHY_REG_PG.txt + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.h + +Change Notes: + 1. [88E]Update MAC_PHY_REG V029 for power by rate + +Verification Before Checked-In: + 1. 88EE RX:99Mbps, TX:83.5Mbps + +-------------------------------------------------------------------------------------------- +<05/03/2012 21:15 LukeLee> +New Files: + HEADER\RegCommon.h + +Change Notes: + 1. [88E]Modify registry AntennaDivType + +Verification Before Checked-In: + 1. 88EE RX:98Mbps, TX:84Mbps + 2. 88EE antenna diversity enable OK + +-------------------------------------------------------------------------------------------- +<05/03/2012 17:00 LukeLee> +New Files: + HAL\OUTSRC\odm_RegDefine11AC.h + HAL\OUTSRC\odm_RegDefine11N.h + +Change Notes: + 1. fix compile error + +Verification Before Checked-In: + 1. None + +-------------------------------------------------------------------------------------------- +<05/03/2012 16:00 LukeLee> +New Files: +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\odm_interface.h + HAL\OUTSRC\odm_precomp.h + HAL\OUTSRC\rtl8188e\odm_RTL8188E.c + HAL\HalDM.c +New Files: + HAL\OUTSRC\odm_RegDefine11AC.h + HAL\OUTSRC\odm_RegDefine11N.h + +Change Notes: + 1. [8812] Reg Define and DIG modified + 2. restrict dynamic functions for 11AC series + 3. Add SupportICtype ODM_RTL8812 + 4. enable odm_DynamicEDCCA() for all 11N series + +Verification Before Checked-In: + 1. Buildall OK + 2. 88EU DL=94Mbps, UL=78Mbps, ODM v285 has the same issue! +-------------------------------------------------------------------------------------------- +<05/03/2012 11:00 JueYang> +New Files: +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + +Change Notes: + 1. Revise CCK PowerByRate. + +Verification Before Checked-In: + 1. OFDM and CCK PowerByRate OK. +-------------------------------------------------------------------------------------------- +<04/28/2012 12:00 JueYang> +New Files: + HAL\OUTSRC\rtl8188e\BB\PHY_REG_PG.txt + +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.h + HAL\OUTSRC\rtl8188e\HalHWImg8188E_TestChip_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_TestChip_BB.h + HAL\OUTSRC\rtl8188e\odm_RegConfig8188E.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\odm_HWConfig.c + HAL\PHY\Hal8188EPhyCfg.c + HAL\PHY\HalComPhyCfg.c + HAL\PHY\HalComPhyCfg.h + + HAL\rtl8188E\rtl8188ee\Hal8188EEGen.c +Change Notes: + HAL\OUTSRC\rtl8188e\BB\PHY_REG_PG.txt + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.h + HAL\OUTSRC\rtl8188e\HalHWImg8188E_TestChip_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_TestChip_BB.h + HAL\OUTSRC\rtl8188e\odm_RegConfig8188E.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\odm_HWConfig.c + HAL\PHY\Hal8188EPhyCfg.c + HAL\PHY\HalComPhyCfg.c + HAL\PHY\HalComPhyCfg.h + 1. Add PowerByRate and update PHY_REG_PG to V003. + + HAL\rtl8188E\rtl8188ee\Hal8188EEGen.c + 1. Fix some bugs. + + +Verification Before Checked-In: + 1. N62 Buildall ok +-------------------------------------------------------------------------------------------- +<04/27/2012 19:25 Georgia> +New Files: +Modified Files: + odm.c + odm.h + odm_debug.c + odm_debug.h + odm_interface.c + odm_precomp.h + odm_types.h + rtl8188e/HalPhyRf_8188e.c + rtl8188e/odm_RTL8188E.c + rtl8188e/odm_RTL8188E.h + rtl8192c/odm_RTL8192C.c + +Change Notes: + 1. Remove CE compile error + +Verification Before Checked-In: + 1. Make all ok. + 2. 88EU auto-test ok. + +-------------------------------------------------------------------------------------------- +<04/27/2012 17:33 MH_Chen> +New Files: +Modified Files: +Change Notes: + HAL\OUTSRC\rtl8188e\HalPhyRf_8188e.c/h + 1. Revise TX power tracking mechanism. Prevent BB swing fail. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. WIN7 88EU ping /reload/ unplug/ S3 ok. + +-------------------------------------------------------------------------------------------- +<04/25/2012 20:00 LukeLee> +New Files: +Modified Files: + rtl8188e/odm_RTL8188E.c +Change Notes: + 1. Remove MP compile error + +Verification Before Checked-In: + 1. MP buildall OK + +-------------------------------------------------------------------------------------------- +<04/25/2012 17:20 button> +New Files: +Modified Files: + odm.c + rtl8188e/odm_RTL8188E.c +Change Notes: + 1. Refine AP's EDCA turbo function + 2. Resolve AP's compile error + +Verification Before Checked-In: + 1. AP platform build OK(88E) + +-------------------------------------------------------------------------------------------- +<04/23/2012 21:55 LukeLee> +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + +Change Notes: + 1. [88E] Update MAC_PHY_REG V028 for 20M mode noise resistence + +Verification Before Checked-In: + 1. 88E Static Analysis OK + +-------------------------------------------------------------------------------------------- +<04/13/2012 23:00 MH_Chen> +New Files: +Modified Files: +Change Notes: + 1. Merge from MP driver V2471 to V2561. Mant modification hard to describe.~~!! + +Verification Before Checked-In: + 1. N5/N62 buildall OK. + 2. 88EU/92CU ping ok S3/S4/reload/unplug ok. + +--------------------------------------------------------------------------------------------- +<04/13/2012 20:10 LukeLee> +New Files: + HAL\HalDM.c + +Modified Files: +Change Notes: + 1. [8812]enable RSSI Monitor + +Verification Before Checked-In: + 1. buildall OK + +--------------------------------------------------------------------------------------------- +<04/13/2012 19:55 LukeLee> +New Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm_HWConfig.c + HAL\HalDM.c + +Modified Files: +Change Notes: + 1. [8812]enable DIG only + 2. [8812]CCK RSSI format as 88E + +Verification Before Checked-In: + 1. buildall OK + +--------------------------------------------------------------------------------------------- +<04/13/2012 16:38 Gimmy> +New Files: + HAL\OUTSRC\rtl8188e\FW +Modified Files: +Change Notes: + 1. Update first version 88E formal firmware. V001. + +Verification Before Checked-In: + 1. NONE. + 2. ImgTransfer ok. + +--------------------------------------------------------------------------------------------- +<04/12/2012 22:30 LukeLee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\rtl8188e\odm_RTL8188E.c + HAL\OUTSRC\rtl8188e\odm_RTL8188E.h + HAL\BTCoexist\HalBtCoexist.c + +Change Notes: + 1.[All IC except 8723A]Modify DIG + 2.[88E] Modify AntDiv + +Verification Before Checked-In: + 1. buildall ok. + 2. 88EE test OK + +--------------------------------------------------------------------------------------------- +<04/12/2012 12:00 LukeLee> +Modified Files: + PLATFORM\NDIS5\N5C_Init.c + PLATFORM\NDIS5\Ndis5Common.h + PLATFORM\NDIS6\N6C_Init.c + PLATFORM\NDIS6\Ndis6Common.h + HAL\EFUSE\Hal8188EEfuse.c + +Change Notes: + 1.[88E]Fix AntDiv type decision in init flow + + +Verification Before Checked-In: + 1. buildall ok. + 2. 88EE test OK + +--------------------------------------------------------------------------------------------- + +<04/12/2012 10:28 Mingzhi> +Modified Files: + \HEADER\Typedef.c + HAL\OUTSRC\odm.c + +Change Notes: + 1.modify definition wireless mode for mp platform + 2.fix a bug in AP/ADSL: choose_iot_main_sta() + +Verification Before Checked-In: + 1.MP platform buildall ok + 2.92du ping ok + +--------------------------------------------------------------------------------------------- +<04/11/2012 10:20 JueYang> +Modified Files: + HAL\OUTSRC\rtl8188e\HalPhyRf_8188e.c + + HAL\OUTSRC\odm.c + +Change Notes: + HAL\OUTSRC\rtl8188e\HalPhyRf_8188e.c + 1. [88E] Fix BOSD. + + HAL\OUTSRC\odm.c + 1. [88E] Add break. + +Verification Before Checked-In: + 1. buildall ok. + +--------------------------------------------------------------------------------------------- +<04/06/2012 18:20 Luke.Lee> +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + +Change Notes: + 1. [88E] Update MAC_PHY_REG V026 + +Verification Before Checked-In: + 1. 88EU TP dynamic rage test OK + +--------------------------------------------------------------------------------------------- +<04/03/2012 10:20 Kordan> +Modified Files: + HEADER/Precomp.h.Wlan*.Windows + PLATFORM/WinInf/*/rtwlan*mp.inf + PLATFORM/WinInf/*/netrtwlan*.inf + PLATFORM/NDIS5/USB/INF/rtwlanump.inf + PLATFORM/NDIS5/PCI/INF/rtwlanemp.inf + HEADER/RegCommon.h + PLATFORM/NDIS5/N5C_Init.c + HAL/EFUSE/Hal8188EEfuse.c + +Change Notes: + 1. Change the default setting of AntennaDivType to "AUTO". + 2. Ignore 0xC1[3] when 0xC9 is "1" or "2". + +Verification Before Checked-In: + 1. MP buildall ok. + +--------------------------------------------------------------------------------------------- +<04/02/2012 20:50 Luke.Lee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\rtl8188e\odm_RTL8188E.c + +Change Notes: + 1. [88E] remove DbgPrint in odm_RTL8188E.c + 2. [88C] modify ODM_SingleDualAntennaDetection() + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88CE TP test OK + +--------------------------------------------------------------------------------------------- +<04/02/2012 15:50 Kordan> +Added Files: + PLATFORM/WinInf/SDIO + PLATFORM/WinInf/SDIO/netrtwlans.inf + PLATFORM/WinInf/SDIO/rtwlansmp.inf + +Deleted Files: + HEADER/Precomp.h.WlanES.Windows + HEADER/Precomp.h.WlanS.Windows.MP + HEADER/Precomp.h.WlanES.Windows.MP + +Modified Files: + HEADER/Precomp.h.Wlan*.Windows + PLATFORM/WinInf/*/rtwlan*mp.inf + PLATFORM/WinInf/*/netrtwlan*.inf + PLATFORM/NDIS5/USB/INF/rtwlanump.inf + PLATFORM/NDIS5/PCI/INF/rtwlanemp.inf + HEADER/RegCommon.h + PLATFORM/NDIS5/N5C_Init.c + HAL/OUTSRC/rtl8188e/odm_RTL8188E.c + HAL/EFUSE/Hal8188EEfuse.c + MPBuild.bat + +Change Notes: + 1. Add an option AUTO in advanced setting. (When AUTO is not selected, EFUSE setting would be ignored.) + 2. Revise the registry setting and default value of Antenna diversity. + 3. Fix compilation errors. + +Verification Before Checked-In: + 1. N5/N62/MP buildall ok. + 2. 88EE MP T/Rx OK. + +--------------------------------------------------------------------------------------------- +<03/29/2012 21:05 Luke.Lee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\odm_HWConfig.c + HAL\OUTSRC\rtl8188e\odm_RTL8188E.c + HAL\OUTSRC\rtl8188e\odm_RTL8188E.h + +Change Notes: + 1. [88E]Modify Antenna Diversity + ODM_SetTxAntByAntDiv() needs to be executed in TXDESC in each platform + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88EE TP test OK + +--------------------------------------------------------------------------------------------- +<03/27/2012 23:05 MH_Chen> +Modified Files: +Change Notes: + 1. Merge from MP driver V2467 to V2470 to support 8821AU and fix some problem. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 882EU ping ok. + +--------------------------------------------------------------------------------------------- +<03/27/2012 22:10 Luke.Lee> +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + +Change Notes: + 1. [88E] Update MAC_PHY_REG V025 + +Verification Before Checked-In: + 1. None + +--------------------------------------------------------------------------------------------- +<03/26/2012 20:15 Luke.Lee> +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + +Change Notes: + 1. [88E] Update MAC_PHY_REG V024 + +Verification Before Checked-In: + 1. Power training is verified by Wilson + +--------------------------------------------------------------------------------------------- +<03/21/2012 11:50 Kordan> +Modified Files: + HAL/OUTSRC/odm_HWConfig.c + HAL/rtl8188E/Hal8188ECom.c + PLATFORM/NDIS5/SDIO/sdio_main.c + MPBuild.bat + +Change Notes: + 1. Fix wrong MACRO definition: READ_AND_CONFIG + 2. Minor changes for MP driver. + +Verification Before Checked-In: + 1. N5/N62/MP buildall OK. + +--------------------------------------------------------------------------------------------- +<03/19/2012 11:20 Luke.Lee> +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + +Change Notes: + 1. Update MAC_PHY Reg V023 + +Verification Before Checked-In: + 1. None + +--------------------------------------------------------------------------------------------- +<03/15/2012 15:30 Kordan> +Modified Files: +Change Notes: + HAL/EFUSE/Hal8188EEfuse.c + HAL/HalDM.c + HAL/HalPci.h + HAL/HalPG.h + HAL/HalSdio.h + HAL/HalUsb.h + HAL/MPT/MPT_HelperFunc.h + HAL/MPT/MPT_Phy.c + HAL/MPT/MPT_Phy.h + HAL/MPT/MPT_Req.c + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_precomp.h + HAL/OUTSRC/rtl8188e/Hal8188EReg.h + HAL/OUTSRC/rtl8188e/odm_RTL8188E.c + HAL/rtl8188E/Hal8188EReg.h + HEADER/CustomOid.h + HEADER/MassProductionDef.h + HEADER/PrecompInc.h + HEADER/RegCommon.h + HEADER/TypeDef.h + + 1. [8188E] Read antenna diversity type (0xC9 in EFUSE) into TRxAntDivType. + 2. [8188E] New OIDs to Set/Query the antenna diversity type. + 3. odm_FastAntTrainingInit for MP driver. + + PLATFORM/MACOSX/PMC_Init.cpp + PLATFORM/NDIS5/N5C_Init.c + PLATFORM/NDIS5/Ndis5Common.h + PLATFORM/NDIS5/PCI/INF/rtwlanemp.inf + PLATFORM/NDIS5/SDIO/INF/netrtwlans.inf + PLATFORM/NDIS5/SDIO/INF/rtwlansmp.inf + PLATFORM/NDIS5/USB/INF/rtwlanump.inf + PLATFORM/NDIS6/Ndis6Common.h + PLATFORM/WinInf/PCI/netrtwlane.inf + PLATFORM/WinInf/PCI/rtwlanemp.inf + PLATFORM/WinInf/USB/netrtwlanu.inf + PLATFORM/WinInf/USB/rtwlanump.inf + + 4. New TRxAntDivType setting in the advance property page of the device manager. + +Verification Before Checked-In: + 1. N5/N62/MP buildall OK. + 2. MP T/Rx OK. + +--------------------------------------------------------------------------------------------- +<03/13/2012 17:40 Luke.Lee> +Modified Files: + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_RF.c + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + HAL\OUTSRC\rtl8188e\RF\RadioA_1T.txt + +Change Notes: + 1. Update MAC_PHY Reg V022 + +Verification Before Checked-In: + 1. 88EE shielding room TP test OK + +--------------------------------------------------------------------------------------------- +<03/12/2012 13:40 Kordan> +Modified Files: + HAL/OUTSRC/Image2Header.exe + +Change Notes: + 1. Bug fixed: wrong output array name of MP chip. + +Verification Before Checked-In: + 1. None + +--------------------------------------------------------------------------------------------- +<03/09/2012 21:45 Kordan> +Modified Files: + HAL/EFUSE/Hal8188EEfuse.c + HAL/HalComReg.h + HAL/HalDM.c + HAL/HalPci.h + HAL/HalSdio.h + HAL/HalUsb.h + HAL/OUTSRC/Image2Header.exe + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/odm_precomp.h + HAL/OUTSRC/OutputHWImg.bat + HAL/OUTSRC/rtl8188e/HalHWImg8188E_*.* + HAL/rtl8188E/Hal8188ECom.c + HAL/rtl8188E/Hal8188EFirmware.c + HAL/rtl8188E/rtl8188ee/Hal8188EEDef.h + HAL/rtl8188E/rtl8188ee/Hal8188EEGen.c + HAL/rtl8188E/rtl8188es/Hal8188ESdioDef.h + HAL/rtl8188E/rtl8188eu/Hal8188EUsbDef.h + HAL/rtl8188E/rtl8188eu/Hal8188EUsbGen.c + HAL/rtl8188E/rtl8188eu/Hal8812AUsbGen.c + HAL/sources.* + HEADER/HalDef.h + HEADER/Precomp.h.WlanE.Windows + +Change Notes: + 1. Support 8188E runtime configuration of MP chip and Test chip. (determined by "bIsMPChip" variable) + a. This feature is now only enabled in 8188EE. + b. You can #define RTL8188E_FOR_TEST_CHIP 2 to supprt both MP and test chip. + c. Also, #define RTL8188E_FOR_TEST_CHIP 0/1 could reduce the code size. + +Verification Before Checked-In: + 1. N5/N62/MP buildall OK. + +--------------------------------------------------------------------------------------------- +<03/08/2012 21:21 button> +Modified Files: + odm_precomp.h + odm_debug.h + odm.c + odm.h + rtl8188e/Hal8188ERateAdaptive.c +Change Notes: + 1. Resolve compile error in AP platform. +Verification Before Checked-In: + 1. AP platform compile OK. + +--------------------------------------------------------------------------------------------- +<03/08/2012 21:10 Kordan> +Modified Files: + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.c + HEADER/Precomp.h.WlanE.Windows + HEADER/Precomp.h.WlanU.Windows + +Change Notes: + 1. Fix switch channel bug which causes OS hung. + 2. Set TEST_CHIP flag to 0. + 3. Fix MP compilation error. + +Verification Before Checked-In: + 1. N5/N62 buildall OK. + +--------------------------------------------------------------------------------------------- +<03/05/2012 16:10 Luke.Lee> +Modified Files: + HAL/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c + HAL/OUTSRC/rtl8188e/HalHWImg8188E_RF.c + HAL/OUTSRC/rtl8188e/MAC/MAC_REG.txt + HAL/OUTSRC/rtl8188e/RF/RadioA_1T.txt + +Added Files: + HAL/OUTSRC/rtl8188e/HalHWImg8188E_MAC_testchip.c/h + HAL/OUTSRC/rtl8188e/HalHWImg8188E_BB_testchip.c/h + HAL/OUTSRC/rtl8188e/HalHWImg8188E_RF_testchip.c/h + +Change Notes: + 1. Update RTL8188E_MAC_PHY_ForMPChip_v021.zip + 2. Rename original MAC/BB/RF files as testchip files + +Verification Before Checked-In: + 2. 8188ES test OK. + +--------------------------------------------------------------------------------------------- +<03/02/2012 19:00 Kordan> +Modified Files: +COMMON/Debug.c + HAL/OUTSRC/Image2Header.exe + HAL/OUTSRC/rtl8188e/*.c + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.c + HAL/OUTSRC/rtl8188e/RF/RadioA_1T.txt + +Change Notes: + 1. Update HWIMG headers and Image2Header to handle if-else case. + 2. Turn off RATE_ADAPTIVE_SUPPORT for MP driver. + +Verification Before Checked-In: + 1. N5/N62 buildall OK. + 2. 8188EE ping OK. +--------------------------------------------------------------------------------------------- +<03/02/2012 17:30 Luke.Lee> +Modified Files: + odm.c + odm.h + \rtl8188e\odm_RTL8188E.c + \rtl8188e\odm_RTL8188E.h + +Change Notes: + 1. Simplify timer callback of fast antenna training + +Verification Before Checked-In: + 1. N5/N62 buildall OK + 2. 88EE hang in Win7 from label v234 + 3. 88EU workitem does not work if it is started by timer in WatchDog + +--------------------------------------------------------------------------------------------- +<02/29/2012 19:40 Georgia> +Modified Files: + odm.c + rtl8188e/Hal8188ERateAdaptive.c + rtl8723a/Hal8723UHWImg_CE.c + rtl8723a/Hal8723UHWImg_CE.h + +Change Notes: + 1. Fix incorrect data type usage in func:ODM_RAInfo_Init_all. + 2. Fix compile error for CE Platform. + +Verification Before Checked-In: + 1. Make all ok. + 2. RTL8723A-VAL auto-test ok. + 3. RTL8189E auto-test ok. +--------------------------------------------------------------------------------------------- +<02/24/2012 18:30 Georgia> +Modified Files: + HalPhyRf.c + HalPhyRf.h + odm.c + odm.h + odm_interface.h + odm_precomp.h + rtl8188e/Hal8188ERateAdaptive.c + rtl8188e/Hal8188ERateAdaptive.h + rtl8188e/HalPhyRf_8188e.c + rtl8188e/HalPhyRf_8188e.h + rtl8188e/odm_RTL8188E.c + +Change Notes: + 1. Fix compile error for CE platform. + 2. Add GPL announce. + 3. Remove useless codes. + +Verification Before Checked-In: + 1. Make all ok. + 2. RTL8723A-VAL auto-test ok. + 3. RTL8189E auto-test ok. + +--------------------------------------------------------------------------------------------- +<02/23/2012 17:10 Kordan> +Modified Files: + HAL\OUTSRC\rtl8188e\HalPhyRf_8188e.c +Change Notes: + 1. Update IQK setting and flow. + +Verification Before Checked-In: + 1. None + +--------------------------------------------------------------------------------------------- +<02/23/2012 22:50 MH_Chen> +Modified Files: +Change Notes: + HAL\OUTSRC\odm.c\h + 1. Revise CCK path diversity timer and workitem architecture. + 2. ResetAllHw timer and cancel Hw timer will call ODM relative API.. + +Verification Before Checked-In: + 1. N5/N62 buildall OK + 2. 92CU WIN7 S3/S4/S5 reload/unplug ok. + +--------------------------------------------------------------------------------------------- +<02/23/2012 21:35 MH_Chen> +Modified Files: +Change Notes: + HAL\OUTSRC\odm.c\h + 1. Revise path diversity timer and workitem architecture. + 2. Deleate HAL layer ODM path diversity timer and workitem declaation. + +Verification Before Checked-In: + 1. N5/N62 buildall OK + 2. 92CU WIN7 S3/S4/S5 reload/unplug ok. + +--------------------------------------------------------------------------------------------- +<02/23/2012 20:35 MH_Chen> +Modified Files: +Change Notes: + HAL\OUTSRC\odm.c\h + 1. Revise all ODM timer/workitem init/cancel.release flow. + 2. Add cancel timer API to prevent BSOD and system resource leakage. + 3. Fix unplug fail issue. + +Verification Before Checked-In: + 1. N5/N62 buildall OK + 2. 92CU WIN7 S3/S4/S5 reload/unplug ok. + 3. A special flow bug fixed ==> S3/S4 and then disable or unplug OK in NB111_WIN7. + +--------------------------------------------------------------------------------------------- +<02/22/2012 16:35 MH_Chen> +Modified Files: +Change Notes: + HAL\OUTSRC\odm.c\h + 1. Merge from MP 2444 to 2459. + 2. Some odm code is moved from MP to ODM code base. + +Verification Before Checked-In: + 1. N5/N62 buildall OK + 2. 92CU WIN7 S3/S4/S5 reload/unplug ok. + 3. A special under investigation ==> S3/S4 and then disable or unplug fail. And then + cause all USB port detection fail in QC NB111. + +--------------------------------------------------------------------------------------------- +<02/22/2012 15:35 Kordan> +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.c + +Change Notes: + 1. Revise PHY_ResetIQKResult to ODM format, ODM_ResetIQKResult. + 2. Move TxPowerTrackControl initialization to odm_TXPowerTrackingThermalMeterInit. + +Verification Before Checked-In: + 1. N5/N62 buildall OK +--------------------------------------------------------------------------------------------- +<02/21/2012 23:10 Kordan> +Modified Files: + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.c + +Change Notes: + 1. Merge TxPower Tracking from trunk to ODM. + 2. Replace EOF pattern, 0xFF, of ParaFiles with 0xFFFF. + +Verification Before Checked-In: + 1. N5/N62 buildall OK + +--------------------------------------------------------------------------------------------- +<02/21/2012 14:45 button> +Modified Files: + odm_precomp.h + odm.c + odm.h + rtl8192c/HalDMOutSrc8192C_AP.c + rtl8188e/odm_RTL8188E.c + rtl8188e/odm_RTL8188E.h + rtl8188e/Hal8188ERateAdaptive.h + rtl8188e/Hal8188ERateAdaptive.c +Change Notes: + 1. Resolve compile error in AP platform. + 2. In AP's IOT engine, search all connected STA, not only root + interface + 3. Sync 92C dynamic mechanism with trunk +Verification Before Checked-In: + 1. AP platform make OK. + 2. 96e+88e ping ok + +--------------------------------------------------------------------------------------------- +<02/19/2012 10:29 Annie> +Modified Files: + +Change Notes: + 1. Fix compile error in ADSL platform. + 2. Correct SNR info. + 3. Add ODM_InitAllTimers interface. + 4. Add ODM_CompareMemory interface. + +Verification Before Checked-In: + 1. ADSL platform make OK. + 2. Ping 65500 OK. + +--------------------------------------------------------------------------------------------- +<02/17/2012 18:05 Kordan> +Modified Files: + HAL/OUTSRC/rtl8188e/HalPhyRf_8188e.c + +Change Notes: + 1. When delta temperature is equal to or larger than 20 centigrade(index delta is about 8), + do IQK and LCK. + 2. Update last thermal value to prevent from running IQK and LCK every time. + +Verification Before Checked-In: + 1. N5/N62 buildall OK + +--------------------------------------------------------------------------------------------- +<02/17/2012 16:45 Luke.Lee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + +Change Notes: + 1. Remove SW AntDiv timer and callback from orignal MP platform + 2. Add init and free all workitems for MP platform + +Verification Before Checked-In: + 1. N5/N62 buildall OK + 2. 88EE web brouse OK + +--------------------------------------------------------------------------------------------- +<02/17/2012 14:18 MH_Chen> +Modified Files: +Change Notes: + 1. Add workitem relative API. Not enabled now, so we need not test. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/16/2012 22:30 LukeLee> +Modified Files: + HAL\OUTSRC\rtl8188e\odm_RTL8188E.c + +Change Notes: + 1. [8188E]Modify fast antenna training + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/16/2012 17:00 Mingzhi> +Modified Files: + HAL\OUTSRC\odm.c + +Change Notes: + 1. for CE platform, BE TXOP in B/G/BG/A mode is 0x5e(3ms) + 2. for AP/ADSL platform: fix a bug in BE TXOP + +Verification Before Checked-In: + 1. N5/N62 buildrtwu/buildrtwe ok. + +--------------------------------------------------------------------------------------------- +<02/16/2012 15:00 Luke.Lee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm_precomp.h + +New Files: + HAL\OUTSRC\rtl8188e\odm_RTL8188E.c + HAL\OUTSRC\rtl8188e\odm_RTL8188E.h + +Change Notes: + 1. [8188E]Move Fast antenna training into 88E folder + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/14/2012 23:12 MH_Chen> +Modified Files: +Change Notes: + 1. FIX ODM tracking list item 60. Revise ODM 88E rate adaptive ability support. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 8188EU ping test ok. + +--------------------------------------------------------------------------------------------- +<02/14/2012 22:12 MH_Chen> +Modified Files: +Change Notes: + 1. FIX ODM tracking list item 58. Revise ODM ability support. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 8188EU ping test ok. + +--------------------------------------------------------------------------------------------- +<02/14/2012 15:40 Georgia> +Modified Files: + odm.c + odm_debug.h + +Change Notes: + 1.Turn on EDCA Turbo function for BG mode (CE Platform) + +Verification Before Checked-In: + 1. CE Platform make ok. + 2. 8188E-SDIO auto-test ok. + +--------------------------------------------------------------------------------------------- +<02/13/2012 17:45 Luke.Lee> +Modified Files: + + HAL\OUTSRC\rtl8188e\MAC\MAC_REG.txt + HAL\OUTSRC\rtl8188e\HalHWImg8188E_MAC.c + +Change Notes: + + 1.Update RTL8188E_MAC_PHY_ForTestChip_v020 + +Verification Before Checked-In: + 1. None + +--------------------------------------------------------------------------------------------- +<02/13/2012 17:30 Luke.Lee> +Modified Files: + + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\odm_HWConfig.c + +Change Notes: + + 1.Modify fast antenna training (default disabled) + +Verification Before Checked-In: + 1. N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/10/2012 19:20 JueYang> +Modified Files: + COMMON\MgntLink.c + + HAL\DESC\Hal8188EETxDesc.c + + HAL\OUTSRC\rtl8188e\Hal8188ERateAdaptive.c + HAL\OUTSRC\rtl8188e\odm_RegConfig8188E.c + PLATFORM\NDIS6\N6C_OidSet.c + PLATFORM\NDIS6\N6C_Req.c + PLATFORM\NDIS6\Ndis_OID.c + + HAL\OUTSRC\odm.c + + HAL\rtl8188E\rtl8188ee\Hal8188EEGen.c + +Change Notes: + + COMMON\MgntLink.c + 1. Do MgntLinkRequest in function MgntLinkRetry even if JoinProbeRequestTimer cancel NG and SET flag is TRUE. + 2. Tune 3U Throughput for DIR 655. Reserved at least 2 packets in Tx FIFO to triggle early mode but avoid single AMPDU. + + HAL\DESC\Hal8188EETxDesc.c + 1. Fix DTM Fuzz BOSD for memory overflow when move memory for ealy mode dummy. Some codes are not covered by pHalData->bEarlyModeEnable. + + HAL\OUTSRC\rtl8188e\Hal8188ERateAdaptive.c + HAL\OUTSRC\rtl8188e\odm_RegConfig8188E.c + PLATFORM\NDIS6\N6C_OidSet.c + PLATFORM\NDIS6\N6C_Req.c + PLATFORM\NDIS6\Ndis_OID.c + 1. Just revise some traces. + + HAL\OUTSRC\odm.c + 1. Fix memory overwrite when update AsocEntry RA mask. The function odm_RefreshRateAdaptiveMaskMP tries to write MgntInfo.AsocEntry[ODM_ASSOCIATE_ENTRY_NUM-1]. + + HAL\rtl8188E\rtl8188ee\Hal8188EEGen.c + 1. Fix RX Hang after RF Off and RF On. Enable TRX DMA(REG[0x301]=0) during intialization. + +Verification Before Checked-In: + 1. N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/09/2012 22:41 MH_Chen> +Modified Files: +Change Notes: + MERGE MP V2435. + 1. Increase build speed and revise aarchitecture. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 1. 88EU reload/s3 ping ok. + +--------------------------------------------------------------------------------------------- +<02/09/2012 17:20 Kordan> +Modified Files: + HAL\OUTSRC\Image2Header.exe + +Change Notes: + 1. Fix wrong output values of Image2Header. + +Verification Before Checked-In: + 1. None. + +--------------------------------------------------------------------------------------------- +<02/08/2012 17:50 Luke.Lee> +Modified Files: + HAL\OUTSRC\rtl8188e\BB\PHY_REG_1T.txt + HAL\OUTSRC\rtl8188e\RF\RadioA_1T.txt + HAL\OUTSRC\rtl8188e\HalHWImg8188E_BB.c + HAL\OUTSRC\rtl8188e\HalHWImg8188E_RF.c + +Change Notes: + 1. Update MAC_PHY reg v019 + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88EE run chariot ok. + +--------------------------------------------------------------------------------------------- +<02/08/2012 17:20 Luke.Lee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm_HWConfig.c + +Change Notes: + 1. modify ODM_BB_ANT_DIV init in MP Platform + 2. [8188E] modify fast antenna training (default disabled) + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88EE run chariot ok. + +--------------------------------------------------------------------------------------------- +<02/07/2012 21:30 MH_Chen> +Modified Files: +Change Notes: + 1. Revise all batch file for MP. To fasten build speed. + 2. We do not request ODM to check buildrtwee/eu/es. The batch files will be removed later. + 3. Enable 92CU C2H timer for intel case. + 4. Prevent SDIO build error by modifying buildclean all. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88EU ping ok. + +--------------------------------------------------------------------------------------------- +<02/07/2012 21:10 Luke.Lee> +Modified Files: + HAL\OUTSRC\odm.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\odm_HWConfig.c + +Change Notes: + 1. [8188E] Modify fast antenna training (default disabled) + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/07/2012 13:35 JueYang> +Modified Files: + HAL\DESC\Hal8188EETxDesc.c + HAL\PHY\HalComPhyCfg.c + +Change Notes: + 1. [8188E] Revise Power Trainning. + +Verification Before Checked-In: + 1. N62 buildrtwe ok. + +--------------------------------------------------------------------------------------------- +<02/07/2012 11:05 JueYang> +Modified Files: + HAL\OUTSRC\rtl8188e\HalPhyRf_8188e.c + +Change Notes: + 1. [8188EE] Fix pbScanInProcess error which cause initialize 88ee delayed 3 seconds. + +Verification Before Checked-In: + 1. N62 buildrtwe ok. + +--------------------------------------------------------------------------------------------- +<02/06/2012 21:30 Luke.Lee> +Modified Files: + 1. rtl8188e/* + +Change Notes: + 1. [8188E] Update 88E MAC_PHY_REG v018 + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/06/2012 20:30 Luke.Lee> +Modified Files: + 1. rtl8188e/* + +Change Notes: + 1. [8188E] Update 88E MAC_PHY_REG v017 + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88EU vs Cisco1252 20M mode DL/UL:48Mbps + +--------------------------------------------------------------------------------------------- +<02/06/2012 13:30 Kordan> +Modified Files: + 1. Image2Header.exe + 2. rtl8723a/* + 3. rtl8188e/* + +Change Notes: + 1. Update Image2Header to remove the redundant code. + +Verification Before Checked-In: + 1. N5/N6/N62 buildall ok. + +--------------------------------------------------------------------------------------------- +<02/06/2012 11:24 MH_Chen> +New Files: +Delete FIles: +Modified Files: +Change Notes: + 1. MErge MP V2516 to fix TX short cut and SDIO build error. + +Verification Before Checked-In: + 1. N5/N6/N62 buildall ok. (Do not support buildrtwes in buildall now.) + 2. 88EU ping ok. + +--------------------------------------------------------------------------------------------- +<02/03/2012 18:20 Georgia> +New Files: +Delete FIles: +Modified Files: + rtl8188e/HalPhyRf_8188e.c + +Change Notes: + 1. Fix compile error for CE Platform. + +Verification Before Checked-In: + 1. CE Platform make ok. + 2. 8723AU auto-test ok. + 3. 8188E-SDIO auto-test ok. + +--------------------------------------------------------------------------------------------- +<02/03/2012 17:35 MH_Chen> +New Files: +Delete FIles: +Modified Files: +Change Notes: + 1. Revise 88E MAC init flow. + +Verification Before Checked-In: + 1. N6/N5 buildall OK. except sdio driver.. + 2. 92CU S3/S5/Reload/Unplug and ping WPA2-AES ok. + +--------------------------------------------------------------------------------------------- +<02/03/2012 14:30 MH_Chen> +New Files: +Delete FIles: +Modified Files: +Change Notes: + COMMON\ApEngine.c + COMMON\WOLPattern.c + 1. Support ODM for AP engine in MP. + 2. Fix SDIO compile error. + + HAL\BTCoexist\HalBtCoexist.c\h + HAL\DESC\Hal8192CRxDesc.c + HAL\HWIMG\HalHWImg.h + 1. Support ODM for BT in MP driver. + 2. IC support flag is moved to haldef.h. + HAL\OUTSRC\rtl8188e\Hal8188ERateAdaptive.c + HAL\OUTSRC\rtl8188e\HalPhyRf_8188e.c + 1. Fix MP compile error. + + HAL\PHY\Hal8188EPhyCfg.c\h + HAL\PHY\Hal8192CPhyCfg.c\h + HAL\PHY\Hal8192DPhyCfg.h + HAL\PHY\HalComPhyCfg.h + 1. Disable original RF calibraet power tracking mechanism in MP old drv. + 2. Georgia move some constant declare from MP old position to ODM. + + HEADER\... + 1. Define IC support flag. + 2. Revise precomp for SDIO build. + + Build batch files: + 1. Support MP all IC with ODM module. + 2. Support all SDIO driver build. + 3. Spport 8812E build. + +Verification Before Checked-In: + 1. N6/N5 buildall OK. We do not check EE/EU/ES sereis build batch file. + 2. 92CU S3/S5/Reload/Unplug and ping WPA2-AES ok. + +--------------------------------------------------------------------------------------------- +<02/03/2012 15:30 Georgia> +Change Notes: + 1. Add func:odm_RATxRPTTimerSetting,to prevent do IO frequently. + +Verification Before Checked-In: + 1. CE Platform make ok. + 2. 8723AU auto-test ok. + 3. 8188E-SDIO auto-test ok. +--------------------------------------------------------------------------------------------- +<02/03/2012 13:40 Georgia> +Change Notes: + 1. Fix compile error for CE Platform. + 2. add relative code for integrate RF Calibration.(add struct ODM_RF_CAL_T) + 3. integrate RA/Tx power training/RF calibration/tx power tracking for 8188ES + 4. Add interface: ODM_CompareMemory. + +Verification Before Checked-In: + 1. CE Platform make ok. + 2. 8723AU auto-test ok. + 3. 8188E-SDIO auto-test ok. +--------------------------------------------------------------------------------------------- +<02/02/2012 21:30 Luke.Lee> +Change Notes: + 1. Enable 88E Early Mode for all IOT peers + +Verification Before Checked-In: + 1. N62 buildall OK + 2. 88EU TP verfication OK +--------------------------------------------------------------------------------------------- +<02/02/2012 21:00 button> +Modified Files: + odm.h + odm.c + odm_HWConfig.h + odm_HWConfig.c + odm_interfac.c +Change Notes: + 1. AP's timer function + 2. AP's antenna diversity callback function + 3. AP's BB,MAC,RF config +Verification Before Checked-In: + 1. AP platform build ok. +--------------------------------------------------------------------------------------------- +<02/02/2012 17:45 JueYang> +Change Notes: + Hal8188EEHWImg.c + Hal8188EEHWImg.h + Hal8188EUHWImg.c + Hal8188EUHWImg.h + Hal8188ESHWImg.c + Hal8188ESHWImg.h + 1. Update 8188E HWImg header file. + +Verification Before Checked-In: + 1. N62 buildall OK +--------------------------------------------------------------------------------------------- +<02/02/2012 17:30 JueYang> +Change Notes: + Precomp.h.WlanU.Windows + usb_DrvIF.c + 1. [8188EU] Fix BSOD. + +Verification Before Checked-In: + 1. N62/N5 buildall OK + 2. 88EU test OK +--------------------------------------------------------------------------------------------- +<02/02/2012 11:20 LukeLee> +Change Notes: + 1. [8188EE/8188ES] InitHalDm should be put ahead of PHY_MACConfig(Adapter)! + 2. Fix compile error + +Verification Before Checked-In: + 1. N62/N5 buildall OK + 2. 88EE ping OK + +--------------------------------------------------------------------------------------------- +<02/01/2012 23:15 Kordan> +Change Notes: + 1. Remove inappropriate 8723_SUPPORT MACRO definition in Precomp.h. + +Verification Before Checked-In: + 1. none + +--------------------------------------------------------------------------------------------- +<02/01/2012 22:10 Kordan> +Change Notes: + 1. To avoid redefinition, function names are changed in odm_RegConfig8188E and odm_RegConfig8723A. + +Verification Before Checked-In: + 1. N62/N5 buildall OK + +--------------------------------------------------------------------------------------------- +<02/01/2012 21:10 LukeLee> +Change Notes: + 1. [8188EU] InitHalDm should be put ahead of PHY_MACConfig(Adapter)! + 2. [8188E] MAC/BB/RF Reg init flow by ODM + +Verification Before Checked-In: + 1. N62/N5 buildall OK + 2. 88EU ping OK + +--------------------------------------------------------------------------------------------- +<02/01/2012 18:10 Kordan> +Change Notes: + 1. Update Image2Header and upload the batch file to output hardware images. + 2. Rename the parameter filename to comply with Image2Heaeder's rule. + 2. [8188EU] InitHalDm should be put ahead of PHY_MACConfig(Adapter)! + +Verification Before Checked-In: + 1. None + +--------------------------------------------------------------------------------------------- +<02/01/2012 11:10 Kordan> +Change Notes: + 1. Add 8188E Hardware Images. + 2. Change the delay pattern, 0xfe, to 0xffe. (0xfe is a active register of 8188E) + +Verification Before Checked-In: + 1. None + +--------------------------------------------------------------------------------------------- +<01/31/2012 22:27 Annie> +Change Notes: + 1. Fix compile error in ADSL platform. + +Verification Before Checked-In: + 1. ADSL platform make OK. + 2. Ping FAIL. + +--------------------------------------------------------------------------------------------- +<01/31/2012 17:00 Luke.Lee> +Modified Files: +Change Notes: + 1. Fix 88EU TX DESC bug + 2. Add Fast Antenna Training Mechanism (default disabled) + 3. enable 88EU auto RTS + 4. Add control flag pAntDivCfg to SW AntDiv + +Verification Before Checked-In: + 1. N6/N5 buildall OK + 2. 92CU run TP OK but 88EU TP bad + +--------------------------------------------------------------------------------------------- +<01/31/2012 16:07 MH_Chen> +Modified Files: +Change Notes: + 1. Merge MP SDIO driver for ODM module test. Unti version 2412. + 2. Revise for MP common binary & ODM compatiable. + +Verification Before Checked-In: + 1. N5/N62 Buildall ok. + 2. 92CU win7 unplug/reload/S3/S5 ok. + +--------------------------------------------------------------------------------------------- +<01/30/2012 21:13 MH_Chen> +Modified Files: +Change Notes: + 1. Fix rtwlan SDIO source file for MP. + 2. Revise precomp header file and batch file for MP SDIO driver. + +Verification Before Checked-In: + 1. N5 Build SDIO driver ok. + +--------------------------------------------------------------------------------------------- +<01/30/2012 20:40 MH_Chen> +Modified Files: +Change Notes: + 1. Revise ODM phy rx desc query for MP. + 2. Revise precomp header file for USB. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. N5 Build 8723AS fail. + 2. 92CU test ok. Link with WPA2-AES AP. Unplug/reload/S3 ok. + +--------------------------------------------------------------------------------------------- +<01/29/2012 17:00 JueYang> +Modified Files: + HAL\OUTSRC\odm.c + + PLATFORM\NDIS6\USB\N6Usb_DrvIF.c + +Change Notes: + HAL\OUTSRC\odm.c + 1. Fix RA info not initialized. + + PLATFORM\NDIS6\USB\N6Usb_DrvIF.c + 1. Fix a mistake in writing which cause USB memory leak. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. 88EE\88CE\88CU test ok. +--------------------------------------------------------------------------------------------- +<01/29/2012 13:20 JueYang> +Modified Files: + COMMON\WOLPattern.c + HAL\rtl8188E\rtl8188eu\Hal8188EUsbGen.c + HAL\rtl8188E\Hal8188ECom.c + HAL\rtl8188E\Hal8812Com.c + HAL\rtl8192C\rtl8192ce\Hal8192CEGen.c + HAL\rtl8192C\rtl8192cu\Hal8192CUsbGen.c + HAL\rtl8192S\rtl8192se\Hal8192SEGen.c + HEADER\TypeDef.h + PLATFORM\NDIS5\PCI\Mp_Req.c + PLATFORM\NDIS5\USB\Mp_Req.c + PLATFORM\NDIS5\N5C_Init.c + PLATFORM\NDIS6\PCI\Mp_Req.c + PLATFORM\NDIS6\PCI\N6Pci_Main.c + PLATFORM\NDIS6\USB\Mp_Req.c + PLATFORM\NDIS6\USB\N6Usb_main.c + PLATFORM\NDIS6\N62C_SetOID.c + + HAL\EFUSE\Hal8192CEfuse.c + HAL\EFUSE\HalEfuse.h + HAL\OUTSRC\odm.c + HEADER\RegCommon.h + +Change Notes: + COMMON\WOLPattern.c + HAL\rtl8188E\rtl8188eu\Hal8188EUsbGen.c + HAL\rtl8188E\Hal8188ECom.c + HAL\rtl8188E\Hal8812Com.c + HAL\rtl8192C\rtl8192ce\Hal8192CEGen.c + HAL\rtl8192C\rtl8192cu\Hal8192CUsbGen.c + HAL\rtl8192S\rtl8192se\Hal8192SEGen.c + HEADER\TypeDef.h + PLATFORM\NDIS5\PCI\Mp_Req.c + PLATFORM\NDIS5\USB\Mp_Req.c + PLATFORM\NDIS5\N5C_Init.c + PLATFORM\NDIS6\PCI\Mp_Req.c + PLATFORM\NDIS6\PCI\N6Pci_Main.c + PLATFORM\NDIS6\USB\Mp_Req.c + PLATFORM\NDIS6\USB\N6Usb_main.c + PLATFORM\NDIS6\N62C_SetOID.c + 1. Use MAX_SUPPORT_WOL_PATTERN_NUM(Adapter) instead of MAX_SUPPORT_WOL_PATTERN_NUM. + + HAL\EFUSE\Hal8192CEfuse.c + HAL\EFUSE\HalEfuse.h + HAL\OUTSRC\odm.c + HEADER\RegCommon.h + 1. Remove HAL_SUPPORT_88E_92C. + +Verification Before Checked-In: + 1. N5/N62 buildall ok +--------------------------------------------------------------------------------------------- +<01/29/2012 11:20 JueYang> +Modified Files: + COMMON\MgntGen.c + COMMON\sources.Ebd + COMMON\sources.props + COMMON\sources.Win + COMMON\TDLSGen.c + COMMON\TransmitDesc.c + HAL\DESC\Hal8188EERxDesc.c + HAL\DESC\Hal8188EETxDesc.c + HAL\DESC\Hal8188ESdioRxDesc.c + HAL\DESC\Hal8188ESdioTxDesc.c + HAL\DESC\Hal8188EUsbRxDesc.c + HAL\DESC\Hal8188EUsbTxDesc.c + HAL\DESC\HalComRxDesc.c + HAL\DM\HalComDM.c + HAL\OUTSRC\Hal8188EDMOutSrc.c + HAL\OUTSRC\odm.h + HAL\OUTSRC\rtl8188e\Hal8188ERateAdaptive.h + HAL\OUTSRC\rtl8188e\Hal8188ERateAdaptive.c + HAL\rtl8188E\rtl8188ee\Hal8188EEGen.c + HAL\rtl8188E\rtl8188ee\Hal8812EGen.c + HAL\rtl8188E\rtl8188es\Hal8188ESdioGen.c + HAL\rtl8188E\rtl8188eu\Hal8188EUsbGen.c + HAL\rtl8188E\Hal8188ECom.c + HAL\rtl8192C\rtl8192ce\Hal8192CEGen.c + HAL\rtl8192C\rtl8192cs\Hal8192CSdioGen.c + HAL\rtl8192C\rtl8192cu\Hal8192CUsbGen.c + HAL\rtl8192S\rtl8192se\Hal8192SEGen.c + HAL\rtl8192S\rtl8192su\Hal8192SUsbGen.c + HAL\HAL.mk + HAL\HalCommon.c + HAL\HalDM.c + HAL\sources.WlanE + HAL\sources.WlanE.props + HAL\sources.WlanU.props + HAL\sources.WlanU.Win + HEADER\HalDef.h + Precomp.h.WlanE.Windows + HEADER\PrecompInc.h + HEADER\TypeDef.h + +Change Notes: + 1. Move RA from COMMON\ to HAL\OURSRC\RTL8188E. + 2. Support 88E and other chips when RATE_ADAPTIVE_SUPPORT=1. + +Verification Before Checked-In: + 1. N5/N62 buildall ok +---------------------------------------------------------------------------------------------- +<01/20/2012 19:07 MH_Chen> +Modified Files: +Change Note: + 1. Merge MP V 2401-2410. + +Verification Before Checked-IN + 1. N5/N6 buildall ok. + 2. 92CU win7 ping test ok. + +---------------------------------------------------------------------------------------------- +<01/19/2012 22:30 MH_Chen> +Modified Files: +Change Note: + 1. Support 8188E power tracking mechanism in odm folder for MP. + +Verification Before Checked-IN + 1. N5/N6 buildall ok. + 2. 92CU win7 ping test ok. + +---------------------------------------------------------------------------------------------- +<01/19/2012 21:30 MH_Chen> +Modified Files: +Change Note: + 1. Merge MP V 2384-2400 to support new 88EU/8812U features. + +Verification Before Checked-IN + 1. N5/N6 buildall ok. + 2. 92CU win7 ping test ok. + 3. 92CU XP chariot throughput 1HR ok. + +---------------------------------------------------------------------------------------------- +<01/19/2012 20:00 MH_Chen> +Modified Files: +Change Note: + 1. According to chariot test. 88EU will fail in RX side, we found that + the reason is due to precomp.h setting. If you want to test 88E series IC + Please use below setting. We will fix the problem later. + +#if 1 // For 92C/92D/8723A +#define HAL_SUPPORT_88E_92C 0 +#if (HAL_SUPPORT_88E_92C ==1) + #undef RTL8192D_DUAL_MAC_MODE_SWITCH + #define RTL8192D_DUAL_MAC_MODE_SWITCH 0 + #undef RTL8192D_EASY_SMART_CONCURRENT + #define RTL8192D_EASY_SMART_CONCURRENT 0 + #define RTL8188E_FOR_MP_TEST 1 + #define RTL8188E_EARLY_MODE_PKT_NUM_10 1 + +#endif +#else // for 88E +#define HAL_SUPPORT_88E_92C 1 +#if (HAL_SUPPORT_88E_92C ==1) + #undef RTL8192D_DUAL_MAC_MODE_SWITCH + #define RTL8192D_DUAL_MAC_MODE_SWITCH 0 + #undef RTL8192D_EASY_SMART_CONCURRENT + #define RTL8192D_EASY_SMART_CONCURRENT 0 + #define RTL8188E_FOR_TEST_CHIP 1 + #define RTL8188E_EARLY_MODE_PKT_NUM_10 1 + #define POWER_TRAINING_ACTIVE 0 + #define RATE_ADAPTIVE_SUPPORT 1 + +#endif +#endif + +Verification Before Checked-IN + 1. 88EU/92CU chariot throughput test ok. + +---------------------------------------------------------------------------------------------- +<01/19/2012 16:00 MH_Chen> +Modified Files: +Change Note: + 1. Move 8188E PHY calibrate relative code from HAL\PHY to HAL\ODM\rtl8188e + 2. Revise MP source & build environment for testing ok. + +Verification Before Checked-IN + 1. MP N5/N6 buildall ok. + 2. 92CU win7 ping test ok. + +---------------------------------------------------------------------------------------------- +<01/19/2012 11:50 Georgia> +Modified Files: + odm_HWConfig.c + +Change Note: + 1. Fix compile error and wrning for CE. + 2. Fix system crash for CE. (in func:odm_Process_RSSIForDM incorrect condition judgment) + +Verification Before Checked-IN + 1. CE mak all ok. + 2. 92DU-VS auto-test ok. +---------------------------------------------------------------------------------------------- +<01/17/2012 23:03 MH_Chen> +Modified Files: +Change Note: + 1. Merge PHY-RF relative API for HW out source share. + 2. Disable MP PHY-RF calibrate relative function. + 3. Revise MP build environment for compile pass. + +Verification Before Checked-IN + 1. N5/N62 buildall OK. + 2. CU Win7/XP ping with WPA2-AES AO OK. + +---------------------------------------------------------------------------------------------- +<01/16/2012 18:20 Luke.Lee> +Modified Files: +Change Note: + 1. Fix ODM_CmnInfoInit() + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. 88EU Win7 ping OK + +---------------------------------------------------------------------------------------------- +<01/16/2012 11:30 Luke.Lee> +Modified Files: +Change Note: + 1. Modify 88E CCK RSSI formula. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. 88CE Win7 ping OK + +---------------------------------------------------------------------------------------------- +<01/13/2012 17:32 Georgia> +Modified Files: +Change Note: + 1. Fix compile error for CE. + +Verification Before Checked-IN + 1. CE Platform make ok. + 2. 88CU/92DU-VS/8723AU/8723AS/8188ES Auto-test ok. + +---------------------------------------------------------------------------------------------- +<01/13/2012 16:35 MH_Chen> +Modified Files: +Change Note: + 1. Revise common binary arch for 88EE/88EU. + 2. Fine tune build environment for MP driver. + +Verification Before Checked-IN + 1. N5/N6/N62 buildall ok. + 2. XP platform 88EU ping and reload ok. + 3. Vista platform 92CU link with dir-655 and ping ok. + 4. WIn7 platform 88CU/92DU-VS/8723AU work at the same with rtwlanu.sys. + Ping with dir-655 wpa2-aes S3/S5/reload ok. + + +---------------------------------------------------------------------------------------------- +<01/12/2012 23:50 MH_Chen> +Modified Files: +Change Note: + 1. Merge MP V 2383 to support 88EU/8812U in the same binary. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. Vista platform 92CU link with dir-655 and ping ok. S3 fail~~!!! Under investigation. + 3. WIn7 platform 88CU/92DU-VS/8723AU work at the same with rtwlanu.sys. + Ping with dir-655 wpa2-aes S3/S5/reload ok. + +---------------------------------------------------------------------------------------------- +<01/12/2012 22:46 MH_Chen> +Modified Files: +Change Note: + 1. Support default & AP mode STA info revise for MP. + 2. Fix tracking list item 23/44. + 3. Add more universal interface for power tracking and rf calibrate. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. Vista platform 92CU link with dir-655 and ping ok. + +---------------------------------------------------------------------------------------------- +<01/12/2012 22:02 MH_Chen> +Modified Files: +Change Note: + 1. Merge mp driver to v2382. + 2. Revise MP DM entry arch. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + +---------------------------------------------------------------------------------------------- +<01/12/2012 17:20 MH_Chen> +Modified Files: +Change Note: + 1. Merge mp driver to v2382. + 2. Revise MP DM entry arch. + +Verification Before Checked-IN + 1. N5/N6/N62 buildall ok. + 2. 88CU/8723AU/92DU test in the win7 platfrom. Ping with DIR-655 WPA2-AES ok. + +---------------------------------------------------------------------------------------------- +<01/12/2012 16:20 MH_Chen> +Modified Files: +Change Note: + 1. Fix 92CU BSOD in win7 platfrom due to ODM deinit with null ptr. + 2. Delete MP useless folder. + 3. Revise driver linked & compilerd object. + 4. Revise indlud file flow. + +Verification Before Checked-IN + 1. N5/N6/N62 buildall ok. + 2. 88CU/8723AU/92DU test in the win7 platfrom. S3/S4/reload unplug with DIR-655 WPA2-AES + and ping 1HR ok. Reload more than 150 rounds ok. + +---------------------------------------------------------------------------------------------- +<01/11/2012 22:30 MH_Chen> +Modified Files: +Change Note: + 1. Enable 8723 ODM HW config mode. + +Verification Before Checked-IN + 1. N62 buildrtwu ok. + 2. 88CU/8723AU/92DU test in the win7 platfrom. S3/S4/reload unplug with DIR-655 WPA1-AES + and ping 1HR ok. + +---------------------------------------------------------------------------------------------- +<01/11/2012 21:30 MH_Chen> +Modified Files: +Change Note: + 1. Merge MP driver from v2258 to v2377. + 2. Revise ODM structure for MP. + 3. Mere 88E/8812/8821 common binary. + +Verification Before Checked-IN + 1. N5/N6/N62 buildall ok. + 2. CU WIN7/Vista DIR-655 WPA2/AES S3/S4/S5 reload and ping ok. + 3. DU WIN7 DIR-655 WPA2/AES S3/S4/S5 reload and ping ok. + 3. IN IBM X60 platfrom, run CU reload endurance test. + +---------------------------------------------------------------------------------------------- +<01/10/2012 10:07 Mingzhi> +Modified Files: +Change Note: + 1. fix a bug which will cause BSOD + +Modified Files: + 1. odm.c + 2. odm_RTL8192D.c + +Verification Before Checked-IN + 1. N5 buildrtwu/buildrtwe ok + 2. 88CE plug ok +---------------------------------------------------------------------------------------------- +<01/10/2012 21:30 MH_Chen> +Modified Files: +Change Note: + 1. Merge MP driver from v2218 to v2258. + 2. Revise ODM structure for MP. + 3. Mere 88E common binary. + +Verification Before Checked-IN + 1. N5/N6/N62 buildall ok. + 2. WIN7/Vista DIR-655 WPA2/AES S3/S4/S5 reload and ping ok. + 3. IN previous IBM X60 platfrom, we can ping over 2 HRs ok, no periodic disconnect event. + +---------------------------------------------------------------------------------------------- +<01/10/2012 16:15 MH_Chen> +Modified Files: +Change Note: + 1. Fix unload fail when deinit haldm in platform layer. + +Verification Before Checked-IN + 1. ping with dir-655 and reload ok in vista. + +---------------------------------------------------------------------------------------------- +<01/09/2012 20:08 MH_Chen> +Modified Files: +Change Note: + 1. Fix compile error in MP. + 2. Fix USB init fail for inithaldm in platfrom or hal layer. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. 8188CUS Vista & win7 ping with DIR-655 wpa2 aes ok. + +---------------------------------------------------------------------------------------------- +<01/09/2012 18:45 Georgia> +Modified Files: + odm.c + odm.h + odm_HWConfig.c + rtl8723a/odm_RegConfig8723A.c + rtl8723a/odm_RegConfig8723A.h + +Change Note: + 1. Fix compile error in CE. + 2. Fix SW-ANT-DIV bug. + +Verification Before Checked-IN + 1. CE-Platform make ok. + 2. 8188CUS with SW-ANT-DIV auto-test ok. +---------------------------------------------------------------------------------------------- +<01/09/2012 13:05 Kordan> +Modified Files: + HAL/OUTSRC/odm_precomp.h + +Added Files: + rtl8723a/odm_RegConfig8723A.h + rtl8723a/odm_RegConfig8723A.c + +Change Note: + 1. Merge RTLXXXXX_HWIMG_SUPPORT and RTLXXXXX_SUPPORT precompile flags to RTLXXXXX_SUPPORT. + 2. Rename odm_HWConfigCallee to odm_RegConfig8723A.h/.c and put it in each individual IC folder. + +Verification Before Checked-IN + 1. MP N5/6/62 buildall ok. +---------------------------------------------------------------------------------------------- +<01/09/2012 10:40 MH_Chen> +Modified Files: +Change Note: + 1.Fix N5/N6/ All IC compile error in MP. + +Verification Before Checked-IN + 1.N5/N62 buildall OK + 2. Link with DIR-655 with 92CU but performance is very bad~~~!! Connect and disconnect periodically~~~!! + 3. Try another RTK AP also meet hard to link problem. + +---------------------------------------------------------------------------------------------- +<01/06/2012 15:40 Georgia> +Added Files: + rtl8192c/Hal8192CEFWImg_CE.c + rtl8192c/Hal8192CEFWImg_CE.h + rtl8192c/Hal8192CEMACImg_CE.c + rtl8192c/Hal8192CEMACImg_CE.h + rtl8192c/Hal8192CEPHYImg_CE.c + rtl8192c/Hal8192CEPHYImg_CE.h + rtl8192c/Hal8192CUFWImg_CE.c + rtl8192c/Hal8192CUFWImg_CE.h + rtl8192c/Hal8192CUMACImg_CE.c + rtl8192c/Hal8192CUMACImg_CE.h + rtl8192c/Hal8192CUPHYImg_CE.c + rtl8192c/Hal8192CUPHYImg_CE.h + rtl8192d/Hal8192DEFWImg_CE.c + rtl8192d/Hal8192DEFWImg_CE.h + rtl8192d/Hal8192DEMACImg_CE.c + rtl8192d/Hal8192DEMACImg_CE.h + rtl8192d/Hal8192DEPHYImg_CE.c + rtl8192d/Hal8192DEPHYImg_CE.h + rtl8192d/Hal8192DUFWImg_CE.c + rtl8192d/Hal8192DUFWImg_CE.h + rtl8192d/Hal8192DUMACImg_CE.c + rtl8192d/Hal8192DUMACImg_CE.h + rtl8192d/Hal8192DUPHYImg_CE.c + rtl8192d/Hal8192DUPHYImg_CE.h + rtl8723a/Hal8723SHWImg_CE.c + rtl8723a/Hal8723SHWImg_CE.h + rtl8723a/Hal8723UHWImg_CE.c + rtl8723a/Hal8723UHWImg_CE.h + +Modified Files: + odm.c + odm_precomp.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192c/HalDMOutSrc8192C_CE.h + +Change Note: + 1.)add related phy-parameters for CE. + 2.)remove useless code of SW-Ant-div for CE. + +Verification Before Checked-IN + 1. CE-Platform make OK. + 2. 8188CUS With SW-ANT-DIV auto-test OK. + +---------------------------------------------------------------------------------------------- +<01/05/2012 20:00 Luke.Lee> +Modified Files: + odm.c + odm_HWConfig.c + odm_HWConfig.h + odm_precomp.h + rtl8192d/odm_RTL8192D.c + +Change Note: + 1.Fix DIG error in some condition + 2.include 88E modification from MERGE_TEMP + 3.remove 64bit division + +Verification Before Checked-IN + 1.N5/N62 buildall OK + +---------------------------------------------------------------------------------------------- +<01/04/2012 18:30 Georgia> +Modified Files: + odm.c + odm.h + odm_precomp.h + odm_types.h + rtl8192d/odm_RTL8192D.c + +Change Note: + 1.Fix compile error for CE. + +Verification Before Checked-IN + 1.CE-platform make ok. + 2.92DU-VS autotest ok. + +---------------------------------------------------------------------------------------------- +<01/04/2012 16:00 Mingzhi> +Modified Files: + 1.odm.c + 2.odm_RTL8192D.c + + +Change Note: + 1. fix a bug in ODM_Write_CCK_CCA_Thres/ODM_Write_CCK_CCA_Thres_92D + +Verification Before Checked-IN + 1. N5 buildrtwu/buildrtwe ok + +---------------------------------------------------------------------------------------------- +<01/02/2012 17:40 Kordan> +Removed Files: + HAL/OUTSRC/rtl8723/* + HAL/OUTSRC/rtl8723a/Hal8723HWImg* + HAL/OUTSRC/rtl8723a/Hal8723HWImg_RF.h + HAL/OUTSRC/rtl8723a/Hal8723SHWImg.* + HAL/OUTSRC/rtl8723a/Hal8723UHWImg.* + +Change Note: + 1. none + +Verification Before Checked-IN + 1. none +---------------------------------------------------------------------------------------------- +<01/02/2012 17:35 Kordan> +Modified Files: + HAL/HWIMG/HalHWImg.h + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/odm_precomp.h + +Added Files: + HAL/OUTSRC/odm_HWConfigCallee.h + +Change Note: + 1. Revise the architecture of ODM HW configuration to meet the memory restriction of CE. + a. odm_HWConfigCallee.h to declare functions used in ODM_ReadAndConfig. + 2. Fix compile error for MP. + a. rename Hal8723*HWImg.* to Hal8723*HWImg_CE.* + b. define RTL8192D_HWIMG_SUPPORT + 3. Rename the output hw images' name. + +Verification Before Checked-IN + 1. MP N5/6/62 buildall ok. + 2. 8723AU ping OK. +---------------------------------------------------------------------------------------------- +<12/29/2011 22:30 Georgia> +Modified Files: + odm.c + odm.h + odm_HWConfig.c + odm_precomp.h + odm_types.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192c/HalDMOutSrc8192C_CE.h + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/HalDMOutSrc8192D_CE.h +Added Files: + rtl8723a + rtl8723a/BB + rtl8723a/BB/AGC_TAB_1T.TXT + rtl8723a/BB/PHY_REG_1T.txt + rtl8723a/BB/PHY_REG_MP.txt + rtl8723a/BB/PHY_REG_PG.txt + rtl8723a/FW + rtl8723a/FW/rtl8723fw.BIN + rtl8723a/Hal8723HWImg_BB.c + rtl8723a/Hal8723HWImg_BB.h + rtl8723a/Hal8723HWImg_FW.c + rtl8723a/Hal8723HWImg_FW.h + rtl8723a/Hal8723HWImg_MAC.c + rtl8723a/Hal8723HWImg_MAC.h + rtl8723a/Hal8723HWImg_RF.c + rtl8723a/Hal8723HWImg_RF.h + rtl8723a/Hal8723Reg.h + rtl8723a/Hal8723SHWImg.c + rtl8723a/Hal8723SHWImg.h + rtl8723a/Hal8723UHWImg.c + rtl8723a/Hal8723UHWImg.h + rtl8723a/MAC + rtl8723a/MAC/MAC_REG.txt + rtl8723a/RF + rtl8723a/RF/RadioA_1T.txt + rtl8723a/RF/RadioB_1T.txt + +Change Note: + 1. add & modify related code for rtl8723a. + +Verification Before Checked-IN: + 1.CE-Platform make ok. + 2.8188CUS auto-test (with PS) ok. + 2.8723AU auto-test ok. + +---------------------------------------------------------------------------------------------- +<12/29/2011 18:00 Mingzhi> +Modified Files: + 1.odm.c + 2.odm_RTL8192D.c +Change Note: + 1. fix a bug in ODM_Write_CCK_CCA_Thres/ODM_Write_CCK_CCA_Thres_92D + 2. fix a bug which may cause 92D can't enter false alarm counter statistics function + 3. modify edca turbo + +Verification Before Checked-IN: + 1.MP N5 buildrtwu/buildrtwe ok. + 2.92DU unplug/ scan ok + + +---------------------------------------------------------------------------------------------- +<12/28/2011 22:45 MH_Chen> +Modified Files: +Change Note: + 1. fix compile error for Ra structure. + +Verification Before Checked-IN + 1. MP N5/6/62 buildall ok. + 2. 92DU reload unplug/s3/s4/s5 ok. + +---------------------------------------------------------------------------------------------- +<12/28/2011 19:55 Annie> +Modified Files: + odm.c + odm.h + +Change Note: + 1. Rename: "RATE_ADAPTIVE" -> "ODM_RATE_ADAPTIVE" to fix redifinition bug for MP. + 2. Recover variables for MP. + +Verification Before Checked-IN + 1. ADSL platform make OK. + 2. RTL8192SU/RaLink2870 link ok and ping ok. + +---------------------------------------------------------------------------------------------- +<12/27/2011 18:12 Annie> +Modified Files: + odm.h + +Change Note: + 1. Revise the architecture of ODM HW configuration to meet CE's memory restriction. + 2. Using precompile flag to avoid compiler error caused by struct RATE_ADAPTIVE redefinition in MP team. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. RTL8192SU/RaLink2870 link ok and ping ok. + +---------------------------------------------------------------------------------------------- +<12/27/2011 18:12 Annie> +Modified Files: + odm.h + +Change Note: + 1. Correct the comment for RATE_ADAPTIVE.LowRSSIThresh. + +Verification Before Checked-IN + 1. ADSL platform make OK. + 2. RTL8192SU/RaLink2870 link ok and ping ok. + +---------------------------------------------------------------------------------------------- +<12/27/2011 18:05 Annie> +Modified Files: + odm.c + odm.h + odm_debug.h + odm_types.h + rtl8192c/HalDMOutSrc8192C_ADSL.c + rtl8192c/HalDMOutSrc8192C_ADSL.h + +Change Note: + 1. Fix compile error in ADSL platform. + 2. RA Mask: add ODM_RAStateCheck() to get rssi_level. + +Verification Before Checked-IN + 1. ADSL platform make OK. + 2. RTL8192SU/RaLink2870 link ok and ping ok. + +---------------------------------------------------------------------------------------------- +<12/26/2011 21:00 Mingzhi> +Modified Files: + Odm.c + +Change Noet: + 1. Merge HW antenna diversity in CE/AP Platform + 2. fix a bug about OFDM_Ant1/2_Cnt /CCK_Ant1/2_Cnt caculation in odm_Hwconfig.h + +Verification Before Checked-IN + 1. N5 buildrtwu/we ok + 2. 92DU-VC test ok +---------------------------------------------------------------------------------------------- +<12/26/2011 15:20 Georgia> +Modified Files: + Odm.c +Change Noet: + 1. Fixed null pointer exception in func:odm_CmnInfoHook_Debug + +Verification Before Checked-IN + 1. CE-Platform make OK + 2. 92DU-VS autotest OK. + +---------------------------------------------------------------------------------------------- +<12/23/2011 21:30 Mingzhi> +Modified Files: + Odm.h + Odm.c +Change Noet: + 1. Remove ODM_ChooseIotMainSTA/ODM_IotEdcaSwitch definition to odm.h + 2. add function(MP/CE) odm_IsEdcaTurboDisable/ODM_EdcaParaSelByIot + +Verification Before Checked-IN + 1. N5 buildall OK + 2. 92DU ping ok + +---------------------------------------------------------------------------------------------- +<12/23/2011 20:50 Georgia> +Modified Files: + odm.c + odm_RTL8192D.c + +Change Noet: + 1. Fix the RSSI monitor bug in CE Platform + +Verification Before Checked-IN + 1. CE-Platform make ok + 2. 92DU-VS autotest ok +---------------------------------------------------------------------------------------------- +<12/23/2011 18:00 Kordan> +Modified Files: + Image2Header.exe + HW Configuration source/header/text files + +Change Noet: + 1. Update merged 8723 RF config. + 2. Fix the line-break bug of Image2Header. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. 8723AU ping OK + 3. 8723AU hw config OK +---------------------------------------------------------------------------------------------- +<12/21/2011 13:20 Georgia> +Added Files: + HW_Integration_Status_20111221.xls +Deleted Files: + HW_Integration_Status_20111215.xls +Modified Files: + odm.h + odm_interface.c + odm_interface.h + +Change Noet: + 1. Update ODM status. + 2. Add ODM_ReleaseSpinLock. + 3. Modify ODM_BW_E's definition. + +Verification Before Checked-IN + 1. CE Platform make ok. +---------------------------------------------------------------------------------------------- +<12/20/2011 21:20 Georgia> +Modified Files: + odm.c + odm.h + odm_interface.c + rtl8192d/odm_RTL8192D.c + +Change Noet: + 1. Remove useless code for CE platform. + 2. Add func: odm_EdcaTurboCheckCE temporarily. + 3. Add memory management APIs for CE platform. + +Verification Before Checked-IN + 1. CE Platform make ok. + 2. 8188CUS Auto-test oK. +---------------------------------------------------------------------------------------------- +<12/20/2011 11:07 MH_Chen> +Modified Files: +Change Noet: + 1. Fix 92C/92D init fail for scan fail issue. + 2. Fix ODM HT Channel width setting. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. Link with DIr-655 reload/unplug/S3/S4/S5 and ping ok. + +---------------------------------------------------------------------------------------------- +<12/20/2011 10:50 Kordan> +Modified Files: + HAL/rtl8192C/rtl8192ce/Hal8192CEGen.c + HAL/rtl8192S/rtl8192su/Hal8192SUsbGen.c + +Change Noet: + 1. Fix compile error under 92CE/SU. (remove ODM_CancelAllTimers from SU) + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/20/2011 10:13 Mingzhi> +Modified Files: + odm.c + +Change Noet: + 1. fix a bug which cause dual mac edca turbo works fail + 2. add iot case for 92d in ce platform + +Verification Before Checked-IN + 1. N5 buildrtwu/buildrtwe fail +---------------------------------------------------------------------------------------------- +<12/19/2011 20:20 Georgia> +Modified Files: + odm.c +Deleted Files: + odm_TimerCallbacks.h + +Change Noet: + 1. Move odm_SwAntDivChkAntSwitchCallback APIs back to odm.c + +Verification Before Checked-IN + 1. CE Platform make OK +---------------------------------------------------------------------------------------------- +<12/19/2011 19:40 Kordan> +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_interface.c + HAL/OUTSRC/odm_interface.h + +Change Noet: + 1. Move ODM_InitAllTimers/ODM_CancelAllTimers APIs back to odm.c + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/19/2011 18:10 Kordan> +Modified Files: + none +Change Noet: + 1. Add missing odm_TimerCallbacks.h + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/19/2011 18:05 Kordan> +Modified Files: + HalDM.c + OUTSRC/odm.c + OUTSRC/odm_interface.c + OUTSRC/odm_TimerCallbacks.h + rtl8192C/rtl8192ce/Hal8192CEGen.c + rtl8192C/rtl8192cs/Hal8192CSdioGen.c + rtl8192C/rtl8192cu/Hal8192CUsbGen.c + HEADER/HTType.h + +Change Noet: + 1. Fix RF performance issue: The hardware capability only supports 20M. + 2. ODM_InitAllTimers/ODM_CancelAllTimers API: + a. TimerCallbacks are now defined in odm_TimerCallbacks.h instead of odm.c. + b. Move ODM_InitAllTimers to InitHalDM (after NicIFReadAdapterInfo). + c. ODM_CancelAllTimers in DeInitHalDM (after NicIFDeInitResource). + d. ODM_CancelAllTimers should also be called when doing a reset.(Added in 92CU/CE/CS) + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/19/2011 17:02 Button> +Modified Files: + odm.c + odm.h + odm_interface.c + odm_types.h + rtl8192c/HALDMOutSrc8192C_AP.c + +Change Noet: + 1. Fix compile error in AP platform. + 2. Add delay, timer, memory function + 3. Remove unused funtions + +Verification Before Checked-IN + 1. AP platform build ok. + +---------------------------------------------------------------------------------------------- +<12/19/2011 13:29 Kordan> +Modified Files: + odm.c + Hal8192CUsbGen.c + +Change Noet: + 1. Fix MP compile error caused by CE precompile flag. + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/19/2011 10:25 Kordan> +Modified Files: + odm.h + HAL/PHY/Hal8192CRf6052.c + +Change Noet: + 1. Replace phy_ConfigRFWithHeaderFile with ODM_ConfigRFWithHeaderFile. + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/16/2011 18:30 Georgia> +Modified Files: + HAL/OUTSRC/odm.c + HAL/OUTSRC/odm.h + HAL/OUTSRC/odm_interface.c + HAL/OUTSRC/odm_interface.h + HAL/OUTSRC/odm_types.h + HAL/OUTSRC/rtl8192c/HalDMOutSrc8192C_CE.c + HAL/OUTSRC/rtl8192c/HalDMOutSrc8192C_CE.h + HAL/OUTSRC/rtl8192d/HalDMOutSrc8192D_CE.c + HAL/OUTSRC/rtl8192d/HalDMOutSrc8192D_CE.h + HAL/rtl8192C/rtl8192ce/Hal8192CEGen.c + HAL/rtl8192C/rtl8192cs/Hal8192CSdioGen.c + HAL/rtl8192C/rtl8192cu/Hal8192CUsbGen.c + +Change Noet: + 1. Refine related code of SW AntDiv after link. + 2. Refine some codes of CE platform. + +Verification Before Checked-IN + 1. CE platform make OK + 2. 8188CUS/8188CU(With Antenna_Div)/92DU-VS(With 2.4G) Auto-test ok. +---------------------------------------------------------------------------------------------- +<12/16/2011 11:23 Kordan> +Modified Files: + HAL/HWIMG/HalHWImg.h + HAL/OUTSRC/odm_HWConfig.c + HAL/OUTSRC/odm_HWConfig.h + HAL/OUTSRC/rtl8192c/Hal8192CHWImg_*.c + HAL/OUTSRC/rtl8192c/Hal8192CHWImg_*.h + HAL/OUTSRC/rtl8723/Hal8723HWImg_*.c + HAL/OUTSRC/rtl8723/Hal8723HWImg_*.h + +Change Noet: + 1. ODM_ConfigRFWithHeaderFile is reverted to r14591 and updated. + 2. ODM_ConfigBBWithHeaderFile bug fixed and move RF/AGC_TAB_1T.TXT to BB/. + 3. Image2Header outputs *_HWIMG_SUPPORT flag. + 4. Fix minor compiler error in the previous revision. + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/15/2011 14:04 Annie> +Modified Files: + odm.c + odm_debug.h + +Change Noet: + 1. Correct debug message code about ODM_COMP_RA_MASK functions. + +Verification Before Checked-IN + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<12/14/2011 17:52 Annie> +Modified Files: + odm.c + odm.h + odm_debug.c + odm_debug.h + +Change Noet: + 1. Fix compiler error in ADSL platform. + 2. Correct debug message code about ODM_COMP_ANT_DIV functions. + 3. Refine ODM_RT_TRACE macro. + +Verification Before Checked-IN + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<12/14/2011 13:30 Kordan> +Modified Files: + odm_types.h + odm_HWConfig.c + odm_HWConfig.h + +Change Noet: + 1. Define HAL_STATUS status code in odm_types.h + 2. Replace ODM_ConfigXxxWithHeaderFile(...) return value with HAL_STATUS. + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/14/2011 09:55 Kordan> +Modified Files: + odm.c + odm_HWConfig.c + odm_HWConfig.h + PHY/Hal8192CPhyCfg.c + rtl8192C/rtl8192cu/Hal8192CUsbGen.c + NDIS5/USB/usb_main.c + NDIS6/USB/N6Usn_main.c + +Change Noet: + 1. Put InitHalDM right after NicIFReadAdapter to avoid null adapter. + 2. ODM_ConfigMACWithHeaderFile prototype changed. + 3. Fix minor bugs in previous revision. + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/13/2011 23:58 Georgia> +Modified Files: + odm.c + odm_precomp.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192d/HalDMOutSrc8192D_CE.c + +Change Noet: + 1. odm_DynamicTxPowerNIC integration. + +Verification Before Checked-IN + 1. CE platform make ok. + 2. 8188CUS Autotest ok. +---------------------------------------------------------------------------------------------- +<12/13/2011 20:00 Georgia> +Modified Files: + odm.c + odm.h + odm_HWConfig.h + odm_precomp.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192c/HalDMOutSrc8192C_CE.h + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/HalDMOutSrc8192D_CE.h + +Change Noet: + 1. Fix compiler error in CE platform + +Verification Before Checked-IN + 1. CE platform make ok. + 2. 8188CUS Autotest(with PS-IPS/LPS) ok. +---------------------------------------------------------------------------------------------- +<12/12/2011 20:01 Mingzhi> +Modified Files: + odm.c + +Change Noet: + 1. fix a bug in EDCA Turbo MP/CE + 2. Attention:WMMEDCA_BE is now set to 0, so sometimes EDCA_BE=0 + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/12/2011 14:30 Mingzhi> +Modified Files: + odm.c + +Change Noet: + 1. re-check EDCA Turbo function in AP/ADSL + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/09/2011 14:30 Mingzhi> +Modified Files: + odm.c + +Change Noet: + 1. fix the bug, that source insight can parsing our code correctly + +Verification Before Checked-IN + 1. N5/N62 buildall OK +---------------------------------------------------------------------------------------------- +<12/07/2011 22:33 MH_Chen> +Modified Files: +Change Noet: + 1. Revise SW antenna diversity atchitecture. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. 92CU win7 ping WPA2-AES AP ok. + +---------------------------------------------------------------------------------------------- +<12/07/2011 19:16 Mingzhi> +Modified Files: + odm.h + odm.c + +Change Noet: + 1. add WMMEDCA_BE in common info + 2. Remov ODM_REG() access in EDCA Turbo function + 3. check in HW Antenna Diversity + +Verification Before Checked-IN + 1. N5/N62 buildall OK + +---------------------------------------------------------------------------------------------- +<12/07/2011 17:00 Kordan> +Modified Files: + odm_HWConfig.c + odm.h + +Change Noet: + 1. Replace 4-space with TAB. + 2. Move RegA24 from HalData to ODM common info. + 3. HalData removed. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + +---------------------------------------------------------------------------------------------- +<12/07/2011 16:55 MH_Chen> +Modified Files: +Change Noet: + 1. Enable all support abilit for chanel emurator test in MP driver. + 2. Fix BSOD in Edca turbo scheme. + +Verification Before Checked-IN + 1. N5/N62 buildall OK. + 2. 92CU ping with 92DU MAC1 AP mode with WPA2 AES and ping large packet ok. + 3. Reload/S3/S5 ok. + +---------------------------------------------------------------------------------------------- +<12/07/2011 13:10 Kordan> +Modified Files: + odm_interface.c + odm_interface.h + odm_HWConfig.c + +Change Noet: + 1. Commit missing changes in v87. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + +---------------------------------------------------------------------------------------------- +<12/07/2011 13:10 Kordan> +Modified Files: + odm_interface.c + odm_interface.h + odm_HWConfig.c + +Change Noet: + 1. New interface: ODM_FreeMemory + 2. Corresponding allocate/free changes in ODM_HWConfig.c + +Verification Before Checked-IN + 1. N5/N62 buildall OK + +---------------------------------------------------------------------------------------------- +<12/06/2011 14:40 Kordan> +Modified Files: + odm_HWConfig.h + odm_precomp.h + rtl8723/* + +Change Noet: + 1. Modify build batch files and sources files to build RTL8723. + 2. Add IC type in the name of both variables and functions. + 3. And using the MACRO to replace the long function name. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + +---------------------------------------------------------------------------------------------- +<12/05/2011 20:20 LukeLee> +Modified Files: + odm.c + +Change Noet: + 1. remove useless compile flag + +Verification Before Checked-IN + 1. MP buildall OK + 2. 88CE ping OK + +---------------------------------------------------------------------------------------------- +<12/02/2011 20:25 MH_Chen> +Modified Files: +Change Noet: + 1. Merge MP code base from V1990 to V2218. + 2. Support 88E and 8812 Jaguar code base for MP. + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. 88CU ping DIR-655 AES OK with large pkt 60000 for more than 1HR. + 3. S3/S4/S5/Reload/Unlog ok. + +---------------------------------------------------------------------------------------------- +<12/02/2011 18:00 LukeLee> +Modified Files: + odm.c + odm.h + odm_HWConfig.h + +Change Noet: + 1. Merge SW AntDiv after link + +Verification Before Checked-IN + 1. N5/N62 buildall OK + 2. 88CE ping OK + +---------------------------------------------------------------------------------------------- +<12/02/2011 15:22 Annie> +Modified Files: + odm.c + odm.h + odm_debug.h + odm_precomp.h + +Change Noet: + 1. Use ODM_REG for EDCA_PARAM registers. + 2. Buug fix: correct SupportICType in ADSL path, remove REG_NAMING_RULE_TEST + and ODM_RegisterOffsetTestFunction(). + 3. Disable ODM_GlobalDebugLevel and ODM_GlobalDebugComponents. + +Verification Before Checked-IN + 1. ADSL platform make ok. + 2. Ping 65500 with Ralink 2870 STA over 30 minutes. + 3. Enable ODM_COMP_COMMON: message OK. + +---------------------------------------------------------------------------------------------- +<12/01/2011 16:40 MH_Chen> +Modified Files: +Change Noet: + 1. Fix compiler error in V92 for different declaration. + +Verification Before Checked-IN + 1. MP N5/N62 buildall ok. + 2. 88CU testi wht DIR-655 in WPA2AES ping 60000 packet ok. S3/S4/S5/reload/inplug ok. + +---------------------------------------------------------------------------------------------- +<12/01/2011 16:30 MH_Chen> +Modified Files: +Change Noet: + 1. Revise debug module to fix compile error. + 2. Fix BSOD in MP EDUCA init case temporarily. + +Verification Before Checked-IN + 1. MP N5/N62 buildall ok. + 2. 88CU testi wht DIR-655 in WPA2AES ping 60000 packet ok. S3/S4/S5/reload/inplug ok. + +---------------------------------------------------------------------------------------------- +<12/01/2011 16:14 Annie> +Modified Files: + odm.c + odm.h + odm_debug.h + +Change Noet: + 1. ODM_CmnInfoUpdate(): add ODM_CMNINFO_DBG_COMP/ODM_CMNINFO_DBG_LEVEL to + update DebugComponents/DebugLevel. + +Verification Before Checked-IN + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<12/01/2011 15:05 Annie> +Modified Files: + odm.c + odm.h + odm_debug.h + odm_reg.h + rtl8192c/HalDMOutSrc8192C_ADSL.c + rtl8192c/HalDMOutSrc8192C_ADSL.h + +Change Noet: + 1. Fix compiler error in ADSL platform. + 2. Revise odm debug print macro. + +Verification Before Checked-IN + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<12/01/2011 11:00 Georgia> +Modified Files: + odm_debug.h + +Change Noet: + 1.Append Chip name in ODM_RT_TRACE. + +Verification Before Checked-IN + 1.CE Platform make ok + +---------------------------------------------------------------------------------------------- +<11/30/2011 23:40 Georgia> +Modified Files: + odm.c + odm_debug.c + odm_debug.h + odm_HWConfig.c + rtl8192c/HalDMOutSrc8192C_AP.c + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/odm_RTL8192D.c + +Change Noet: + 1.Rename RT_TRACE to ODM_RT_TRACE + +Verification Before Checked-IN + 1.CE Platform make ok + +---------------------------------------------------------------------------------------------- +<11/30/2011 23:20 Georgia> +Modified Files: + odm.c + odm.h + odm_debug.c + odm_debug.h + odm_HWConfig.c + odm_HWConfig.h + odm_interface.h + odm_precomp.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192c/HalDMOutSrc8192C_CE.h + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/HalDMOutSrc8192D_CE.h + rtl8192d/odm_RTL8192D.h + +Change Noet: + 1.Fixed compiler error in CE platform + +Verification Before Checked-IN + 1.CE Platform make ok + +---------------------------------------------------------------------------------------------- +<11/30/2011 18:42 Mingzhi> +Modified Files: + odm.c + odm.h + odm_RTL8192D.c + odm_RTL8192D.h + +Change Noet: + 1.Merge AP/ADSL/MP/CE Edca turbo function + 2.move ODM_dynamicEarlyMode function to odm_RTL8192D.c + +Verification Before Checked-IN + 1.buildrtwu/buildrtwe ok + +---------------------------------------------------------------------------------------------- +<11/30/2011 16:50 LukeLee> +Modified Files: + odm.c + odm.h + +Change Notes: + 1. Merge SW AntDiv + +Verification Before Checked-IN + 1. BuildAll ok. + +---------------------------------------------------------------------------------------------- +<11/30/2011 15:30 Kordan> +Modified Files: + PrecompInc.h + +Change Notes: + 1. 8192CS compilation error fixed + +Verification Before Checked-IN + 1. BuildAll ok. + +---------------------------------------------------------------------------------------------- +<11/29/2011 20:23 Kordan> +Modified Files: + rtl8723/BB + rtl8723/MAC + rtl8723/RF + rtl8723/FW +Change Notes: + 1. Create new folders for rtl8723 + +Verification Before Checked-IN + 1. none + +---------------------------------------------------------------------------------------------- +<11/29/2011 17:52 Annie> +Modified Files: + odm.c + odm.h +Change Notes: + 1. Add ODM_CMNINFO_ONE_PATH_CCA hook pointer API in common info. + +Verification Before Checked-IN + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<11/28/2011 15:50 Kordan> +Modified Files: + Image2Header.exe + Hal8192CHWImg_Xxx.c + Hal8192CHWImg_Xxx.h + +Change Notes: + 1. Extract repeated code from ODM_GetArrayLengthXxx(...) to reduce the code size. + 2. Remove I2H.tmp after processing. + 3. The bug of transferring FW Binary to HW image is fixed. + +Verification Before Checked-IN + 1. WinXP/Win7 Buildrtwu.bat OK +---------------------------------------------------------------------------------------------- +<11/28/2011 14:00 Kordan> +Modified Files: + odm_HWConfig.c + odm_HWConfig.h + +Change Notes: + 1. Return type of the ODM_ConfigXxxWithHeader(...) is changed to VOID. + 2. Replace COMP_INIT, DBG_LOUD with ODM-prefixed definition + +Verification Before Checked-IN + 1. WinXP/Win7 Buildrtwu.bat OK +---------------------------------------------------------------------------------------------- +<11/28/2011 11:30 Kordan> +Modified Files: + odm.h + odm_HWConfig.c + odm_interface.h + +Change Notes: + 1. New definition: MAX_STALL_TIME, RT_STATUS + 2. odm_ConfigRFReg(...) is new function used to set RF register in ODM_ConfigRFWithHeader(...) + 3. Minor bugs fixed + +Verification Before Checked-IN + 1. WinXP/Win7 Buildrtwu.bat OK +---------------------------------------------------------------------------------------------- +<11/25/2011 20:45 Annie> +Modified Files: + rtl8192c/Hal8192CHWImg_BB.c + rtl8192c/Hal8192CHWImg_BB.h + rtl8192c/Hal8192CHWImg_FW.c + rtl8192c/Hal8192CHWImg_FW.h + rtl8192c/Hal8192CHWImg_MAC.c + rtl8192c/Hal8192CHWImg_MAC.h + rtl8192c/Hal8192CHWImg_RF.c + rtl8192c/Hal8192CHWImg_RF.h + odm.h + odm_precomp.h + +Change Notes: + 1. Fix compile error at ADSL platform. + 2. Rearrange file including in odm_precomp.h. + 3. Move gArrayPointer_XXX from img.h to img.c for redefinition issue. + +Verification Before Checked-IN + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<11/25/2011 14:30 Georgia> +Modified Files: + odm.c + odm.h + odm_debug.c + odm_debug.h + odm_HWConfig.c + odm_HWConfig.h + odm_interface.c + odm_interface.h + odm_precomp.h + odm_types.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/HalDMOutSrc8192D_CE.h + +Change Notes: + 1. remove related pack(1) statement. + 2. add sleep/delay funcs. + 3. fixed compile error / warning at CE platform. + +Verification Before Checked-IN + 1. CE Platform make ok + +---------------------------------------------------------------------------------------------- +<11/25/2011 11:49 Kordan> +Modified Files: + odm.h + odm_HWConfig.c + odm_interface.c + Image2Header.exe + +Change Notes: + 1. New definition in odm.h: + a. ODM_RF_RADIO_PATH_E + b. ODM_delay_ms, ODM_delay_us, odm_StallExecution + c. InterfaceIndex + d. ODM_BaseBand_Config_Type + e. InternalPA5G + 2. Eliminate MP-specific code, for example: PlatformStallExecution -> ODM_delay_us + 3. Arguments of Image2Header.exe now are case-insensitive. + +Verification Before Checked-IN + 1. WinXP/Win7 Buildrtwu.bat OK + +---------------------------------------------------------------------------------------------- +<11/24/2011 21:12 button> +Modified Files: + odm.h + odm.c + rtl8192c/HalDMOutSrc8192C_AP.c + +Change Notes: + 1. Remove AP's PSD from ODM module + 2. Move AP's RSSI monitor into ODM module + 3. Refine AP's IOT peer definition + +Verification Before Checked-In: + 1. AP platform build ok. +---------------------------------------------------------------------------------------------- +<11/24/2011 21:00 Annie> +Renamed Files: + Hal8192CHWImg_fw.c -> Hal8192CHWImg_FW.c + Hal8192CHWImg_fw.h -> Hal8192CHWImg_FW.h + Hal8192CHWImg_mac.c -> Hal8192CHWImg_MAC.c + Hal8192CHWImg_mac.h -> Hal8192CHWImg_MAC.h + +Change Notes: + 1. Rename image FW/MAC files, because linux system is case sensitive. + +Verification Before Checked-IN + N/A + +---------------------------------------------------------------------------------------------- +<11/23/2011 22:30 LukeLee> +Modified Files: + HW_Integration_Status_Luke.xls + odm.c + odm_RTL8192D.c + odm_debug.c + odm_HWConfig.c + +Change Notes: + 1. add GPL on odm_RTL8192D.c + 2. update common info for MP platform + +Verification Before Checked-IN + 1. MP buildall OK except N5 buildrtws fail + 2. 88CE Win7 ping OK + +---------------------------------------------------------------------------------------------- +<11/23/2011 17:30 LukeLee> +Modified Files: + HW_Integration_Status_Luke.xls + odm.c + odm.h + odm_debug.c + odm_HWConfig.c + odm_precomp.h + +Added Files: + Hal8192CHWImg_BB.c + Hal8192CHWImg_BB.h + Hal8192CHWImg_fw.c + Hal8192CHWImg_fw.h + Hal8192CHWImg_mac.c + Hal8192CHWImg_mac.h + Hal8192CHWImg_RF.c + Hal8192CHWImg_RF.h + +Change Notes: + 1. remove compile error + 2. DIG merge OK + 3. PSD and RXHP only for MP platform + +Verification Before Checked-IN + 1. MP buildall OK except N5 buildrtws fail + 2. 88CE Win7 ping OK + +---------------------------------------------------------------------------------------------- +<11/21/2011 15:50 Mingzhi> +Modified Files: + odm.c + odm.h + +Change Notes: + 1. remove variable bDefAdapter_APMode/bDefAdapter_ClientMode/bExtAdapter_APMode/bExtClientMode in Common info + 2. modify dynamic early mode + +Verification Before Checked-IN + 1. MP Platform buildrtwu/buildrtwe ok + +---------------------------------------------------------------------------------------------- +<21/11/2011 14:12 Kordan> +Modified Files: + Image2Header.exe + odm_HWConfig.c + odm_precomp.h + +Change Notes: + 1. Add three ODM_ConfigXxxWithHeaderFile(...) APIs in odm_HWConfig.c. + 2. Image2Header.exe is updated. + 3. Notes: + a. HWImg header files should be included in OUTSRC\odm_precomp.h + b. HWImg source files should be added in source file, + for example, HAL\rtl8192C\rtl8192cu\sources.WlanU.Win + c. By now, text files under the folders are just for testing. + +Verification Before Checked-IN + 1. Buildrtwu.bat OK +---------------------------------------------------------------------------------------------- +<11/21/2011 14:04 Annie> +Modified Files: + odm.c + odm_precomp.h + +Change Notes: + 1. Use RTL8192XX_HWIMG_SUPPORT flag to separate code of differentail chip. + +Verification Before Checked-IN + 1. ADSL platform buildall ok. + +---------------------------------------------------------------------------------------------- +<11/21/2011 13:40 LukeLee> +Removed Files: + HW_Itegration_Status.xls + +Added Files: + HW_Integration_Status_Luke.xls + +Change Notes: + 1. Update HW_Iteration_Status + +Verification Before Checked-IN + N/A +---------------------------------------------------------------------------------------------- +<11/21/2011 11:36 Annie> +Modified Files: + odm.c + odm.h + +Change Notes: + 1. Add common info interface ODM_CMNINFO_BOARD_TYPE. + +Verification Before Checked-IN + 1. ADSL platform buildall ok. + +---------------------------------------------------------------------------------------------- +<11/18/2011 19:10 Annie> +Modified Files: + rtl8192c\odm_RTL8192C.c + rtl8192c\odm_RTL8192C.h + rtl8192d\odm_RTL8192D.c + rtl8192d\odm_RTL8192D.h + odm.c + odm.h + odm_debug.c + odm_precomp.h + odm_types.h + +Change Notes: + 1. Make sure ADSL make ok. + 2. Workaround: Add NO_8192D flag to not include 8192d file and functions. + 3. Check for debug print related code. + +Verification Before Checked-IN + 1. ADSL platform buildall ok. + 2. RT_TRACE: DIG message print OK. + +---------------------------------------------------------------------------------------------- +<11/18/2011 17:50 LukeLee> +Modified Files: +Change Notes: + 1. Move bLinked and RSSI_Min to ODM_CmnInfoUpdate() + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. HW_Itegration_Status.xls cannot be opened + +---------------------------------------------------------------------------------------------- +<18/11/2011 18:13 Kordan> +Modified Files: + Image2Header.exe + +Change Notes: + 1. Bug fixed: If too many files are under the folder, it would run out of buffer. + 2. Bug fixed: Wrong fprintf causes some header files are not included. + +Verification Before Checked-IN + +---------------------------------------------------------------------------------------------- +<11/18/2011 00:01 MH_Chen> +Modified Files: +Change Notes: + 1. Support ODM PHY status query. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. CU slim combo card link with DIR-655 in AES mode and ping more than 20 minutes ok. + 3. PHY status query ok but RSSI seems incorrect. + +---------------------------------------------------------------------------------------------- +<11/17/2011 23:15 MH_Chen> +Modified Files: +Change Notes: + 1. Add more universal interface template and MP can work. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. CU slim combo card link with DIR-655 in AES mode and ping more than 20 minutes ok. + +---------------------------------------------------------------------------------------------- +<11/17/2011 21:06 MH_Chen> +Modified Files: +Change Notes: + 1. Revise #include flow to be compatiable with other SW team. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. CU slim combo card link with DIR-655 in AES mode and ping more than 20 minutes ok. + +---------------------------------------------------------------------------------------------- +<11/17/2011 20:30 LukeLee> +Modified Files: + HW_Itegration_Status.xls + +Change Notes: + 1. update status + +Verification Before Checked-IN + None +---------------------------------------------------------------------------------------------- +<11/17/2011 16:48 MH_Chen> +Modified Files: +Change Notes: + 1. Add new API for spin lock and memory allocate. + 2. Revise MP include flow to default setting. + +Verification Before Checked-IN + 1. N5/N62 buildall ok. + 2. CU slim combo card link with DIR-655 in AES mode and ping more than 20 minutes ok. + +---------------------------------------------------------------------------------------------- +<17/11/2011 10:34 Mingzhi> +Modified Files: + odm.c + +Change Notes: + 1. fix a bug in dynamic_early_mode + + +Verification Before Checked-IN + 1. MP platfrom N5 build ok + +---------------------------------------------------------------------------------------------- +<17/11/2011 10:34 Mingzhi> +Modified Files: + odm.c + +Change Notes: + 1. add variable bDefAdapter_APMode/bDefAdapter_ClientMode/bExtAdapter_APMode/bExtClientMode in Common info + 2. remove ACTING_AS_AP() from dynamic_early_mode + + +Verification Before Checked-IN + 1. MP platfrom N5 build ok +---------------------------------------------------------------------------------------------- +<17/11/2011 13:23 Kordan> +Modified Files: + Image2Header.exe + +Change Notes: + 1. Remove img2headerfile.exe from SVN + 2. Add new Image2Header.exe to SVN + +Verification Before Checked-IN + 1. Usage: Image2Header.exe IC_TYPE FILE_TYPE + + Example: If you want to convert text files in OUTSRC/rtl8192cu/BB/, + you could type the following command. The output files will be + put under OUTSRC/rtl8192cu/. + $ Image2Header.exe rtl8192cu BB (case-sensitive) + +---------------------------------------------------------------------------------------------- +<17/11/2011 10:34 Mingzhi> +Modified Files: + odm.c + +Change Notes: + 1. re-check dynamic_early_mode() function + +Verification Before Checked-IN + 1. MP platfrom N5 build ok +---------------------------------------------------------------------------------------------- +<11/16/2011 22:22 MH_Chen> +Modified Files: +Change Notes: + 1. Revise Dual mac band definition to prevent scan fail. Need to adjust later. + +Verification Before Checked-In: + 1. MP platform N5/N62 build ok. + 2. 92CU/92CE ping with open AP ok. But CU scan stop after a while. + +---------------------------------------------------------------------------------------------- +<11/16/2011 22:22 button> +Modified Files: + odm.h + odm.c + odm_debug.c + odm_debug.h + +Change Notes: + 1. Move AP team's tx power control to ODM module + 2. rename macro IS_STA_VALID + 3. GlobalDebugComponents => ODM_GlobalDebugComponents , + GlobalDebugLevel => ODM_GlobalDebugLevel + +Verification Before Checked-In: + 1. AP platform build ok. + +---------------------------------------------------------------------------------------------- +<11/16/2011 17:40 LukeLee> +Modified Files: + odm.c + odm.h + odm_debug.c + odm_debug.h + odm_precomp.h + \rtl8192c\odm_RTL8192C.c + \rtl8192d\odm_RTL8192D.c + +Added Files: + HW_Itegration_Status.xls + +Change Notes: + 1. add debug flag + 2. add common info print function + 3. modify DIG related functions + +Verification Before Checked-In: + 1. MP platform build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c/odm_RTL8192C.c/odm_RTL8192D.c) + 2. 88CE Win7X86 cannot show scan list since v0049 + 3. #include <../Mp_Promcomp.h> is not allowable in MP platform + +---------------------------------------------------------------------------------------------- +<11/15/2011 13:40 LukeLee> +Modified Files: + odm.c + +Change Notes: + 1. fix compile error + +Verification Before Checked-In: + 1. MP platform build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c/odm_RTL8192C.c/odm_RTL8192D.c) + +---------------------------------------------------------------------------------------------- +<11/15/2011 13:00 LukeLee> +Modified Files: + odm_debug.h + odm.c + +Added Files: + \rtl8192c\odm_RTL8192C.c + \rtl8192c\odm_RTL8192C.h + \rtl8192d\odm_RTL8192D.c + \rtl8192d\odm_RTL8192D.h + +Change Notes: + 1. Merge DIG / FA statistics / CCK CCA threshold functions + 2. debug print OK + +Verification Before Checked-In: + 1. MP platform build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c/odm_RTL8192C.c/odm_RTL8192D.c) + +---------------------------------------------------------------------------------------------- +<11/14/2011 21:15 button> +Modified Files: + odm.h + odm.c + +Change Notes: + 1. Add IOT peer definition + 2. Add a macro "isSTAValid" to check sta validd or not + +Verification Before Checked-In: + 1. AP platform build ok. + +---------------------------------------------------------------------------------------------- +<11/14/2011 16:50 MH_Chen> +Modified Files: + odm.h + odm.c + odm_debug.c + odm_HWConfig.c + +Change Notes: + 1. hook real common info in MP platform. + 2. Revise some universal interface definition compatiable with other SW team. + +Verification Before Checked-In: + 1. MP platform N5/N62 build ok. + +---------------------------------------------------------------------------------------------- +<11/14/2011 13:00 LukeLee> +Modified Files: + odm.h + odm.c + odm_debug.c + odm_HWConfig.c + +Change Notes: + 1. hook fake common info in MP platform for bluescreen issue + 2. add odm_IsLinked() and odm_InitCommonInfo() for ODM internal common info + +Verification Before Checked-In: + 1. MP platform N5/N62 build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c) +---------------------------------------------------------------------------------------------- +<14/11/2011 10:56 Mingzhi> +Modified Files: + odm.c + +Change Notes: + 1. Modify dynamic_early_mode() function + +Verification Before Checked-IN + 1. MP platfrom N5 build ok + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c) + +---------------------------------------------------------------------------------------------- +<11/11/2011 17:20 LukeLee> +Modified Files: + odm.h + odm.h + odm_debug.h + odm_HWConfig.c + +Change Notes: + 1. Modifiy ODM_CmnInfoInit() and ODM_CmnInfoHook() + 2. Define debug tracing components + +Verification Before Checked-In: + 1. MP platform N5/N62 build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c) +---------------------------------------------------------------------------------------------- +<11/11/2011 10:00 LukeLee> +Modified Files: + odm.h + +Change Notes: + 1. Re-define common info + +Verification Before Checked-In: + 1. All platforms should not compile OK!!! + +---------------------------------------------------------------------------------------------- +<11/10/2011 23:00 LukeLee> +Modified Files: + odm.c + odm.h + +Change Notes: + 1. Re-define common info + +Verification Before Checked-In: + 1. All platforms should not compile OK + +---------------------------------------------------------------------------------------------- +<11/10/2011 16:40 MH_Chen> +Modified Files: + odm.c + odm.h +Change Notes: + 1. bRFPathRxEnable �Q�@�U�A�o���ӬO�]�w�� ODM write variable�A�Ҧ� team �����ݭn�]�w�~��A + �p�G�q�ڭ̪� HAL copy �L�h���Ӥ��X�z�C�ҥH���ӬO�b ODM ����update �o��value �� PHY query �ɨϥΡA + �쥻 code base �]���]�~�A�ڭ����ӧאּ bit oriented coding style�A�o�����ڷ| update�C + 2. MacPhyMode �ק令 ptr reference�A�ثe�u��MP�Ψ�Lteam follow + 3. BTCoexist �ק令 ptr reference �ק令�u�� ON/OFF boolean ��ܡA�ѩi� driver ���䴩�A + �کw�q�@�� pseudo ptr in DM structure for all team reference?�C + 4. �U���������� prt reference�A�u�� init �]�w�@���C + 5. �U����ij�]�� run-time �]�w�ȡA�קאּ ptr reference�A���� HAL �@�ήɴN�ק����p~~~!! + 6. �ѩ��ʤ@��ptr �]�w�A�i��|����Lteam compile���L�ٽ�����~~~!!! ����o�W����ij�O�_�i�H support ��?? �p�G�����ٽЭק� execel �[�c�A���¡C + 7. �ڭ̤U���ݭn review �@�U���ǬO ODM/Driver write ���Τ@�U���c�W���C + +Verification Before Checked-In: + 1. N5N62 buildall ok. + +---------------------------------------------------------------------------------------------- +<11/09/2011 23:10 Annie> +Modified Files: + odm.c + odm.h + odm_interface.h + odm_precomp.h + odm_types.h + +Change Notes: + 1. Change PVOID position to bind and allocate DM_ODM_T in priv. + 2. Temporarily mark some code by ADSL_BUILD_WORKAROUND flag + to make sure ADSL make ok. + +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<11/09/2011 22:50 LukeLee> +Modified Files: + odm.c + +Change Notes: + 1. clean compile errors + +Verification Before Checked-In: + 1. MP platform N5/N62 build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c) +---------------------------------------------------------------------------------------------- +<11/09/2011 22:00 LukeLee> +Modified Files: + odm.c + odm.h + +Change Notes: + 1. Merge DIG function into ODM structure + +Verification Before Checked-In: + 1. MP platform N5/N62 build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c) +---------------------------------------------------------------------------------------------- +<11/09/2011 21:45 Button> +Modified Files: + odm.c + odm.h + odm_HWConfig.c + +Change Notes: + 1. Modify structure _ODM_Phy_Status_Info_ for AP query phy info + 2. Avoid core dump when pEntry = NULL + +Verification Before Checked-In: + 1. AP platform build ok + +---------------------------------------------------------------------------------------------- +<11/09/2011 17:00 LukeLee> +Removed Files: + HalDMOutSrc.c + HalDMOutSrc.h + HalHWOutSrc.c + HalHWOutSrc.h + +Added Files: + odm.c + odm.h + odm_HWConfig.c + odm_HWconfig.h + +Change Notes: + 1. File rename + HalDMOutSrc.c/h -> odm.c/h + HalHWOutSrc.c/h -> odm_HWConfig.c/h + 2. add common info for BTDM and DMSP + 3. remove compile errors in MP platform + +Verification Before Checked-In: + 1. MP platform N5/N62 build ok. + (need to include Mp_Precomp.h in odm_debug.c/odm_interface.c/odm.c/odm_HWConfig.c) + +---------------------------------------------------------------------------------------------- +<11/09/2011 14:40 Georgia> +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + HalHWOutSrc.c + HalHWOutSrc.h + rtl8192c/HalDMOutSrc8192C_CE.c + +Change Notes: + 1. Revise related source of odm_DynamicBBPowerSaving for MP driver compile ok. + 2. Removed useless code of CE team driver. + 3. Revise customer id for AP/ADSL driver compiler ok. + +Verification Before Checked-In: + 1. CE platform build ok. + +---------------------------------------------------------------------------------------------- +<11/08/2011 14:20 Georgia> +Modified Files: + HalHWOutSrc.c + HalHWOutSrc.h + +Change Notes: + 1. Removed useless code. + +Verification Before Checked-In: + 1. CE platform build ok. + +---------------------------------------------------------------------------------------------- +<11/08/2011 12:00 Georgia> +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + HalHWOutSrc.c + odm_debug.c + +Change Notes: + 1. fixed phy_staus parsing error in func odm_RxPhyStatus92CSeries_Parsing + +Verification Before Checked-In: + 1. CE platform build ok. + +---------------------------------------------------------------------------------------------- +<11/07/2011 17:00 LukeLee> +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + +Change Notes: + 1. Merge part of DIG function into ODM structure + 2. divide common info OPMode into several BOOLEAN variables + +Verification Before Checked-In: + 1. MP platform build ok. + (need to include Mp_Precomp.h in odm_interface.c/HalDMOutSrc.c/HalHWOutSrc.c) + +---------------------------------------------------------------------------------------------- +<11/04/2011 16:14 Annie> +Modified Files: + odm_interface.h + +Change Notes: + 1. Sorry for no file saving correctly on previous version. + Now compiler ok. + +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<11/04/2011 13:23 Annie> +Modified Files: + odm_interface.h + +Change Notes: + 1. ODM register/bitmap: currently for 92C_SERIES(11N) only, + we don't need to define JAGUARS registers now. + +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<11/03/2011 16:57 Annie> +New Files: + rtl8195/Hal8195Reg.h + odm_reg.h +Modified Files: + rtl8188e/Hal8188EReg.h + rtl8192c/Hal8192CReg.h + rtl8192d/Hal8192DReg.h + rtl8192s/Hal8192SReg.h + rtl8723/Hal8723Reg.h + HalDMOutSrc.c + HalDMOutSrc.h + odm_interface.h + odm_precomp.h + odm_types.h + +Change Notes: + 1. Improve ODM register/bitmap naming rule: use new ODM_REG and ODM_BIT macro. + 2. Move general register definition to odm_reg.h. + +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<11/02/2011 22:47 MH_Chen> +Modified Files: + HAL\rtl8192C\sources.WlanE/U/S + HAL\HalDM.c +Change Notes: + 1. Revise source for MP driver all interface compile ok. + 2. Fix compile error for all CE/AP/ADSL checkin ODM relative function. + 3. Still can not support compile pass withour mp_precomp.h + 4. Revise wireless mode/band type/security mode for CE/MP. + 5. Support ODM debug module. + +Verification Before Checked-In: + 1. N5/N62 compile all ok. Please enale mp_precomp.h in start address. + +---------------------------------------------------------------------------------------------- +<11/02/2011 21:30 Georgia> + +Modified Files: + HalDMOutSrc.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192d/HalDMOutSrc8192D_CE.c + +Change Notes: + 1.Remove useless code. + 2.move EDCA related DM of CE platform to ODM. + +Verification Before Checked-In: + 1. CE platform build ok. + +---------------------------------------------------------------------------------------------- +<11/02/2011 20:00 Georgia> +Modified Files: + HalDMOutSrc.h + HalHWOutSrc.c + odm_types.h + +Change Notes: + 1.Remove useless flag and code. + 2.Fixed incorrect compiler flag. + +Verification Before Checked-In: + 1. Reviewer: Luke Lee. + 2. CE platform build ok. + +---------------------------------------------------------------------------------------------- +<11/02/2011 18:20 Georgia> +New Files: + HalHWOutSrc.c + HalHWOutSrc.h + +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + odm_debug.c + odm_debug.h + odm_interface.c + odm_interface.h + odm_precomp.h + odm_types.h + rtl8192c/Hal8192CReg.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192d/Hal8192DReg.h + rtl8192d/HalDMOutSrc8192D_CE.c + +Removed Files: + rtl8192c/odm_phy_info.h + rtl8192d/odm_phy_info.h + +Change Notes: + 1. Add Func ODM_PhyStatusQuery. + 2. Modify INT8/INT16.. series declaration. + +Verification Before Checked-In: + 1. CE platform build ok. + +---------------------------------------------------------------------------------------------- +<11/02/2011 17:03 Annie> +Modified Files: + HalDMOutSrc.h + odm_interface.h + odm_types.h + +Change Notes: + 1. Add I/O prototypes. + 2. ADSL compile check. +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<11/02/2011 14:45 button> +Removed Files: + HalDMOutSrc_AP.c + HalDMOutSrc_AP.h +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + odm_precomp.h + odm_types.h + rtl8192c/Hal8192CEFWImg_AP.c + rtl8192c/HHal8192CEMACImg_AP.c + rtl8192c/HHal8192CEPHYImg_AP.c + rtl8192c/HHalDMOutSrc8192C_AP.c +Change Notes: + 1. Merge HalDMOutSrc_AO.c/h into HalDMOutSrc.c/h + +Verification Before Checked-In: + 1. AP platform build ok. +---------------------------------------------------------------------------------------------- +<11/01/2011 15:09 Annie> +New Files: + rtl8188e/Hal8188EReg.h + rtl8192c/Hal8192CReg.h + rtl8192d/Hal8192DReg.h + rtl8192s/Hal8192SReg.h + rtl8723/Hal8723Reg.h +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + odm_interface.h + odm_precomp.h + +Change Notes: + 1. Add REG and REG_BIT for general register naming. +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<10/31/2011 14:42 Annie> +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + odm_interface.c + odm_precomp.h + odm_types.h + +Change Notes: + 1. Change DM_ODM_SUPPORT_TYPE definition: defined by BIT + (1) so that we can use "#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))" statement. + (2) Define BITs in odm_types.h. + 2. 8192cd_util.h can be included in odm_precomp.h formally + because it defines basic I/O functions. +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<10/28/2011 13:32 Annie> +Modified Files: + HalDMOutSrc.h + odm_interface.c + odm_precomp.h + odm_types.h + +Change Notes: + 1. Correct I/O prototype. +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<10/27/2011 20:02 button> +Modified Files: + HalDMOutSrc_AP.c + HalDMOutSrc_AP.h + odm_types.h + odm_precomp.h + odm_interface.c + +Change Notes: + 1. Support ODM I/O W/R. + 2. Sync HalDMOutSrc.c/h with HalDMOutSrc_AP.c/h + +Verification Before Checked-In: + 1. AP platform build ok. +---------------------------------------------------------------------------------------------- +<10/27/2011 17:51 Annie> +New Files: + rtl8192c/Hal8192CEFWImg_ADSL.[ch] +Modified Files: + rtl8192c/Hal8192CEMACImg_ADSL.[ch] + HalDMOutSrc.[ch] + odm_precomp.h + +Change Notes: + 1. MAC image: Seperate firmware array to firmware file. + 2. Set ODM_ENDIAN_TYPE for ADSL and AP. + +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<10/27/2011 15:06 Annie> +Modified Files: + odm_types.h + +Change Notes: + 1. Add STA_INFO_T for ADSL/AP case. + +Verification Before Checked-In: + 1. ADSL platform build ok. + +---------------------------------------------------------------------------------------------- +<10/21/2011 18:26 MH> +New Files: + Add odm debug & interface . +Modified Files: +Change Notes: + 1. Support ODM independent I/O and debug interface. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. (Except N5 SDIO due to PSD ODM) + +---------------------------------------------------------------------------------------------- +<10/21/2011 16:20 Georgia> +New Files: + rtl8192c/odm_phy_info.h + rtl8192d/odm_phy_info.h +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + odm_precomp.h + odm_types.h +Change Notes: + 1. Add data struct declaration of phy_info and rx_desc(must discuss the data member declaration method which different HW interface). + 2. Add related statement for pack(1). + 3. Fixed some compiler warning and error in linux platform. + +Verification Before Checked-In: + 1. CE make ok. + +---------------------------------------------------------------------------------------------- +<10/20/2011 23:44 MH> +Modified Files: + HAL\OUTSRC\HalDMOutSrc.c\h + HAL\HalDM.c + HEADER\TypeDef.h +Change Notes: + 1. Add common info interface init/hook/update/array pointer hook. + 2. MP driver can hook all common info interface. You can refer to API dm_ODMStructureInit() + 3. Revise code architecture for common interface hook readbility. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. (Except N5 SDIO due to PSD ODM) + +---------------------------------------------------------------------------------------------- +<10/20/2011 21:30 LukeLee> +Modified Files: + HalDMOutSrc.h + odm_types.h +Change Notes: + 1. Add Reg Naming + 2. Define PHY_INFO + 3. Define TX_INFO + +Verification Before Checked-In: + 1. N5/N62 buildrtwu/buildrtwe ok. (Need to enable mp_precomp.h) + 2. N5/N62 build819xP/build8192SE/build8192SU fail from v0016 + 3. N5 buildrtws fail from v0016 +---------------------------------------------------------------------------------------------- +<10/19/2011 11:04 MH_Chen> +Modified Files: + HAL\OUTSRC\HalDMOutSrc.c\h +Change Notes: + 1. Add and revise for ODM universal interface. + +Verification Before Checked-In: + 1. N5/N62 buildrtwu ok. (Need to enable mp_precomp.h) + +---------------------------------------------------------------------------------------------- +<10/17/2011 14:06 Annie> + +Modified Files: + odm_precomp.h + rtl8192c/HalDMOutSrc8192C_ADSL.c + rtl8192c/HalDMOutSrc8192C_ADSL.h + +Change Notes: + 1. Move original dynamic mechanism to OURSRC. + +Verification Before Checked-In: + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<10/13/2011 21:40 Georgia> + +New Files: + +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + odm_precomp.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192c/HalDMOutSrc8192C_CE.h + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/HalDMOutSrc8192D_CE.h + +Change Notes: + 1. Modify odm_precomp.h for CE project compiler. + 2. Move related code of IQK/APK/LCK to OUTSRC. +Verification Before Checked-In: + 1. CE make ok. + 2. 8192 CU/DU test ok. + +---------------------------------------------------------------------------------------------- +<10/12/2011 15:42 Annie> + +New Files: + 1. HAL/OUTSRC/odm_precomp.h + +Modified Files: + HAL/OUTSRC/ + 1. rtl8192c/Hal8192CEMACImg_ADSL.c + 2. rtl8192c/Hal8192CEPHYImg_ADSL.c + 3. rtl8192c/Hal8192CEPHYImg_ADSL.h + 4. HalDMOutSrc.c + 5. odm_types.h + +Change Notes: + 1. Add odm_precomp.h to provide the including order of header files. + +Verification Before Checked-In: + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<10/07/2011 23:43 Annie> + +New Files: + HAL/OUTSRC/ + 1. rtl8192c/HalDMOutSrc8192C_ADSL.c + 2. rtl8192c/HalDMOutSrc8192C_ADSL.h + +Modified Files: + HAL/OUTSRC/ + 1. HalDMOutSrc.c + 2. HalDMOutSrc.h + 3. HalDMOutSrc.h + +Change Notes: + 1. Modify common code for ADSL project compiler. + - Add a workaround flag: "ADSL_AP_BUILD_WORKAROUND", + it should be eliminated before final stage. + +Verification Before Checked-In: + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<10/07/2011 17:12 Georgia> +Modified Files: + HalDMOutSrc.c + HalDMOutSrc.h + odm_types.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192c/HalDMOutSrc8192C_CE.h + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/HalDMOutSrc8192D_CE.h + +Change Notes: + 1. Modified related ODM code for build CE Team's universal interface. + +Verification Before Checked-In: + 1. CE Team linux driver make ok. + +---------------------------------------------------------------------------------------------- +<10/06/2011 22:12 Jensonlee> +Modified Files: + HAL/OUTSRC/ + 1. rtl8192c/Hal8192CEMACImg_AP.c + 2. rtl8192c/Hal8192CEMACImg_AP.h + 3. rtl8192c/Hal8192CEPHYImg_AP.c + 4. rtl8192c/Hal8192CEPHYImg_AP.c + 5. rtl8192c/Hal8192CEFWImg_AP.h.h + 6. rtl8192c/Hal8192CEFWImg_AP.h.c + 7. rtl8192c/HalDMOutSrc8192C_AP.c + 8. rtl8192c/HalDMOutSrc8192C_AP.h + 9. HalDMOutSrc_AP.h + a. HalDMOutSrc_AP.c + +Change Notes: + 1. Update parameters and ODM outsrc files of AP + +Verification Before Checked-In: + 1. AP platform 8196c+8192c build ok, connect with STA ok. + +---------------------------------------------------------------------------------------------- +<10/06/2011 21:22 Annie> +Modified Files: + HAL/OUTSRC/ + 1. rtl8192c/Hal8192CEMACImg_ADSL.c + 2. rtl8192c/Hal8192CEPHYImg_ADSL.c + 3. rtl8192c/Hal8192CEPHYImg_ADSL.h + 4. odm_types.h + +Change Notes: + 1. Update parameter files: try to sync with sd7 ODM svn. + +Verification Before Checked-In: + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<10/05/2011 22:50 Luke> +New Files: +Modified Files: + /HalDMOutSrc.h +Change Notes: + 1. Add common info and STA structure + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + +---------------------------------------------------------------------------------------------- +<10/05/2011 22:11 Annie> +New Files: + HAL/OUTSRC/rtl8192c/ + 1. Hal8192CEMACImg_ADSL.c + 2. Hal8192CEMACImg_ADSL.h + 3. Hal8192CEPHYImg_ADSL.c + 4. Hal8192CEPHYImg_ADSL.h + +Change Notes: + 1. Add 8192ce MAC/BB/RF parameter files for current ADSL platform. + +Verification Before Checked-In: + 1. ADSL platform make ok. + +---------------------------------------------------------------------------------------------- +<10/05/2011 12:00 Georgia> +New Files: +Modified Files: +Change Notes: + 1. Add odm_types.h. + 2. Remove useless img files. + +Verification Before Checked-In: + 1. CE Team linux driver make ok. + +---------------------------------------------------------------------------------------------- +<09/30/2011 17:50 MH_Chen> +New Files: +Modified Files: +Change Notes: + 1. Revise HW integration architecture. + 2. Add MAC relative image.c. + 3. Update the newest HW parameters. + +Verification Before Checked-In: + 1. Windows N5/N62 compiler buildall ok. + +---------------------------------------------------------------------------------------------- +<09/23/2011 11:30 Georgia> +New Files: + rtl8192c/Hal8192CEPHYImg_CE.c + rtl8192c/Hal8192CEPHYImg_CE.h + rtl8192c/Hal8192CUPHYImg_CE.c + rtl8192c/Hal8192CUPHYImg_CE.h + rtl8192c/HalDMOutSrc8192C_CE.c + rtl8192c/HalDMOutSrc8192C_CE.h + rtl8192d/Hal8192DEPHYImg_CE.c + rtl8192d/Hal8192DEPHYImg_CE.h + rtl8192d/Hal8192DETestPHYImg_CE.c + rtl8192d/Hal8192DETestPHYImg_CE.h + rtl8192d/Hal8192DUPHYImg_CE.c + rtl8192d/Hal8192DUPHYImg_CE.h + rtl8192d/Hal8192DUTestPHYImg_CE.c + rtl8192d/Hal8192DUTestPHYImg_CE.h + rtl8192d/HalDMOutSrc8192D_CE.c + rtl8192d/HalDMOutSrc8192D_CE.h +Modified Files: +Change Notes: + 1. Add related files for SD4- NIC Linux + +Verification Before Checked-In: + 1. CE,CU,DE,DU buildall ok. +---------------------------------------------------------------------------------------------- +<09/22/2011 23:09 MH_Chen> +New Files: +Modified Files: +Change Notes: + 1. Revise batch file for MP driver PCIE/USB/SDIO compile pass. + 2. Revise all architecture for differemt team shaer common iinterface. + 3. Revise coding style for readbility. + 4. All common interface share the same DM structure. + +Verification Before Checked-In: + 1. N5/N62 buildall ok. + 2. We need other teams to use the file to compile pass. + +---------------------------------------------------------------------------------------------- +<09/20/2011 23:01 MH_Chen> +New Files: +Modified Files: +Change Notes: + 1. Add new out source interface for AP/Linux/ADSL/Windows team. + HAL\OUTSRC ==> common interface + HAL\OUTSRC\rtl8192c ==> independent out src files for different team temporarily. + HAL\OUTSRC\rtl8192c\Hal8192CEPHYImg.c/h .... + HAL\OUTSRC\rtl8192c\HalDMOutSrc8192C.c + 2. Disable DM temporarily until the architecture is ready. + 3. Revise DM architecture flow for MP driver. + +Verification Before Checked-In: + 1. Windows CU build ok. + 2. We need other teams to use the file to compile pass. + +------------------------------------------------------------------------------------------ + +<------Template----> +< ??/??/2009 00:00 Name > +New Files: +Modified Files: +Change Notes: +Verification before checked-in: + diff --git a/network/wlan/WDI/HAL/phydm/halhwimg.h b/network/wlan/WDI/HAL/phydm/halhwimg.h new file mode 100644 index 00000000..4c5c8816 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/halhwimg.h @@ -0,0 +1,123 @@ +#pragma once +#ifndef __INC_HW_IMG_H +#define __INC_HW_IMG_H + +// +// 2011/03/15 MH Add for different IC HW image file selection. code size consideration. +// +#if RT_PLATFORM == PLATFORM_LINUX + + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 1 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 0 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + // For 92D + #define RTL8192DE_HWIMG_SUPPORT 1 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 0 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 0 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_USB_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + //For 92D + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 0 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + //For 92D + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + #endif + +#else // PLATFORM_WINDOWS & MacOSX + +//For 92C +#define RTL8192CE_HWIMG_SUPPORT 1 +#define RTL8192CE_TEST_HWIMG_SUPPORT 1 +#define RTL8192CU_HWIMG_SUPPORT 1 +#define RTL8192CU_TEST_HWIMG_SUPPORT 1 + +// For 92D +#define RTL8192DE_HWIMG_SUPPORT 1 +#define RTL8192DE_TEST_HWIMG_SUPPORT 1 +#define RTL8192DU_HWIMG_SUPPORT 1 +#define RTL8192DU_TEST_HWIMG_SUPPORT 1 + + #if defined(UNDER_CE) + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + // For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #else + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 1 + //#define RTL_8723E_TEST_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 1 + //#define RTL_8723U_TEST_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 1 + //#define RTL_8723S_TEST_HWIMG_SUPPORT 1 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 1 + #define RTL8188EU_HWIMG_SUPPORT 1 + #define RTL8188ES_HWIMG_SUPPORT 1 + #endif + +#endif + +#endif //__INC_HW_IMG_H diff --git a/network/wlan/WDI/HAL/phydm/halphyrf_ap.h b/network/wlan/WDI/HAL/phydm/halphyrf_ap.h new file mode 100644 index 00000000..5fc91594 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/halphyrf_ap.h @@ -0,0 +1,153 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PVOID); + //refine by YuChen for 8814A +typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +VOID +ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#if (RTL8192E_SUPPORT==1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); +#endif + +#if (RTL8814A_SUPPORT == 1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#elif ODM_IC_11AC_SERIES_SUPPORT +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); +#endif + +#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M ) + + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + + // +// BB/MAC/RF other monitor API +// + +void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, + IN BOOLEAN bEnableMonitorMode ); + +// +// IQ calibrate +// +void +PHY_IQCalibrate_8192C( IN PADAPTER pAdapter, + IN BOOLEAN bReCovery); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8192C( IN PADAPTER pAdapter); + +// +// AP calibrate +// +void +PHY_APCalibrate_8192C( IN PADAPTER pAdapter, + IN s1Byte delta); +#endif + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +void phydm_rf_init(IN PVOID pDM_VOID); +void phydm_rf_watchdog(IN PVOID pDM_VOID); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/network/wlan/WDI/HAL/phydm/halphyrf_ce.h b/network/wlan/WDI/HAL/phydm/halphyrf_ce.h new file mode 100644 index 00000000..9e95d955 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/halphyrf_ce.h @@ -0,0 +1,95 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +typedef enum _SPUR_CAL_METHOD { + PLL_RESET, + AFE_PHASE_SEL +} SPUR_CAL_METHOD; + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PVOID); +typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +void ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_ClearTxPowerTrackingState( + IN PVOID pDM_VOID + ); + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +void phydm_rf_init( IN PVOID pDM_VOID); +void phydm_rf_watchdog( IN PVOID pDM_VOID); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/network/wlan/WDI/HAL/phydm/halphyrf_win.h b/network/wlan/WDI/HAL/phydm/halphyrf_win.h new file mode 100644 index 00000000..b7aa4bbb --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/halphyrf_win.h @@ -0,0 +1,98 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +typedef enum _SPUR_CAL_METHOD { + PLL_RESET, + AFE_PHASE_SEL +} SPUR_CAL_METHOD; + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PDM_ODM_T); + //refine by YuChen for 8814A +typedef VOID (*FuncSwing)(PDM_ODM_T, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PDM_ODM_T, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +VOID +ConfigureTxpowerTrack( + IN PDM_ODM_T pDM_Odm, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_ClearTxPowerTrackingState( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +VOID odm_IQCalibrate(IN PDM_ODM_T pDM_Odm); +VOID phydm_rf_init( IN PDM_ODM_T pDM_Odm); +VOID phydm_rf_watchdog( IN PDM_ODM_T pDM_Odm); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/network/wlan/WDI/HAL/phydm/mp_precomp.h b/network/wlan/WDI/HAL/phydm/mp_precomp.h new file mode 100644 index 00000000..2e950cb2 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/mp_precomp.h @@ -0,0 +1,20 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + diff --git a/network/wlan/WDI/HAL/phydm/phydm.h b/network/wlan/WDI/HAL/phydm/phydm.h new file mode 100644 index 00000000..21651973 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm.h @@ -0,0 +1,1438 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +//============================================================ +// include files +//============================================================ +#include "phydm_pre_define.h" +#include "phydm_dig.h" +#include "phydm_edcaturbocheck.h" +#include "phydm_pathdiv.h" +#include "phydm_antdiv.h" +#include "phydm_antdect.h" +#include "phydm_dynamicbbpowersaving.h" +#include "phydm_rainfo.h" +#include "phydm_dynamictxpower.h" +#include "phydm_cfotracking.h" +#include "phydm_acs.h" +#include "phydm_adaptivity.h" + + +//#include "rtl8814a/phydm_iqk_8814a.h" +//#include "rtl8822b/phydm_iqk_8822b.h" + + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#include "halphyrf_ap.h" +#include "phydm_powertracking_ap.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#include "phydm_beamforming.h" +#include "phydm_noisemonitor.h" +#include "halphyrf_ce.h" +#include "phydm_powertracking_ce.h" +#endif + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +//#include "phydm_beamforming.h" +#include "phydm_rxhp.h" +#include "halphyrf_win.h" +#include "phydm_powertracking_win.h" +#endif + +//============================================================ +// Definition +//============================================================ +// +// 2011/09/22 MH Define all team supprt ability. +// + +// +// 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. +// +//#define DM_ODM_SUPPORT_AP 0 +//#define DM_ODM_SUPPORT_ADSL 0 +//#define DM_ODM_SUPPORT_CE 0 +//#define DM_ODM_SUPPORT_MP 1 + +// +// 2011/09/28 MH Define ODM SW team support flag. +// + +//For SW AntDiv, PathDiv, 8192C AntDiv joint use +#define TP_MODE 0 +#define RSSI_MODE 1 + +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 +#define TRAFFIC_ULTRA_LOW 2 + +#define NONE 0 + + + + +//8723A High Power IGI Setting +#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 +#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 +#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a +#define DM_DIG_LOW_PWR_THRESHOLD 0x14 + + +//============================================================ +// structure and define +//============================================================ + +// +// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. +// We need to remove to other position??? +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) +typedef struct rtl8192cd_priv { + u1Byte temp; + +}rtl8192cd_priv, *prtl8192cd_priv; +#endif + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +typedef struct _ADAPTER{ + u1Byte temp; + #ifdef AP_BUILD_WORKAROUND + HAL_DATA_TYPE* temp2; + prtl8192cd_priv priv; + #endif +}ADAPTER, *PADAPTER; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +typedef struct _WLAN_STA{ + u1Byte temp; +} WLAN_STA, *PRT_WLAN_STA; + +#endif + +typedef struct _Dynamic_Primary_CCA{ + u1Byte PriCCA_flag; + u1Byte intf_flag; + u1Byte intf_type; + u1Byte DupRTS_flag; + u1Byte Monitor_flag; + u1Byte CH_offset; + u1Byte MF_state; +}Pri_CCA_T, *pPri_CCA_T; + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + + +#ifdef ADSL_AP_BUILD_WORKAROUND +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms +#endif +#if 0//defined in 8192cd.h +// +// Indicate different AP vendor for IOT issue. +// +typedef enum _HT_IOT_PEER +{ + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO = 6, + HT_IOT_PEER_MERU = 7, + HT_IOT_PEER_MARVELL = 8, + HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 + HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP + HT_IOT_PEER_AIRGO = 11, + HT_IOT_PEER_INTEL = 12, + HT_IOT_PEER_RTK_APCLIENT = 13, + HT_IOT_PEER_REALTEK_81XX = 14, + HT_IOT_PEER_REALTEK_WOW = 15, + HT_IOT_PEER_MAX = 16 +}HT_IOT_PEER_E, *PHTIOT_PEER_E; +#endif +#endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 + +// +// Declare for common info +// + +#define IQK_THRESHOLD 8 +#define DPK_THRESHOLD 4 + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +__PACK typedef struct _ODM_Phy_Status_Info_ +{ + u1Byte RxPWDBAll; + u1Byte SignalQuality; /* in 0-100 index. */ + u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ + s1Byte RxMIMOSignalQuality[4]; /* EVM */ + s1Byte RxSNR[4]; /* per-path's SNR */ +#if (RTL8822B_SUPPORT == 1) + u1Byte RxCount; /* RX path counter---*/ +#endif + u1Byte BandWidth; + +} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; + +typedef struct _ODM_Phy_Status_Info_Append_ +{ + u1Byte MAC_CRC32; + +}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; + +#else + +typedef struct _ODM_Phy_Status_Info_ +{ + // + // Be care, if you want to add any element please insert between + // RxPWDBAll & SignalStrength. + // +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + u4Byte RxPWDBAll; +#else + u1Byte RxPWDBAll; +#endif + u1Byte SignalQuality; /* in 0-100 index. */ + s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ + u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ + u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ + s2Byte Cfo_short[4]; /* per-path's Cfo_short */ + s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ + s1Byte RxPower; /* in dBm Translate from PWdB */ + s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u1Byte BTRxRSSIPercentage; + u1Byte SignalStrength; /* in 0-100 index. */ + s1Byte RxPwr[4]; /* per-path's pwdb */ + s1Byte RxSNR[4]; /* per-path's SNR */ +#if (RTL8822B_SUPPORT == 1) + u1Byte RxCount:2; /* RX path counter---*/ + u1Byte BandWidth:2; + u1Byte rxsc:4; /* sub-channel---*/ +#else + u1Byte BandWidth; +#endif + u1Byte btCoexPwrAdjust; +#if (RTL8822B_SUPPORT == 1) + u1Byte channel; /* channel number---*/ + BOOLEAN bMuPacket; /* is MU packet or not---*/ + BOOLEAN bBeamformed; /* BF packet---*/ +#endif +}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; +#endif + +typedef struct _ODM_Per_Pkt_Info_ +{ + //u1Byte Rate; + u1Byte DataRate; + u1Byte StationID; + BOOLEAN bPacketMatchBSSID; + BOOLEAN bPacketToSelf; + BOOLEAN bPacketBeacon; + BOOLEAN bToSelf; +}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; + + +typedef struct _ODM_Phy_Dbg_Info_ +{ + //ODM Write,debug info + s1Byte RxSNRdB[4]; + u4Byte NumQryPhyStatus; + u4Byte NumQryPhyStatusCCK; + u4Byte NumQryPhyStatusOFDM; +#if (RTL8822B_SUPPORT == 1) + u4Byte NumQryMuPkt; + u4Byte NumQryBfPkt; +#endif + u1Byte NumQryBeaconPkt; + //Others + s4Byte RxEVM[4]; + +}ODM_PHY_DBG_INFO_T; + + +typedef struct _ODM_Mac_Status_Info_ +{ + u1Byte test; + +}ODM_MAC_INFO; + +// +// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T +// Please declare below ODM relative info in your STA info structure. +// +#if 1 +typedef struct _ODM_STA_INFO{ + // Driver Write + BOOLEAN bUsed; // record the sta status link or not? + //u1Byte WirelessMode; // + u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E + + // ODM Write + //1 PHY_STATUS_INFO + u1Byte RSSI_Path[4]; // + u1Byte RSSI_Ave; + u1Byte RXEVM[4]; + u1Byte RXSNR[4]; + + // ODM Write + //1 TX_INFO (may changed by IC) + //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. +#if 0 + u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_C; //only in Jagar: 4bit + u1Byte ANTSEL_D; //only in Jagar: 4bit + u1Byte TX_ANTL; //not in Jagar: 2bit + u1Byte TX_ANT_HT; //not in Jagar: 2bit + u1Byte TX_ANT_CCK; //not in Jagar: 2bit + u1Byte TXAGC_A; //not in Jagar: 4bit + u1Byte TXAGC_B; //not in Jagar: 4bit + u1Byte TXPWR_OFFSET; //only in Jagar: 3bit + u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK +#endif + + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // Move To lower layer. + // + // ODM Write Wilson will handle this part(said by Luke.Lee) + //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. +#if 0 + //1 For 88E RA (don't redefine the naming) + u1Byte rate_id; + u1Byte rate_SGI; + u1Byte rssi_sta_ra; + u1Byte SGI_enable; + u1Byte Decision_rate; + u1Byte Pre_rate; + u1Byte Active; + + // Driver write Wilson handle. + //1 TX_RPT (don't redefine the naming) + u2Byte RTY[4]; // ??? + u2Byte TOTAL; // ??? + u2Byte DROP; // ??? + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // +#endif + +}ODM_STA_INFO_T, *PODM_STA_INFO_T; +#endif + +// +// 2011/10/20 MH Define Common info enum for all team. +// +typedef enum _ODM_Common_Info_Definition +{ +//-------------REMOVED CASE-----------// + //ODM_CMNINFO_CCK_HP, + //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? + //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E + //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E +//-------------REMOVED CASE-----------// + + // + // Fixed value: + // + + //-----------HOOK BEFORE REG INIT-----------// + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, // ODM_ABILITY_E + ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E + ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E + ODM_CMNINFO_FAB_VER, // ODM_FAB_E + ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? + ODM_CMNINFO_RFE_TYPE, + ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E + ODM_CMNINFO_PACKAGE_TYPE, + ODM_CMNINFO_EXT_LNA, // TRUE + ODM_CMNINFO_5G_EXT_LNA, + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_5G_EXT_PA, + ODM_CMNINFO_GPA, + ODM_CMNINFO_APA, + ODM_CMNINFO_GLNA, + ODM_CMNINFO_ALNA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_EXT_LNA_GAIN, + ODM_CMNINFO_PATCH_ID, //CUSTOMER ID + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + ODM_CMNINFO_CONFIG_BB_RF, + ODM_CMNINFO_DOMAIN_CODE_2G, + ODM_CMNINFO_DOMAIN_CODE_5G, + ODM_CMNINFO_IQKFWOFFLOAD, + ODM_CMNINFO_HUBUSBMODE, + ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, + ODM_CMNINFO_TX_TP, + ODM_CMNINFO_RX_TP, + ODM_CMNINFO_SOUNDING_SEQ, + //-----------HOOK BEFORE REG INIT-----------// + + + // + // Dynamic value: + // +//--------- POINTER REFERENCE-----------// + ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E + ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E + ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E + ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E + ODM_CMNINFO_BW, // ODM_BW_E + ODM_CMNINFO_CHNL, + ODM_CMNINFO_FORCED_RATE, + + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + //ODM_CMNINFO_RTSTA_AID, // For win driver only? + ODM_CMNINFO_FORCED_IGI_LB, + ODM_CMNINFO_P2P_LINK, + ODM_CMNINFO_FCS_MODE, + ODM_CMNINFO_IS1ANTENNA, + ODM_CMNINFO_RFDEFAULTPATH, +//--------- POINTER REFERENCE-----------// + +//------------CALL BY VALUE-------------// + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK_IN_PROGRESS, + ODM_CMNINFO_LINK, + ODM_CMNINFO_STATION_STATE, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_DBG_COMP, // u8Byte + ODM_CMNINFO_DBG_LEVEL, // u4Byte + ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte + ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte + ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte + ODM_CMNINFO_BT_ENABLED, + ODM_CMNINFO_BT_HS_CONNECT_PROCESS, + ODM_CMNINFO_BT_HS_RSSI, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not + ODM_CMNINFO_BT_DIG, + ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil + ODM_CMNINFO_BT_DISABLE_EDCA, +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + ODM_CMNINFO_VXD_LINK, +#endif +#endif + ODM_CMNINFO_AP_TOTAL_NUM, + ODM_CMNINFO_POWER_TRAINING, +//------------CALL BY VALUE-------------// + + // + // Dynamic ptr array hook itms. + // + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_PHY_STATUS, + ODM_CMNINFO_MAC_STATUS, + + ODM_CMNINFO_MAX, + + +}ODM_CMNINFO_E; + +// +// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY +// +typedef enum _ODM_Support_Ability_Definition +{ + // + // BB ODM section BIT 0-19 + // + ODM_BB_DIG = BIT0, + ODM_BB_RA_MASK = BIT1, + ODM_BB_DYNAMIC_TXPWR = BIT2, + ODM_BB_FA_CNT = BIT3, + ODM_BB_RSSI_MONITOR = BIT4, + ODM_BB_CCK_PD = BIT5, + ODM_BB_ANT_DIV = BIT6, + ODM_BB_PWR_SAVE = BIT7, + ODM_BB_PWR_TRAIN = BIT8, + ODM_BB_RATE_ADAPTIVE = BIT9, + ODM_BB_PATH_DIV = BIT10, + ODM_BB_PSD = BIT11, + ODM_BB_RXHP = BIT12, + ODM_BB_ADAPTIVITY = BIT13, + ODM_BB_CFO_TRACKING = BIT14, + ODM_BB_NHM_CNT = BIT15, + ODM_BB_PRIMARY_CCA = BIT16, + ODM_BB_TXBF = BIT17, + + // + // MAC DM section BIT 20-23 + // + ODM_MAC_EDCA_TURBO = BIT20, + ODM_MAC_EARLY_MODE = BIT21, + + // + // RF ODM section BIT 24-31 + // + ODM_RF_TX_PWR_TRACK = BIT24, + ODM_RF_RX_GAIN_TRACK = BIT25, + ODM_RF_CALIBRATION = BIT26, + +}ODM_ABILITY_E; + +//Move some non-DM enum,define, struc. form phydm.h to phydm_types.h by Dino + +// ODM_CMNINFO_ONE_PATH_CCA +typedef enum tag_CCA_Path +{ + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}ODM_CCA_PATH_E; + +//move RAInfo to Phydm_RaInfo.h + +//Remove struct PATHDIV_PARA to odm_PathDiv.h + +//Remove struct to odm_PowerTracking.h by YuChen +// +// ODM Dynamic common info value definition +// +//Move AntDiv form phydm.h to Phydm_AntDiv.h by Dino + +//move PathDiv to Phydm_PathDiv.h + +typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +} PHY_REG_PG_TYPE; + +// +// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. +// +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (RT_PLATFORM != PLATFORM_LINUX) +typedef +#endif + +struct DM_Out_Source_Dynamic_Mechanism_Structure +#else// for AP,ADSL,CE Team +typedef struct DM_Out_Source_Dynamic_Mechanism_Structure +#endif +{ + //RT_TIMER FastAntTrainingTimer; + // + // Add for different team use temporarily + // + PADAPTER Adapter; // For CE/NIC team + prtl8192cd_priv priv; // For AP/ADSL team + // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. + BOOLEAN odm_ready; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + rtl8192cd_priv fake_priv; +#endif +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + // ADSL_AP_BUILD_WORKAROUND + ADAPTER fake_adapter; +#endif + + PHY_REG_PG_TYPE PhyRegPgValueType; + u1Byte PhyRegPgVersion; + + u8Byte DebugComponents; + u4Byte DebugLevel; + + u4Byte NumQryPhyStatusAll; //CCK + OFDM + u4Byte LastNumQryPhyStatusAll; + u4Byte RxPWDBAve; + BOOLEAN MPDIG_2G; //off MPDIG + u1Byte Times_2G; + +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + BOOLEAN bCckHighPower; + u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE + u1Byte ControlChannel; +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + +//--------REMOVED COMMON INFO----------// + //u1Byte PseudoMacPhyMode; + //BOOLEAN *BTCoexist; + //BOOLEAN PseudoBtCoexist; + //u1Byte OPMode; + //BOOLEAN bAPMode; + //BOOLEAN bClientMode; + //BOOLEAN bAdHocMode; + //BOOLEAN bSlaveOfDMSP; +//--------REMOVED COMMON INFO----------// + + +//1 COMMON INFORMATION + + // + // Init Value + // +//-----------HOOK BEFORE REG INIT-----------// + // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 + u1Byte SupportPlatform; + // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K + u4Byte SupportAbility; + // ODM PCIE/USB/SDIO = 1/2/3 + u1Byte SupportInterface; + // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... + u4Byte SupportICType; + // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... + u1Byte CutVersion; + // Fab Version TSMC/UMC = 0/1 + u1Byte FabVersion; + // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... + u1Byte RFType; + u1Byte RFEType; + // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... + u1Byte BoardType; + u1Byte PackageType; + u2Byte TypeGLNA; + u2Byte TypeGPA; + u2Byte TypeALNA; + u2Byte TypeAPA; + // with external LNA NO/Yes = 0/1 + u1Byte ExtLNA; // 2G + u1Byte ExtLNA5G; //5G + // with external PA NO/Yes = 0/1 + u1Byte ExtPA; // 2G + u1Byte ExtPA5G; //5G + // with external TRSW NO/Yes = 0/1 + u1Byte ExtTRSW; + u1Byte ExtLNAGain; // 2G + u1Byte PatchID; //Customer ID + BOOLEAN bInHctTest; + BOOLEAN bWIFITest; + + BOOLEAN bDualMacSmartConcurrent; + u4Byte BK_SupportAbility; + u1Byte AntDivType; + BOOLEAN ConfigBBRF; + u1Byte odm_Regulation2_4G; + u1Byte odm_Regulation5G; + u1Byte IQKFWOffload; + BOOLEAN cck_new_agc; +//-----------HOOK BEFORE REG INIT-----------// + + // + // Dynamic Value + // +//--------- POINTER REFERENCE-----------// + + u1Byte u1Byte_temp; + BOOLEAN BOOLEAN_temp; + PADAPTER PADAPTER_temp; + + // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 + u1Byte *pMacPhyMode; + //TX Unicast byte count + u8Byte *pNumTxBytesUnicast; + //RX Unicast byte count + u8Byte *pNumRxBytesUnicast; + // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 + u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E + // Frequence band 2.4G/5G = 0/1 + u1Byte *pBandType; + // Secondary channel offset don't_care/below/above = 0/1/2 + u1Byte *pSecChOffset; + // Security mode Open/WEP/AES/TKIP = 0/1/2/3 + u1Byte *pSecurity; + // BW info 20M/40M/80M = 0/1/2 + u1Byte *pBandWidth; + // Central channel location Ch1/Ch2/.... + u1Byte *pChannel; //central channel number + BOOLEAN DPK_Done; + // Common info for 92D DMSP + + BOOLEAN *pbGetValueFromOtherMac; + PADAPTER *pBuddyAdapter; + BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave + // Common info for Status + BOOLEAN *pbScanInProcess; + BOOLEAN *pbPowerSaving; + // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. + u1Byte *pOnePathCCA; + //pMgntInfo->AntennaTest + u1Byte *pAntennaTest; + BOOLEAN *pbNet_closed; + //u1Byte *pAidMap; + u1Byte *pu1ForcedIgiLb; + BOOLEAN *pIsFcsModeEnable; +/*--------- For 8723B IQK-----------*/ + BOOLEAN *pIs1Antenna; + u1Byte *pRFDefaultPath; + // 0:S1, 1:S0 + +//--------- POINTER REFERENCE-----------// + pu2Byte pForcedDataRate; + pu1Byte HubUsbMode; + BOOLEAN *pbFwDwRsvdPageInProgress; + u4Byte *pCurrentTxTP; + u4Byte *pCurrentRxTP; + u1Byte *pSoundingSeq; +//------------CALL BY VALUE-------------// + BOOLEAN bLinkInProcess; + BOOLEAN bWIFI_Direct; + BOOLEAN bWIFI_Display; + BOOLEAN bLinked; + BOOLEAN bsta_state; +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + BOOLEAN VXD_bLinked; +#endif +#endif // for repeater mode add by YuChen 2014.06.23 + u1Byte RSSI_Min; + u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ + BOOLEAN bIsMPChip; + BOOLEAN bOneEntryOnly; + BOOLEAN mp_mode; + u4Byte OneEntry_MACID; + u1Byte pre_number_linked_client; + u1Byte number_linked_client; + u1Byte pre_number_active_client; + u1Byte number_active_client; + // Common info for BTDM + BOOLEAN bBtEnabled; // BT is enabled + BOOLEAN bBtConnectProcess; // BT HS is under connection progress. + u1Byte btHsRssi; // BT HS mode wifi rssi value. + BOOLEAN bBtHsOperation; // BT HS mode is under progress + u1Byte btHsDigVal; // use BT rssi to decide the DIG value + BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo + BOOLEAN bBtBusy; // BT is busy. + BOOLEAN bBtLimitedDig; // BT is busy. + BOOLEAN bDisablePhyApi; +//------------CALL BY VALUE-------------// + u1Byte RSSI_A; + u1Byte RSSI_B; + u1Byte RSSI_C; + u1Byte RSSI_D; + u8Byte RSSI_TRSW; + u8Byte RSSI_TRSW_H; + u8Byte RSSI_TRSW_L; + u8Byte RSSI_TRSW_iso; + u1Byte TXAntStatus; + u1Byte RXAntStatus; + u1Byte cck_lna_idx; + u1Byte cck_vga_idx; + u1Byte ofdm_agc_idx[4]; + + u1Byte RxRate; + BOOLEAN bNoisyState; + u1Byte TxRate; + u1Byte LinkedInterval; + u1Byte preChannel; + u4Byte TxagcOffsetValueA; + BOOLEAN IsTxagcOffsetPositiveA; + u4Byte TxagcOffsetValueB; + BOOLEAN IsTxagcOffsetPositiveB; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u4Byte BbSwingOffsetA; + BOOLEAN IsBbSwingOffsetPositiveA; + u4Byte BbSwingOffsetB; + BOOLEAN IsBbSwingOffsetPositiveB; + u1Byte antdiv_rssi; + u1Byte fat_comb_a; + u1Byte fat_comb_b; + u1Byte antdiv_intvl; + u1Byte AntType; + u1Byte pre_AntType; + u1Byte antdiv_period; + u1Byte antdiv_select; + u1Byte path_select; + u1Byte antdiv_evm_en; + u1Byte bdc_holdstate; + u1Byte NdpaPeriod; + BOOLEAN H2C_RARpt_connect; + BOOLEAN cck_agc_report_type; + + u1Byte dm_dig_max_TH; + u1Byte dm_dig_min_TH; + u1Byte print_agc; + + //For Adaptivtiy + u2Byte NHM_cnt_0; + u2Byte NHM_cnt_1; + s1Byte TH_L2H_ini; + s1Byte TH_EDCCA_HL_diff; + s1Byte TH_L2H_ini_mode2; + s1Byte TH_EDCCA_HL_diff_mode2; + BOOLEAN Carrier_Sense_enable; + u1Byte Adaptivity_IGI_upper; + BOOLEAN adaptivity_flag; + u1Byte DCbackoff; + BOOLEAN Adaptivity_enable; + u1Byte APTotalNum; + BOOLEAN EDCCA_enable; + ADAPTIVITY_STATISTICS Adaptivity; + //For Adaptivtiy + u1Byte LastUSBHub; + u1Byte TxBfDataRate; + u1Byte CurrentAddress[6]; + + u1Byte c2h_cmd_start; + u1Byte fw_debug_trace[60]; + u1Byte pre_c2h_seq; + BOOLEAN fw_buff_is_enpty; + u4Byte data_frame_num; + + /*for noise detection*/ + BOOLEAN NoisyDecision; /*b_noisy*/ + BOOLEAN pre_b_noisy; + u4Byte NoisyDecision_Smooth; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; +#endif + // + //2 Define STA info. + // _ODM_STA_INFO + // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? + PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ + + u2Byte CurrminRptTime; + ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 + + // + // 2012/02/14 MH Add to share 88E ra with other SW team. + // We need to colelct all support abilit to a proper area. + // + BOOLEAN RaSupport88E; + + // Define ........... + + // Latest packet phy info (ODM write) + ODM_PHY_DBG_INFO_T PhyDbgInfo; + //PHY_INFO_88E PhyInfo; + + // Latest packet phy info (ODM write) + ODM_MAC_INFO *pMacInfo; + //MAC_INFO_88E MacInfo; + + // Different Team independt structure?? + + // + //TX_RTP_CMN TX_retrpo; + //TX_RTP_88E TX_retrpo; + //TX_RTP_8195 TX_retrpo; + + // + //ODM Structure + // +#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + BDC_T DM_BdcTable; + #endif + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + SAT_T dm_sat_table; + #endif + +#endif + FAT_T DM_FatTable; + DIG_T DM_DigTable; + + PS_T DM_PSTable; + Pri_CCA_T DM_PriCCA; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RXHP_T DM_RXHP_Table; +#endif + RA_T DM_RA_Table; + FALSE_ALARM_STATISTICS FalseAlmCnt; + FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; + SWAT_T DM_SWAT_Table; + BOOLEAN RSSI_test; + CFO_TRACKING DM_CfoTrack; + ACS DM_ACS; + + + + //IQK_INFO IQK_info; + + +#if (RTL8822B_SUPPORT == 1) + IQK_INFO IQK_info_8822B; +#endif /* (RTL8814A_SUPPORT==1) */ + + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + //Path Div Struct + PATHDIV_PARA pathIQK; +#endif +#if(defined(CONFIG_PATH_DIVERSITY)) + PATHDIV_T DM_PathDiv; +#endif + + EDCA_T DM_EDCA_Table; + u4Byte WMMEDCA_BE; + + // Copy from SD4 structure + // + // ================================================== + // + + //common + //u1Byte DM_Type; + //u1Byte PSD_Report_RXHP[80]; // Add By Gary + //u1Byte PSD_func_flag; // Add By Gary + //for DIG + //u1Byte bDMInitialGainEnable; + //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. + //for Antenna diversity + //u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse + //PSTA_INFO_T RSSI_target; + + BOOLEAN *pbDriverStopped; + BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; + BOOLEAN *pinit_adpt_in_progress; + + //PSD + BOOLEAN bUserAssignLevel; + RT_TIMER PSDTimer; + u1Byte RSSI_BT; //come from BT + BOOLEAN bPSDinProcess; + BOOLEAN bPSDactive; + BOOLEAN bDMInitialGainEnable; + + //MPT DIG + RT_TIMER MPT_DIGTimer; + + //for rate adaptive, in fact, 88c/92c fw will handle this + u1Byte bUseRAMask; + + ODM_RATE_ADAPTIVE RateAdaptive; +//#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if(defined(CONFIG_ANT_DETECTION)) + ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool +#endif + ODM_RF_CAL_T RFCalibrateInfo; + + + // + // Dynamic ATC switch + // + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + // + // Power Training + // + u1Byte ForcePowerTrainingState; + BOOLEAN bChangeState; + u4Byte PT_score; + u8Byte OFDM_RX_Cnt; + u8Byte CCK_RX_Cnt; +#endif + BOOLEAN bDisablePowerTraining; + + // + // ODM system resource. + // + + // ODM relative time. + RT_TIMER PathDivSwitchTimer; + //2011.09.27 add for Path Diversity + RT_TIMER CCKPathDiversityTimer; + RT_TIMER FastAntTrainingTimer; +#ifdef ODM_EVM_ENHANCE_ANTDIV + RT_TIMER EVM_FastAntTrainingTimer; +#endif + RT_TIMER sbdcnt_timer; + + // ODM relative workitem. +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM PathDivSwitchWorkitem; + RT_WORK_ITEM CCKPathDiversityWorkitem; + RT_WORK_ITEM FastAntTrainingWorkitem; + RT_WORK_ITEM MPT_DIGWorkitem; + RT_WORK_ITEM RaRptWorkitem; + RT_WORK_ITEM sbdcnt_workitem; +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + RT_BEAMFORMING_INFO BeamformingInfo; +#endif +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if (RT_PLATFORM != PLATFORM_LINUX) +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#else +}; +#endif + +#else// for AP,ADSL,CE Team +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#endif + + +typedef enum _PHYDM_STRUCTURE_TYPE{ + PHYDM_FALSEALMCNT, + PHYDM_CFOTRACK, + PHYDM_ADAPTIVITY, + PHYDM_ROMINFO, + +}PHYDM_STRUCTURE_TYPE; + + + + typedef enum _ODM_RF_CONTENT{ + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +} ODM_RF_CONTENT; + +typedef enum _ODM_BB_Config_Type{ + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, + CONFIG_BB_PHY_REG_MP, + CONFIG_BB_AGC_TAB_DIFF, +} ODM_BB_Config_Type, *PODM_BB_Config_Type; + +typedef enum _ODM_RF_Config_Type{ + CONFIG_RF_RADIO, + CONFIG_RF_TXPWR_LMT, +} ODM_RF_Config_Type, *PODM_RF_Config_Type; + +typedef enum _ODM_FW_Config_Type{ + CONFIG_FW_NIC, + CONFIG_FW_NIC_2, + CONFIG_FW_AP, + CONFIG_FW_AP_2, + CONFIG_FW_MP, + CONFIG_FW_WoWLAN, + CONFIG_FW_WoWLAN_2, + CONFIG_FW_AP_WoWLAN, + CONFIG_FW_BT, +} ODM_FW_Config_Type; + +// Status code +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef enum _RT_STATUS{ + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}RT_STATUS,*PRT_STATUS; +#endif // end of RT_STATUS definition + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +//#include "odm_function.h" + +//3=========================================================== +//3 DIG +//3=========================================================== + +//Remove DIG by Yuchen + +//3=========================================================== +//3 AGC RX High Power Mode +//3=========================================================== +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +//3=========================================================== +//3 EDCA +//3=========================================================== + +//3=========================================================== +//3 Dynamic Tx Power +//3=========================================================== +//Dynamic Tx Power Control Threshold + +//Remove By YuChen + +//3=========================================================== +//3 Tx Power Tracking +//3=========================================================== + + + +//3=========================================================== +//3 Rate Adaptive +//3=========================================================== +//Remove to odm_RaInfo.h by RS_James + +//3=========================================================== +//3 BB Power Save +//3=========================================================== + +typedef enum tag_1R_CCA_Type_Definition +{ + CCA_1R =0, + CCA_2R = 1, + CCA_MAX = 2, +}DM_1R_CCA_E; + +typedef enum tag_RF_Type_Definition +{ + RF_Save =0, + RF_Normal = 1, + RF_MAX = 2, +}DM_RF_E; + + +// +// Extern Global Variables. +// +//PowerTracking move to odm_powerTrakcing.h by YuChen +// +// check Sta pointer valid or not +// +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) +#else +#define IS_STA_VALID(pSta) (pSta) +#endif + +//Remove DIG by yuchen + +//Remove BB power saving by Yuchen + +//remove PT by yuchen + +//ODM_RAStateCheck() Remove by RS_James + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL)) +//============================================================ +// function prototype +//============================================================ +//#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); + +//Remove DIG by yuchen + + +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter + ); + + +//Remove ODM_RateAdaptiveStateApInit() by RS_James + +//Remove Edca by YuChen + +#endif + + + +u4Byte odm_ConvertTo_dB(u4Byte Value); + +u4Byte odm_ConvertTo_linear(u4Byte Value); + +#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) + +u4Byte +GetPSDData( + PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +VOID +ODM_DMWatchdog_LPS( + IN PDM_ODM_T pDM_Odm +); +#endif + + +s4Byte +ODM_PWdB_Conversion( + IN s4Byte X, + IN u4Byte TotalBit, + IN u4Byte DecimalBit + ); + +s4Byte +ODM_SignConversion( + IN s4Byte value, + IN u4Byte TotalBit + ); + +VOID +ODM_DMInit( + IN PDM_ODM_T pDM_Odm +); + +VOID +ODM_DMReset( + IN PDM_ODM_T pDM_Odm + ); + +VOID +phydm_support_ablity_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm // For common use in the future + ); + +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ); + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ); + +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) +VOID +ODM_InitAllThreads( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_StopAllThreads( + IN PDM_ODM_T pDM_Odm + ); +#endif + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ); + + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); +VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); + + + +u8Byte +PlatformDivision64( + IN u8Byte x, + IN u8Byte y +); + +//==================================================== +//3 PathDiV End +//==================================================== + + +#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); +// +// PathDiveristy Remove by RS_James + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +// +// 2012/01/12 MH Check afapter status. Temp fix BSOD. +// +#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ + if (pDM_Odm->Adapter == NULL)\ + {\ + return;\ + }\ + + +// +// For new definition in MP temporarily fro power tracking, +// + + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +ODM_AsocEntry_Init( + IN PDM_ODM_T pDM_Odm + ); + +//Remove ODM_DynamicARFBSelect() by RS_James + +PVOID +PhyDM_Get_Structure( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Structure_Type +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) +/*===========================================================*/ +/* The following is for compile only*/ +/*===========================================================*/ + +#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE +#define RF_T_METER_92D 0x42 + + +#define SET_TX_DESC_ANTSEL_A_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 0, 1, __Value) +#define SET_TX_DESC_TX_ANTL_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 4, 2, __Value) +#define SET_TX_DESC_TX_ANT_HT_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 6, 2, __Value) +#define SET_TX_DESC_TX_ANT_CCK_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 2, 2, __Value) + +#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) + +#define RX_HAL_IS_CCK_RATE_92C(pDesc)\ + (GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE1M ||\ + GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE2M ||\ + GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE5_5M ||\ + GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE11M) + +#define H2C_92C_PSD_RESULT 16 + +#define rConfig_ram64x16 0xb2c + +#define TARGET_CHNL_NUM_2G_5G 59 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +FillH2CCmd92C( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); +VOID +PHY_SetTxPowerLevel8192C( + IN PADAPTER Adapter, + IN u1Byte channel + ); +u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); + +#endif + +//=========================================================== +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +void odm_dtc(PDM_ODM_T pDM_Odm); +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + + +VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); + + +#endif + diff --git a/network/wlan/WDI/HAL/phydm/phydm_acs.h b/network/wlan/WDI/HAL/phydm/phydm_acs.h new file mode 100644 index 00000000..d7eabda8 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_acs.h @@ -0,0 +1,129 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMACS_H__ +#define __PHYDMACS_H__ + +#define ACS_VERSION "1.0" +#define CLM_VERSION "1.0" + +#define ODM_MAX_CHANNEL_2G 14 +#define ODM_MAX_CHANNEL_5G 24 + +// For phydm_AutoChannelSelectSettingAP() +#define STORE_DEFAULT_NHM_SETTING 0 +#define RESTORE_DEFAULT_NHM_SETTING 1 +#define ACS_NHM_SETTING 2 + +typedef struct _ACS_ +{ + BOOLEAN bForceACSResult; + u1Byte CleanChannel_2G; + u1Byte CleanChannel_5G; + u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times + u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G]; + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + u1Byte ACS_Step; + // NHM Count 0-11 + u1Byte NHM_Cnt[14][11]; + + // AC-Series, for storing previous setting + u4Byte Reg0x990; + u4Byte Reg0x994; + u4Byte Reg0x998; + u4Byte Reg0x99C; + u1Byte Reg0x9A0; // u1Byte + + // N-Series, for storing previous setting + u4Byte Reg0x890; + u4Byte Reg0x894; + u4Byte Reg0x898; + u4Byte Reg0x89C; + u1Byte Reg0xE28; // u1Byte +#endif + +}ACS, *PACS; + + +VOID +odm_AutoChannelSelectInit( + IN PVOID pDM_VOID +); + +VOID +odm_AutoChannelSelectReset( + IN PVOID pDM_VOID +); + +VOID +odm_AutoChannelSelect( + IN PVOID pDM_VOID, + IN u1Byte Channel +); + +u1Byte +ODM_GetAutoChannelSelectResult( + IN PVOID pDM_VOID, + IN u1Byte Band +); + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + +VOID +phydm_AutoChannelSelectSettingAP( + IN PVOID pDM_VOID, + IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING + IN u4Byte acs_step +); + +VOID +phydm_GetNHMStatisticsAP( + IN PVOID pDM_VOID, + IN u4Byte idx, // @ 2G, Real channel number = idx+1 + IN u4Byte acs_step +); + +#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + + +VOID +phydm_CLMInit( + IN PVOID pDM_VOID, + IN u2Byte sampleNum +); + +VOID +phydm_CLMtrigger( + IN PVOID pDM_VOID +); + +BOOLEAN +phydm_checkCLMready( + IN PVOID pDM_VOID +); + +u2Byte +phydm_getCLMresult( + IN PVOID pDM_VOID +); + + +#endif //#ifndef __PHYDMACS_H__
\ No newline at end of file diff --git a/network/wlan/WDI/HAL/phydm/phydm_adaptivity.h b/network/wlan/WDI/HAL/phydm/phydm_adaptivity.h new file mode 100644 index 00000000..99b63871 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_adaptivity.h @@ -0,0 +1,196 @@ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMADAPTIVITY_H__ +#define __PHYDMADAPTIVITY_H__ + +#define ADAPTIVITY_VERSION "9.0.1" /*Add new API for USB3.0 interference in 2.4G*/ + +#define PwdBUpperBound 7 +#define DFIRloss 5 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +typedef enum _tag_PhyDM_REGULATION_Type { + REGULATION_FCC = 0, + REGULATION_MKK = 1, + REGULATION_ETSI = 2, + REGULATION_WW = 3, + + MAX_REGULATION_NUM = 4 +} PhyDM_REGULATION_TYPE; +#endif + +typedef enum tag_PhyDM_set_LNA { + PhyDM_disable_LNA = 0, + PhyDM_enable_LNA = 1, +} PhyDM_set_LNA; + + +typedef enum tag_PhyDM_TRx_MUX_Type +{ + PhyDM_SHUTDOWN = 0, + PhyDM_STANDBY_MODE = 1, + PhyDM_TX_MODE = 2, + PhyDM_RX_MODE = 3 +}PhyDM_Trx_MUX_Type; + +typedef enum tag_PhyDM_MACEDCCA_Type +{ + PhyDM_IGNORE_EDCCA = 0, + PhyDM_DONT_IGNORE_EDCCA = 1 +}PhyDM_MACEDCCA_Type; + +typedef struct _ADAPTIVITY_STATISTICS { + s1Byte TH_L2H_ini_backup; + s1Byte TH_EDCCA_HL_diff_backup; + s1Byte IGI_Base; + u1Byte IGI_target; + u1Byte NHMWait; + s1Byte H2L_lb; + s1Byte L2H_lb; + BOOLEAN bFirstLink; + BOOLEAN bCheck; + BOOLEAN DynamicLinkAdaptivity; + u1Byte APNumTH; + u1Byte AdajustIGILevel; + s1Byte backupL2H; + s1Byte backupH2L; + BOOLEAN bStopEDCCA; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_WORK_ITEM phydm_pauseEDCCAWorkItem; + RT_WORK_ITEM phydm_resumeEDCCAWorkItem; +#endif +} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS; + +VOID +phydm_pauseEDCCA( + IN PVOID pDM_VOID, + IN BOOLEAN bPasueEDCCA +); + +VOID +Phydm_CheckAdaptivity( + IN PVOID pDM_VOID + ); + +VOID +Phydm_CheckEnvironment( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatistics( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsReset( + IN PVOID pDM_VOID +); + +VOID +Phydm_GetNHMCounterStatistics( + IN PVOID pDM_VOID +); + +VOID +Phydm_MACEDCCAState( + IN PVOID pDM_VOID, + IN PhyDM_MACEDCCA_Type State +); + +VOID +Phydm_SetEDCCAThreshold( + IN PVOID pDM_VOID, + IN s1Byte H2L, + IN s1Byte L2H +); + +VOID +Phydm_SetTRxMux( + IN PVOID pDM_VOID, + IN PhyDM_Trx_MUX_Type txMode, + IN PhyDM_Trx_MUX_Type rxMode +); + +BOOLEAN +Phydm_CalNHMcnt( + IN PVOID pDM_VOID +); + +VOID +Phydm_SearchPwdBLowerBound( + IN PVOID pDM_VOID +); + +VOID +Phydm_AdaptivityInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_Adaptivity( + IN PVOID pDM_VOID, + IN u1Byte IGI + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Phydm_DisableEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_DynamicEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_AdaptivityBSOD( + IN PVOID pDM_VOID +); + +#endif + +VOID +phydm_pauseEDCCA_WorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +phydm_resumeEDCCA_WorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_antdect.h b/network/wlan/WDI/HAL/phydm/phydm_antdect.h new file mode 100644 index 00000000..f3ccfad3 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_antdect.h @@ -0,0 +1,98 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDECT_H__ +#define __PHYDMANTDECT_H__ + +#define ANTDECT_VERSION "2.0" //2014.11.04 + +#if(defined(CONFIG_ANT_DETECTION)) +//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) +//ANT Test +#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/ +#define ANTTESTA 0x01 /*Ant A will be Testing*/ +#define ANTTESTB 0x02 /*Ant B will be testing*/ + +#define MAX_ANTENNA_DETECTION_CNT 10 + + +typedef struct _ANT_DETECTED_INFO{ + BOOLEAN bAntDetected; + u4Byte dBForAntA; + u4Byte dBForAntB; + u4Byte dBForAntO; +}ANT_DETECTED_INFO, *PANT_DETECTED_INFO; + + +typedef enum tag_SW_Antenna_Switch_Definition +{ + Antenna_A = 1, + Antenna_B = 2, + Antenna_MAX = 3, +}DM_SWAS_E; + + + +//1 [1. Single Tone Method] =================================================== + + + +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PVOID pDM_VOID + ); + +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PVOID pDM_VOID, + IN u1Byte mode + ); + +//1 [2. Scan AP RSSI Method] ================================================== + +#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink + +BOOLEAN +ODM_SwAntDivCheckBeforeLink( + IN PVOID pDM_VOID + ); + + + + +//1 [3. PSD Method] ========================================================== + + +VOID +ODM_SingleDualAntennaDetection_PSD( + IN PVOID pDM_VOID +); + +#endif + +VOID +odm_SwAntDetectInit( + IN PVOID pDM_VOID + ); + + +#endif + + diff --git a/network/wlan/WDI/HAL/phydm/phydm_antdiv.h b/network/wlan/WDI/HAL/phydm/phydm_antdiv.h new file mode 100644 index 00000000..95b1cee3 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_antdiv.h @@ -0,0 +1,628 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDIV_H__ +#define __PHYDMANTDIV_H__ + +/*#define ANTDIV_VERSION "2.0" //2014.11.04*/ +/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ +/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ +/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ +/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ +#define ANTDIV_VERSION "3.3" /*2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, +because antenna diversity only works when BT is disable or radio off*/ + +//1 ============================================================ +//1 Definition +//1 ============================================================ + +#define ANTDIV_INIT 0xff +#define MAIN_ANT 1 //Ant A or Ant Main +#define AUX_ANT 2 //AntB or Ant Aux +#define MAX_ANT 3 // 3 for AP using + +#define ANT1_2G 0 // = ANT2_5G +#define ANT2_2G 1 // = ANT1_5G +/*smart antenna*/ +#define SUPPORT_RF_PATH_NUM 4 +#define SUPPORT_BEAM_PATTERN_NUM 4 + + +//Antenna Diversty Control Type +#define ODM_AUTO_ANT 0 +#define ODM_FIX_MAIN_ANT 1 +#define ODM_FIX_AUX_ANT 2 + +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8188F|ODM_RTL8723D) +#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) +#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT|ODM_AC_ANTDIV_SUPPORT) +#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E) +#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821) + +#define ODM_OLD_IC_ANTDIV_SUPPORT (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8192D) + +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A|ODM_RTL8188F|ODM_RTL8723D) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) + +#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E) + +#define ODM_ANTDIV_2G BIT0 +#define ODM_ANTDIV_5G BIT1 + +#define ANTDIV_ON 1 +#define ANTDIV_OFF 0 + +#define FAT_ON 1 +#define FAT_OFF 0 + +#define TX_BY_DESC 1 +#define REG 0 + +#define RSSI_METHOD 0 +#define EVM_METHOD 1 +#define CRC32_METHOD 2 + +#define INIT_ANTDIV_TIMMER 0 +#define CANCEL_ANTDIV_TIMMER 1 +#define RELEASE_ANTDIV_TIMMER 2 + +#define CRC32_FAIL 1 +#define CRC32_OK 0 + +#define Evm_RSSI_TH_High 25 +#define Evm_RSSI_TH_Low 20 + +#define NORMAL_STATE_MIAN 1 +#define NORMAL_STATE_AUX 2 +#define TRAINING_STATE 3 + +#define FORCE_RSSI_DIFF 10 + +#define CSI_ON 1 +#define CSI_OFF 0 + +#define DIVON_CSIOFF 1 +#define DIVOFF_CSION 2 + +#define BDC_DIV_TRAIN_STATE 0 +#define BDC_BFer_TRAIN_STATE 1 +#define BDC_DECISION_STATE 2 +#define BDC_BF_HOLD_STATE 3 +#define BDC_DIV_HOLD_STATE 4 + +#define BDC_MODE_1 1 +#define BDC_MODE_2 2 +#define BDC_MODE_3 3 +#define BDC_MODE_4 4 +#define BDC_MODE_NULL 0xff + +/*SW S0S1 antenna diversity*/ +#define SWAW_STEP_INIT 0xff +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +#define HL_SMTANT_2WIRE_DATA_LEN 24 + +//1 ============================================================ +//1 structure +//1 ============================================================ + + +typedef struct _SW_Antenna_Switch_ +{ + u1Byte Double_chk_flag; + u1Byte try_flag; + s4Byte PreRSSI; + u1Byte CurAntenna; + u1Byte PreAntenna; + u1Byte RSSI_Trying; + u1Byte TestMode; + u1Byte bTriggerAntennaSwitch; + u1Byte SelectAntennaMap; + u1Byte RSSI_target; + u1Byte reset_idx; + u2Byte Single_Ant_Counter; + u2Byte Dual_Ant_Counter; + u2Byte Aux_FailDetec_Counter; + u2Byte Retry_Counter; + + // Before link Antenna Switch check + u1Byte SWAS_NoLink_State; + u4Byte SWAS_NoLink_BK_Reg860; + u4Byte SWAS_NoLink_BK_Reg92c; + u4Byte SWAS_NoLink_BK_Reg948; + BOOLEAN ANTA_ON; //To indicate Ant A is or not + BOOLEAN ANTB_ON; //To indicate Ant B is on or not + BOOLEAN Pre_Aux_FailDetec; + BOOLEAN RSSI_AntDect_bResult; + u1Byte Ant5G; + u1Byte Ant2G; + + s4Byte RSSI_sum_A; + s4Byte RSSI_sum_B; + s4Byte RSSI_cnt_A; + s4Byte RSSI_cnt_B; + + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u8Byte TXByteCnt_A; + u8Byte TXByteCnt_B; + u8Byte RXByteCnt_A; + u8Byte RXByteCnt_B; + u1Byte TrafficLoad; + u1Byte Train_time; + u1Byte Train_time_flag; + RT_TIMER SwAntennaSwitchTimer; +#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) + RT_TIMER SwAntennaSwitchTimer_8723B; + u4Byte PktCnt_SWAntDivByCtrlFrame; + BOOLEAN bSWAntDivByCtrlFrame; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if USE_WORKITEM + RT_WORK_ITEM SwAntennaSwitchWorkitem; + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) + RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B; + #endif + #endif +#endif +/* CE Platform use +#ifdef CONFIG_SW_ANTENNA_DIVERSITY + _timer SwAntennaSwitchTimer; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u8Byte TXByteCnt_A; + u8Byte TXByteCnt_B; + u8Byte RXByteCnt_A; + u8Byte RXByteCnt_B; + u1Byte DoubleComfirm; + u1Byte TrafficLoad; + //SW Antenna Switch + + +#endif +*/ +#ifdef CONFIG_HW_ANTENNA_DIVERSITY + //Hybrid Antenna Diversity + u4Byte CCK_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte CCK_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte OFDM_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte OFDM_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte RSSI_Ant1_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte RSSI_Ant2_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte TxAnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte TargetSTA; + u1Byte antsel; + u1Byte RxIdleAnt; + +#endif + +}SWAT_T, *pSWAT_T; + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) +typedef struct _BF_DIV_COEX_ +{ + BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM]; + BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; + + u1Byte BDCcoexType_wBfer; + u1Byte num_Txbfee_Client; + u1Byte num_Txbfer_Client; + u1Byte BDC_Try_counter; + u1Byte BDC_Hold_counter; + u1Byte BDC_Mode; + u1Byte BDC_active_Mode; + u1Byte BDC_state; + u1Byte BDC_RxIdleUpdate_counter; + u1Byte num_Client; + u1Byte pre_num_Client; + u1Byte num_BfTar; + u1Byte num_DivTar; + + BOOLEAN bAll_DivSta_Idle; + BOOLEAN bAll_BFSta_Idle; + BOOLEAN BDC_Try_flag; + BOOLEAN BF_pass; + BOOLEAN DIV_pass; +}BDC_T,*pBDC_T; +#endif +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +typedef struct _SMART_ANTENNA_TRAINNING_ { + u4Byte latch_time; + BOOLEAN pkt_skip_statistic_en; + u4Byte fix_beam_pattern_en; + u4Byte fix_training_num_en; + u4Byte fix_beam_pattern_codeword; + u4Byte update_beam_codeword; + u4Byte ant_num; /*number of smart beam antenna*/ + u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ + u4Byte data_codeword_bit_num; + u4Byte per_beam_training_pkt_num; + u4Byte pkt_counter; + u4Byte fast_training_beam_num; + u4Byte pre_fast_training_beam_num; + u4Byte pkt_rssi_sum[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte pkt_rssi_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM]; + u4Byte pre_codeword; + BOOLEAN force_update_beam_en; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM hl_smart_antenna_workitem; + RT_WORK_ITEM hl_smart_antenna_decision_workitem; + #endif + +} SAT_T, *pSAT_T; +#endif + +typedef struct _FAST_ANTENNA_TRAINNING_ +{ + u1Byte Bssid[6]; + u1Byte antsel_rx_keep_0; + u1Byte antsel_rx_keep_1; + u1Byte antsel_rx_keep_2; + u1Byte antsel_rx_keep_3; + u4Byte antSumRSSI[7]; + u4Byte antRSSIcnt[7]; + u4Byte antAveRSSI[7]; + u1Byte FAT_State; + u4Byte TrainIdx; + u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte RxIdleAnt; + u1Byte AntDiv_OnOff; + BOOLEAN bBecomeLinked; + u4Byte MinMaxRSSI; + u1Byte idx_AntDiv_counter_2G; + u1Byte idx_AntDiv_counter_5G; + u1Byte AntDiv_2G_5G; + u4Byte CCK_counter_main; + u4Byte CCK_counter_aux; + u4Byte OFDM_counter_main; + u4Byte OFDM_counter_aux; + + #ifdef ODM_EVM_ENHANCE_ANTDIV + u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + BOOLEAN EVM_method_enable; + u1Byte TargetAnt_EVM; + u1Byte TargetAnt_CRC32; + u1Byte TargetAnt_enhance; + u1Byte pre_TargetAnt_enhance; + u2Byte Main_MPDU_OK_cnt; + u2Byte Aux_MPDU_OK_cnt; + + u4Byte CRC32_Ok_Cnt; + u4Byte CRC32_Fail_Cnt; + u4Byte MainCRC32_Ok_Cnt; + u4Byte AuxCRC32_Ok_Cnt; + u4Byte MainCRC32_Fail_Cnt; + u4Byte AuxCRC32_Fail_Cnt; + #endif + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u4Byte CCK_CtrlFrame_Cnt_main; + u4Byte CCK_CtrlFrame_Cnt_aux; + u4Byte OFDM_CtrlFrame_Cnt_main; + u4Byte OFDM_CtrlFrame_Cnt_aux; + u4Byte MainAnt_CtrlFrame_Sum; + u4Byte AuxAnt_CtrlFrame_Sum; + u4Byte MainAnt_CtrlFrame_Cnt; + u4Byte AuxAnt_CtrlFrame_Cnt; + #endif + BOOLEAN fix_ant_bfee; + BOOLEAN enable_ctrl_frame_antdiv; + BOOLEAN use_ctrl_frame_antdiv; + u1Byte hw_antsw_occur; +}FAT_T,*pFAT_T; + + +//1 ============================================================ +//1 enumeration +//1 ============================================================ + + + +typedef enum _FAT_STATE /*Fast antenna training*/ +{ + FAT_BEFORE_LINK_STATE = 0, + FAT_PREPARE_STATE = 1, + FAT_TRAINING_STATE = 2, + FAT_DECISION_STATE = 3 +}FAT_STATE_E, *PFAT_STATE_E; + +typedef enum _ANT_DIV_TYPE +{ + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, + S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/ + HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/ +}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; + + +//1 ============================================================ +//1 function prototype +//1 ============================================================ + + +VOID +ODM_StopAntennaSwitchDm( + IN PVOID pDM_VOID + ); +VOID +ODM_SetAntConfig( + IN PVOID pDM_VOID, + IN u1Byte antSetting // 0=A, 1=B, 2=C, .... + ); + + +#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink +VOID ODM_SwAntDivRestAfterLink( + IN PVOID pDM_VOID + ); + +#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) + +VOID +ODM_UpdateRxIdleAnt( + IN PVOID pDM_VOID, + IN u1Byte Ant +); + +#if (RTL8188F_SUPPORT == 1) +VOID +phydm_update_rx_idle_antenna_8188F( + IN PVOID pDM_VOID, + IN u4Byte default_ant +); +#endif + +#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_SW_AntDiv_Callback( + IN PRT_TIMER pTimer + ); + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext + ); + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext +); + +VOID +ODM_SW_AntDiv_Callback( + void *FunctionContext + ); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +odm_S0S1_SwAntDivByCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte Step +); + +VOID +odm_AntselStatisticsOfCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte RxPWDBAll +); + +VOID +odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( + IN PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void +); + + +#endif +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV +VOID +odm_EVM_FastAntTrainingCallback( + IN PVOID pDM_VOID +); +#endif + +VOID +odm_HW_AntDiv( + IN PVOID pDM_VOID +); + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) +VOID +odm_FastAntTraining( + IN PVOID pDM_VOID +); + +VOID +odm_FastAntTrainingCallback( + IN PVOID pDM_VOID +); + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PVOID pDM_VOID +); +#endif + + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +phydm_beam_switch_workitem_callback( + IN PVOID pContext + ); + +VOID +phydm_beam_decision_workitem_callback( + IN PVOID pContext + ); + +#endif + +VOID +phydm_update_beam_pattern( + IN PVOID pDM_VOID, + IN u4Byte codeword, + IN u4Byte codeword_length + ); + +void +phydm_set_all_ant_same_beam_num( + IN PVOID pDM_VOID + ); + +VOID +phydm_hl_smart_ant_cmd( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +); + +#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +VOID +ODM_AntDivInit( + IN PVOID pDM_VOID +); + +VOID +ODM_AntDiv( + IN PVOID pDM_VOID +); + +VOID +odm_AntselStatistics( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u4Byte utility, + IN u1Byte method +); + +VOID +ODM_Process_RSSIForAntDiv( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void +); + + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + +#define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink + +VOID +ODM_SwAntDivResetBeforeLink( + IN PDM_ODM_T pDM_Odm +); + +VOID +ODM_SetTxAntByTxInfo( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId +); + +#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +ODM_SetTxAntByTxInfo( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid +); + +#endif + + +VOID +ODM_AntDiv_Config( + IN PVOID pDM_VOID +); + + +VOID +ODM_UpdateRxIdleAnt_8723B( + IN PVOID pDM_VOID, + IN u1Byte Ant, + IN u4Byte DefaultAnt, + IN u4Byte OptionalAnt +); + +VOID +ODM_AntDivTimers( + IN PVOID pDM_VOID, + IN u1Byte state +); + +#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) + +VOID +ODM_AntDivReset( + IN PVOID pDM_VOID +); + +VOID +odm_AntennaDiversityInit( + IN PVOID pDM_VOID +); + +VOID +odm_AntennaDiversity( + IN PVOID pDM_VOID +); + + +#endif //#ifndef __ODMANTDIV_H__ diff --git a/network/wlan/WDI/HAL/phydm/phydm_beamforming.h b/network/wlan/WDI/HAL/phydm/phydm_beamforming.h new file mode 100644 index 00000000..ed472ce6 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_beamforming.h @@ -0,0 +1,376 @@ +#ifndef __INC_BEAMFORMING_H +#define __INC_BEAMFORMING_H + +#ifndef BEAMFORMING_SUPPORT +#define BEAMFORMING_SUPPORT 0 +#endif + +/*Beamforming Related*/ +#include "txbf/halcomtxbf.h" +#include "txbf/haltxbfjaguar.h" +#include "txbf/haltxbf8192e.h" +#include "txbf/haltxbf8814a.h" +#include "txbf/haltxbf8821b.h" +#include "txbf/haltxbf8822b.h" +#include "txbf/haltxbfinterface.h" + +#if (BEAMFORMING_SUPPORT == 1) + +#define MAX_BEAMFORMEE_SU 2 +#define MAX_BEAMFORMER_SU 2 +#if (RTL8822B_SUPPORT == 1) +#define MAX_BEAMFORMEE_MU 6 +#define MAX_BEAMFORMER_MU 1 +#else +#define MAX_BEAMFORMEE_MU 0 +#define MAX_BEAMFORMER_MU 0 +#endif + +#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) +#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*for different naming between WIN and CE*/ +#define BEACON_QUEUE BCN_QUEUE_INX +#define NORMAL_QUEUE MGT_QUEUE_INX +#define eqMacAddr(a, b) ((a[0] == b[0] && a[1] == b[1] && a[2] == b[2] && a[3] == b[3] && a[4] == b[4] && a[5] == b[5]) ? 1:0) +#define cpMacAddr(des, src) (des[0] = src[0], des[1] = src[1], des[2] = src[2], des[3] = src[3], des[4] = src[4], des[5] = src[5]) +#define cpIpAddr(des, src) (des[0] = src[0], des[1] = src[1], des[2] = src[2], des[3] = src[3]) +#define RT_DISABLE_FUNC RTW_DISABLE_FUNC +#define RT_ENABLE_FUNC RTW_ENABLE_FUNC +#endif + +typedef enum _BEAMFORMING_ENTRY_STATE { + BEAMFORMING_ENTRY_STATE_UNINITIALIZE, + BEAMFORMING_ENTRY_STATE_INITIALIZEING, + BEAMFORMING_ENTRY_STATE_INITIALIZED, + BEAMFORMING_ENTRY_STATE_PROGRESSING, + BEAMFORMING_ENTRY_STATE_PROGRESSED +} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; + + +typedef enum _BEAMFORMING_NOTIFY_STATE { + BEAMFORMING_NOTIFY_NONE, + BEAMFORMING_NOTIFY_ADD, + BEAMFORMING_NOTIFY_DELETE, + BEAMFORMEE_NOTIFY_ADD_SU, + BEAMFORMEE_NOTIFY_DELETE_SU, + BEAMFORMEE_NOTIFY_ADD_MU, + BEAMFORMEE_NOTIFY_DELETE_MU, + BEAMFORMING_NOTIFY_RESET +} BEAMFORMING_NOTIFY_STATE, *PBEAMFORMING_NOTIFY_STATE; + +typedef enum _BEAMFORMING_CAP { + BEAMFORMING_CAP_NONE = 0x0, + BEAMFORMER_CAP_HT_EXPLICIT = BIT1, + BEAMFORMEE_CAP_HT_EXPLICIT = BIT2, + BEAMFORMER_CAP_VHT_SU = BIT5, /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_SU = BIT6, /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP_VHT_MU = BIT7, /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_MU = BIT8, /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP = BIT9, + BEAMFORMEE_CAP = BIT10, +}BEAMFORMING_CAP, *PBEAMFORMING_CAP; + + +typedef enum _SOUNDING_MODE { + SOUNDING_SW_VHT_TIMER = 0x0, + SOUNDING_SW_HT_TIMER = 0x1, + SOUNDING_STOP_All_TIMER = 0x2, + SOUNDING_HW_VHT_TIMER = 0x3, + SOUNDING_HW_HT_TIMER = 0x4, + SOUNDING_STOP_OID_TIMER = 0x5, + SOUNDING_AUTO_VHT_TIMER = 0x6, + SOUNDING_AUTO_HT_TIMER = 0x7, + SOUNDING_FW_VHT_TIMER = 0x8, + SOUNDING_FW_HT_TIMER = 0x9, +}SOUNDING_MODE, *PSOUNDING_MODE; + +typedef struct _RT_BEAMFORM_STAINFO { + pu1Byte RA; + u2Byte AID; + u2Byte MacID; + WIRELESS_MODE WirelessMode; + CHANNEL_WIDTH BW; + BEAMFORMING_CAP BeamformCap; + u1Byte HtBeamformCap; + u2Byte VhtBeamformCap; + u1Byte CurBeamform; + u2Byte CurBeamformVHT; +} RT_BEAMFORM_STAINFO, *PRT_BEAMFORM_STAINFO; + + +typedef struct _RT_BEAMFORMEE_ENTRY { + BOOLEAN bUsed; + BOOLEAN bTxBF; + BOOLEAN bSound; + u2Byte AID; /*Used to construct AID field of NDPA packet.*/ + u2Byte MacId; /*Used to Set Reg42C in IBSS mode. */ + u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u2Byte G_ID; /*Used to fill Tx DESC*/ + u1Byte MacAddr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ + CHANNEL_WIDTH SoundBW; /*Sounding BandWidth*/ + u2Byte SoundPeriod; + BEAMFORMING_CAP BeamformEntryCap; + BEAMFORMING_ENTRY_STATE BeamformEntryState; + BOOLEAN bBeamformingInProgress; + /*u1Byte LogSeq; // Move to _RT_BEAMFORMER_ENTRY*/ + /*u2Byte LogRetryCnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ + /*u2Byte LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ + u2Byte LogStatusFailCnt:5; // 0~21 + u2Byte DefaultCSICnt:5; // 0~21 + u1Byte CSIMatrix[327]; + u2Byte CSIMatrixLen; + u1Byte NumofSoundingDim; + u1Byte CompSteeringNumofBFer; + u1Byte su_reg_index; + /*For MU-MIMO*/ + BOOLEAN is_mu_sta; + u1Byte mu_reg_index; + u1Byte gid_valid[8]; + u1Byte user_position[16]; +} RT_BEAMFORMEE_ENTRY, *PRT_BEAMFORMEE_ENTRY; + +typedef struct _RT_BEAMFORMER_ENTRY { + BOOLEAN bUsed; + /*P_AID of BFer entry is probably not used*/ + u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u2Byte G_ID; + u1Byte MacAddr[6]; + BEAMFORMING_CAP BeamformEntryCap; + u1Byte NumofSoundingDim; + u1Byte ClockResetTimes; /*Modified by Jeffery @2015-04-10*/ + u1Byte PreLogSeq; /*Modified by Jeffery @2015-03-30*/ + u1Byte LogSeq; /*Modified by Jeffery @2014-10-29*/ + u2Byte LogRetryCnt:3; /*Modified by Jeffery @2014-10-29*/ + u2Byte LogSuccess:2; /*Modified by Jeffery @2014-10-29*/ + u1Byte su_reg_index; + /*For MU-MIMO*/ + BOOLEAN is_mu_ap; + u1Byte gid_valid[8]; + u1Byte user_position[16]; + u2Byte AID; +} RT_BEAMFORMER_ENTRY, *PRT_BEAMFORMER_ENTRY; + +typedef struct _RT_SOUNDING_INFO { + u1Byte SoundIdx; + CHANNEL_WIDTH SoundBW; + SOUNDING_MODE SoundMode; + u2Byte SoundPeriod; +} RT_SOUNDING_INFO, *PRT_SOUNDING_INFO; + + + +typedef struct _RT_BEAMFORMING_OID_INFO { + u1Byte SoundOidIdx; + CHANNEL_WIDTH SoundOidBW; + SOUNDING_MODE SoundOidMode; + u2Byte SoundOidPeriod; +} RT_BEAMFORMING_OID_INFO, *PRT_BEAMFORMING_OID_INFO; + + +typedef struct _RT_BEAMFORMING_INFO { + BEAMFORMING_CAP BeamformCap; + RT_BEAMFORMEE_ENTRY BeamformeeEntry[BEAMFORMEE_ENTRY_NUM]; + RT_BEAMFORMER_ENTRY BeamformerEntry[BEAMFORMER_ENTRY_NUM]; + RT_BEAMFORM_STAINFO BeamformSTAinfo; + u1Byte BeamformeeCurIdx; + RT_TIMER BeamformingTimer; + RT_TIMER mu_timer; + RT_SOUNDING_INFO SoundingInfo; + RT_BEAMFORMING_OID_INFO BeamformingOidInfo; + HAL_TXBF_INFO TxbfInfo; + u1Byte SoundingSequence; + u1Byte beamformee_su_cnt; + u1Byte beamformer_su_cnt; + u4Byte beamformee_su_reg_maping; + u4Byte beamformer_su_reg_maping; + /*For MU-MINO*/ + u1Byte beamformee_mu_cnt; + u1Byte beamformer_mu_cnt; + u4Byte beamformee_mu_reg_maping; + u1Byte mu_ap_index; + BOOLEAN is_mu_sounding; + u1Byte FirstMUBFeeIndex; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER SourceAdapter; +#endif + /* Control register */ + u4Byte RegMUTxCtrl; /* For USB/SDIO interfaces aync I/O */ +} RT_BEAMFORMING_INFO, *PRT_BEAMFORMING_INFO; + + +typedef struct _RT_NDPA_STA_INFO { + u2Byte AID:12; + u2Byte FeedbackType:1; + u2Byte NcIndex:3; +} RT_NDPA_STA_INFO, *PRT_NDPA_STA_INFO; + +typedef enum _PHYDM_ACTING_TYPE { + PhyDM_ACTING_AS_IBSS = 0, + PhyDM_ACTING_AS_AP = 1 +} PHYDM_ACTING_TYPE; + + +BEAMFORMING_CAP +phydm_Beamforming_GetEntryBeamCapByMacId( + IN PVOID pDM_VOID, + IN u1Byte MacId + ); + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetBFeeEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte RA, + OUT pu1Byte Idx + ); + +PRT_BEAMFORMER_ENTRY +phydm_Beamforming_GetBFerEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte TA, + OUT pu1Byte Idx + ); + +u1Byte +Beamforming_GetHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +); + +u1Byte +Beamforming_GetVHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +); + +VOID +phydm_Beamforming_Notify( + IN PVOID pDM_VOID + ); + +BOOLEAN +phydm_actingDetermine( + IN PDM_ODM_T pDM_Odm, + IN PHYDM_ACTING_TYPE type + ); + +VOID +Beamforming_Enter( + IN PVOID pDM_VOID, + IN u2Byte staIdx + ); + +VOID +Beamforming_Leave( + IN PVOID pDM_VOID, + pu1Byte RA + ); + +BOOLEAN +BeamformingStart_FW( + IN PVOID pDM_VOID, + u1Byte Idx + ); + +VOID +Beamforming_CheckSoundingSuccess( + IN PVOID pDM_VOID, + BOOLEAN Status +); + +VOID +phydm_Beamforming_End_SW( + IN PVOID pDM_VOID, + BOOLEAN Status + ); + +VOID +Beamforming_TimerCallback( + IN PVOID pDM_VOID + ); + +VOID +phydm_Beamforming_Init( + IN PVOID pDM_VOID + ); + + + +BEAMFORMING_CAP +phydm_Beamforming_GetBeamCap( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo + ); + + +BOOLEAN +BeamformingControl_V1( + IN PVOID pDM_VOID, + pu1Byte RA, + u1Byte AID, + u1Byte Mode, + CHANNEL_WIDTH BW, + u1Byte Rate + ); + + +BOOLEAN +phydm_BeamformingControl_V2( + IN PVOID pDM_VOID, + u1Byte Idx, + u1Byte Mode, + CHANNEL_WIDTH BW, + u2Byte Period + ); + +VOID +phydm_Beamforming_Watchdog( + IN PVOID pDM_VOID + ); + +VOID +Beamforming_SWTimerCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PRT_TIMER pTimer +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + void *FunctionContext +#endif + ); + +BOOLEAN +Beamforming_SendHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ); + + +BOOLEAN +Beamforming_SendVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ); + +#else +#define Beamforming_GidPAid(Adapter, pTcb) +#define phydm_actingDetermine(pDM_Odm, type) FALSE +#define Beamforming_Enter(pDM_Odm, staIdx) +#define Beamforming_Leave(pDM_Odm, RA) +#define Beamforming_End_FW(pDMOdm) +#define BeamformingControl_V1(pDM_Odm, RA, AID, Mode, BW, Rate) TRUE +#define BeamformingControl_V2(pDM_Odm, Idx, Mode, BW, Period) TRUE +#define phydm_Beamforming_End_SW(pDM_Odm, _Status) +#define Beamforming_TimerCallback(pDM_Odm) +#define phydm_Beamforming_Init(pDM_Odm) +#define phydm_BeamformingControl_V2(pDM_Odm, _Idx, _Mode, _BW, _Period) FALSE +#define Beamforming_Watchdog(pDM_Odm) +#define phydm_Beamforming_Watchdog(pDM_Odm) + + +#endif +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_cfotracking.h b/network/wlan/WDI/HAL/phydm/phydm_cfotracking.h new file mode 100644 index 00000000..7eca3f6e --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_cfotracking.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMCFOTRACK_H__ +#define __PHYDMCFOTRACK_H__ + +#define CFO_TRACKING_VERSION "1.2" /*2015.06.17*/ + +#define CFO_TH_XTAL_HIGH 20 // kHz +#define CFO_TH_XTAL_LOW 10 // kHz +#define CFO_TH_ATC 80 // kHz + +typedef struct _CFO_TRACKING_ +{ + BOOLEAN bATCStatus; + BOOLEAN largeCFOHit; + BOOLEAN bAdjust; + u1Byte CrystalCap; + u1Byte DefXCap; + int CFO_tail[2]; + int CFO_ave_pre; + u4Byte packetCount; + u4Byte packetCount_pre; + + BOOLEAN bForceXtalCap; + BOOLEAN bReset; +}CFO_TRACKING, *PCFO_TRACKING; + +VOID +ODM_CfoTrackingReset( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTrackingInit( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTracking( + IN PVOID pDM_VOID +); + +VOID +ODM_ParsingCFO( + IN PVOID pDM_VOID, + IN PVOID pPktinfo_VOID, + IN s1Byte* pcfotail +); + +#endif
\ No newline at end of file diff --git a/network/wlan/WDI/HAL/phydm/phydm_debug.h b/network/wlan/WDI/HAL/phydm/phydm_debug.h new file mode 100644 index 00000000..5996cc7b --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_debug.h @@ -0,0 +1,331 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + +#define DEBUG_VERSION "1.0" /*2015.01.13 Dino*/ +//----------------------------------------------------------------------------- +// Define the debug levels +// +// 1. DBG_TRACE and DBG_LOUD are used for normal cases. +// So that, they can help SW engineer to develope or trace states changed +// and also help HW enginner to trace every operation to and from HW, +// e.g IO, Tx, Rx. +// +// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, +// which help us to debug SW or HW. +// +//----------------------------------------------------------------------------- +// +// Never used in a call to ODM_RT_TRACE()! +// +#define ODM_DBG_OFF 1 + +// +// Fatal bug. +// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, +// resource allocation failed, unexpected HW behavior, HW BUG and so on. +// +#define ODM_DBG_SERIOUS 2 + +// +// Abnormal, rare, or unexpeted cases. +// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. +// +#define ODM_DBG_WARNING 3 + +// +// Normal case with useful information about current SW or HW state. +// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, +// SW protocol state change, dynamic mechanism state change and so on. +// +#define ODM_DBG_LOUD 4 + +// +// Normal case with detail execution flow or information. +// +#define ODM_DBG_TRACE 5 + +/*FW DBG MSG*/ +#define RATE_DECISION BIT0 +#define INIT_RA_TABLE BIT1 +#define RATE_UP BIT2 +#define RATE_DOWN BIT3 +#define TRY_DONE BIT4 +#define F_RATE_AP_RPT BIT7 + +#define ODM_TMP_BUF_SIZE 100 +//----------------------------------------------------------------------------- +// Define the tracing components +// +//----------------------------------------------------------------------------- +//BB Functions +#define ODM_COMP_DIG BIT0 +#define ODM_COMP_RA_MASK BIT1 +#define ODM_COMP_DYNAMIC_TXPWR BIT2 +#define ODM_COMP_FA_CNT BIT3 +#define ODM_COMP_RSSI_MONITOR BIT4 +#define ODM_COMP_CCK_PD BIT5 +#define ODM_COMP_ANT_DIV BIT6 +#define ODM_COMP_PWR_SAVE BIT7 +#define ODM_COMP_PWR_TRAIN BIT8 +#define ODM_COMP_RATE_ADAPTIVE BIT9 +#define ODM_COMP_PATH_DIV BIT10 +#define ODM_COMP_PSD BIT11 +#define ODM_COMP_DYNAMIC_PRICCA BIT12 +#define ODM_COMP_RXHP BIT13 +#define ODM_COMP_MP BIT14 +#define ODM_COMP_CFO_TRACKING BIT15 +#define ODM_COMP_ACS BIT16 +#define PHYDM_COMP_ADAPTIVITY BIT17 +#define PHYDM_COMP_RA_DBG BIT18 +#define PHYDM_COMP_TXBF BIT19 +//MAC Functions +#define ODM_COMP_EDCA_TURBO BIT20 +#define ODM_COMP_EARLY_MODE BIT21 +#define ODM_FW_DEBUG_TRACE BIT22 +//RF Functions +#define ODM_COMP_TX_PWR_TRACK BIT24 +#define ODM_COMP_RX_GAIN_TRACK BIT25 +#define ODM_COMP_CALIBRATION BIT26 +//Common Functions +#define ODM_PHY_CONFIG BIT28 +#define BEAMFORMING_DEBUG BIT29 +#define ODM_COMP_COMMON BIT30 +#define ODM_COMP_INIT BIT31 +#define ODM_COMP_NOISY_DETECT BIT32 + +/*------------------------Export Marco Definition---------------------------*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define RT_PRINTK DbgPrint +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #define DbgPrint printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); + #define RT_DISP(dbgtype, dbgflag, printstr) +#else + #define DbgPrint panic_printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); +#endif + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#if DBG +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \ + { \ + if(pDM_Odm->SupportICType == ODM_RTL8192C) \ + DbgPrint("[ODM-92C] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8192D) \ + DbgPrint("[ODM-92D] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8723A) \ + DbgPrint("[ODM-8723A] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8188E) \ + DbgPrint("[ODM-8188E] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8192E) \ + DbgPrint("[ODM-8192E] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8812) \ + DbgPrint("[ODM-8812] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8821) \ + DbgPrint("[ODM-8821] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8814A) \ + DbgPrint("[ODM-8814] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8703B) \ + DbgPrint("[ODM-8703B] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8822B) \ + DbgPrint("[ODM-8822] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8188F) \ + DbgPrint("[ODM-8188F] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8723D) \ + DbgPrint("[ODM-8723D] "); \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if(!(expr)) { \ + DbgPrint( "Assertion failed! %s at ......\n", #expr); \ + DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ + RT_PRINTK fmt; \ + ASSERT(FALSE); \ + } +#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } +#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } +#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } + +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + int __i; \ + pu1Byte __ptr = (pu1Byte)ptr; \ + DbgPrint("[ODM] "); \ + DbgPrint(title_str); \ + DbgPrint(" "); \ + for( __i=0; __i<6; __i++ ) \ + DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ + DbgPrint("\n"); \ + } +#else +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) +#define ODM_dbg_enter() +#define ODM_dbg_exit() +#define ODM_dbg_trace(str) +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) +#endif + + +VOID +PHYDM_InitDebugSetting(IN PDM_ODM_T pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID phydm_BB_RxHang_Info(IN PDM_ODM_T pDM_Odm); +#endif + +#define BB_TMP_BUF_SIZE 100 +VOID phydm_BB_Debug_Info(IN PDM_ODM_T pDM_Odm); +VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define PHYDM_DBGPRINT 0 +#define PHYDM_SSCANF(x, y, z) DCMD_Scanf(x, y, z) +#if (PHYDM_DBGPRINT == 1) +#define PHYDM_SNPRINTF(msg) \ + do {\ + rsprintf msg;\ + DbgPrint(output);\ + } while (0) +#else +#define PHYDM_SNPRINTF(msg) \ + do {\ + rsprintf msg;\ + DCMD_Printf(output);\ + } while (0) +#endif +#else +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define PHYDM_DBGPRINT 0 +#else +#define PHYDM_DBGPRINT 1 +#endif +#define MAX_ARGC 20 +#define MAX_ARGV 16 +#define DCMD_DECIMAL "%d" +#define DCMD_CHAR "%c" +#define DCMD_HEX "%x" + +#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) +#if (PHYDM_DBGPRINT == 1) +#define PHYDM_SNPRINTF(msg)\ + do {\ + snprintf msg;\ + DbgPrint(output);\ + } while (0) +#else +#define PHYDM_SNPRINTF(msg)\ + do {\ + if(out_len > used)\ + used+=snprintf msg;\ + } while (0) +#endif +#endif + + +VOID phydm_BasicProfile( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) +s4Byte +phydm_cmd( + IN PDM_ODM_T pDM_Odm, + IN char *input, + IN u4Byte in_len, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +); +#endif +VOID +phydm_cmd_parser( + IN PDM_ODM_T pDM_Odm, + IN char input[][16], + IN u4Byte input_num, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_sbd_check( + IN PDM_ODM_T pDM_Odm + ); + +void phydm_sbd_callback( + PRT_TIMER pTimer + ); + +void phydm_sbd_workitem_callback( + IN PVOID pContext + ); +#endif + +VOID +phydm_fw_trace_en_h2c( + IN PVOID pDM_VOID, + IN BOOLEAN enable, + IN u4Byte monitor_mode, + IN u4Byte macid +); + +VOID +phydm_fw_trace_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +phydm_fw_trace_handler_code( + IN PVOID pDM_VOID, + IN pu1Byte Buffer, + IN u1Byte CmdLen +); + +VOID +phydm_fw_trace_handler_8051( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +#endif // __ODM_DBG_H__ + diff --git a/network/wlan/WDI/HAL/phydm/phydm_dig.h b/network/wlan/WDI/HAL/phydm/phydm_dig.h new file mode 100644 index 00000000..801369ae --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_dig.h @@ -0,0 +1,329 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDIG_H__ +#define __PHYDMDIG_H__ + +#define DIG_VERSION "1.7" /*2015.06.22, Changed by YuChen for adaptivity*/ + +/* Pause DIG & CCKPD */ +#define DM_DIG_MAX_PAUSE_TYPE 0x7 + +typedef struct _Dynamic_Initial_Gain_Threshold_ +{ + BOOLEAN bStopDIG; // for debug + BOOLEAN bIgnoreDIG; + BOOLEAN bPSDInProgress; + + u1Byte Dig_Enable_Flag; + u1Byte Dig_Ext_Port_Stage; + + int RssiLowThresh; + int RssiHighThresh; + + u4Byte FALowThresh; + u4Byte FAHighThresh; + + u1Byte CurSTAConnectState; + u1Byte PreSTAConnectState; + u1Byte CurMultiSTAConnectState; + + u1Byte PreIGValue; + u1Byte CurIGValue; + u1Byte BackupIGValue; //MP DIG + u1Byte BT30_CurIGI; + u1Byte IGIBackup; + + s1Byte BackoffVal; + s1Byte BackoffVal_range_max; + s1Byte BackoffVal_range_min; + u1Byte rx_gain_range_max; + u1Byte rx_gain_range_min; + u1Byte Rssi_val_min; + + u1Byte PreCCK_CCAThres; + u1Byte CurCCK_CCAThres; + u1Byte PreCCKPDState; + u1Byte CurCCKPDState; + u1Byte CCKPDBackup; + u1Byte pause_cckpd_level; + u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + + u1Byte LargeFAHit; + u1Byte ForbiddenIGI; + u4Byte Recover_cnt; + + u1Byte DIG_Dynamic_MIN_0; + u1Byte DIG_Dynamic_MIN_1; + BOOLEAN bMediaConnect_0; + BOOLEAN bMediaConnect_1; + + u4Byte AntDiv_RSSI_max; + u4Byte RSSI_max; + + u1Byte *bP2PInProcess; + + u1Byte pause_dig_level; + u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + BOOLEAN bTpTarget; + BOOLEAN bNoiseEst; + u4Byte TpTrainTH_min; + u1Byte IGIOffset_A; + u1Byte IGIOffset_B; +#endif + + u4Byte cckFaMa; +}DIG_T,*pDIG_T; + +typedef struct _FALSE_ALARM_STATISTICS{ + u4Byte Cnt_Parity_Fail; + u4Byte Cnt_Rate_Illegal; + u4Byte Cnt_Crc8_fail; + u4Byte Cnt_Mcs_fail; + u4Byte Cnt_Ofdm_fail; + u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A + u4Byte Cnt_Cck_fail; + u4Byte Cnt_all; + u4Byte Cnt_Fast_Fsync; + u4Byte Cnt_SB_Search_fail; + u4Byte Cnt_OFDM_CCA; + u4Byte Cnt_CCK_CCA; + u4Byte Cnt_CCA_all; + u4Byte Cnt_BW_USC; //Gary + u4Byte Cnt_BW_LSC; //Gary +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; + +typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition +{ + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_BACKOFF = 2, + DIG_TYPE_RX_GAIN_MIN = 3, + DIG_TYPE_RX_GAIN_MAX = 4, + DIG_TYPE_ENABLE = 5, + DIG_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}DM_DIG_OP_E; + +/* +typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition +{ + CCK_PD_STAGE_LowRssi = 0, + CCK_PD_STAGE_HighRssi = 1, + CCK_PD_STAGE_MAX = 3, +}DM_CCK_PDTH_E; + +typedef enum tag_DIG_EXT_PORT_ALGO_Definition +{ + DIG_EXT_PORT_STAGE_0 = 0, + DIG_EXT_PORT_STAGE_1 = 1, + DIG_EXT_PORT_STAGE_2 = 2, + DIG_EXT_PORT_STAGE_3 = 3, + DIG_EXT_PORT_STAGE_MAX = 4, +}DM_DIG_EXT_PORT_ALG_E; + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} + +#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) + +#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) +*/ + +typedef enum tag_PHYDM_Pause_Type { + PHYDM_PAUSE = BIT0, + PHYDM_RESUME = BIT1 +} PHYDM_PAUSE_TYPE; + +typedef enum tag_PHYDM_Pause_Level { +/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ + PHYDM_PAUSE_LEVEL_0 = 0, + PHYDM_PAUSE_LEVEL_1 = 1, + PHYDM_PAUSE_LEVEL_2 = 2, + PHYDM_PAUSE_LEVEL_3 = 3, + PHYDM_PAUSE_LEVEL_4 = 4, + PHYDM_PAUSE_LEVEL_5 = 5, + PHYDM_PAUSE_LEVEL_6 = 6, + PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ +} PHYDM_PAUSE_LEVEL; + + +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_FALSEALARM_THRESH_LOW 400 +#define DM_FALSEALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c +#define DM_DIG_MAX_OF_MIN_NIC 0x3e + +#define DM_DIG_MAX_AP 0x3e +#define DM_DIG_MIN_AP 0x1c +#define DM_DIG_MAX_OF_MIN 0x2A //0x32 +#define DM_DIG_MIN_AP_DFS 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define DM_DIG_MAX_AP_COVERAGR 0x26 +#define DM_DIG_MIN_AP_COVERAGE 0x1c +#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22 + +#define DM_DIG_TP_Target_TH0 500 +#define DM_DIG_TP_Target_TH1 1000 +#define DM_DIG_TP_Training_Period 10 +#endif + +//vivi 92c&92d has different definition, 20110504 +//this is for 92c +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + #define DM_DIG_FA_TH0 0x80//0x20 + #else + #define DM_DIG_FA_TH0 0x200//0x20 + #endif +#else + #define DM_DIG_FA_TH0 0x100//0x20 +#endif + +#define DM_DIG_FA_TH1 0x200 +#define DM_DIG_FA_TH2 0x300 +//this is for 92d +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps +#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps +#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps +#define RSSI_OFFSET_DIG 0x05 + +VOID +ODM_ChangeDynamicInitGainThresh( + IN PVOID pDM_VOID, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ); + +VOID +ODM_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurrentIGI + ); + +VOID +odm_PauseDIG( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte IGIValue + ); + +VOID +odm_DIGInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DIG( + IN PVOID pDM_VOID + ); + +VOID +odm_DIGbyRSSI_LPS( + IN PVOID pDM_VOID + ); + +VOID +odm_FalseAlarmCounterStatistics( + IN PVOID pDM_VOID + ); + +VOID +odm_PauseCCKPacketDetection( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte CCKPDThreshold + ); + +VOID +odm_CCKPacketDetectionThresh( + IN PVOID pDM_VOID + ); + +VOID +ODM_Write_CCK_CCA_Thres( + IN PVOID pDM_VOID, + IN u1Byte CurCCK_CCAThres + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +odm_MPT_DIGCallback( + PRT_TIMER pTimer +); + +VOID +odm_MPT_DIGWorkItemCallback( + IN PVOID pContext + ); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +VOID +odm_MPT_DIGCallback( + IN PVOID pDM_VOID +); +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) +VOID +ODM_MPT_DIG( + IN PVOID pDM_VOID +); +#endif + + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_dynamicbbpowersaving.h b/network/wlan/WDI/HAL/phydm/phydm_dynamicbbpowersaving.h new file mode 100644 index 00000000..365c1718 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_dynamicbbpowersaving.h @@ -0,0 +1,63 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ +#define __PHYDMDYNAMICBBPOWERSAVING_H__ + +#define DYNAMIC_BBPWRSAV_VERSION "1.0" + +typedef struct _Dynamic_Power_Saving_ +{ + u1Byte PreCCAState; + u1Byte CurCCAState; + + u1Byte PreRFState; + u1Byte CurRFState; + + int Rssi_val_min; + + u1Byte initialize; + u4Byte Reg874,RegC70,Reg85C,RegA74; + +}PS_T,*pPS_T; + +#define dm_RF_Saving ODM_RF_Saving + +void ODM_RF_Saving( + IN PVOID pDM_VOID, + IN u1Byte bForceInNormal +); + +VOID +odm_DynamicBBPowerSavingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicBBPowerSaving( + IN PVOID pDM_VOID + ); + +VOID +odm_1R_CCA( + IN PVOID pDM_VOID + ); + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_dynamictxpower.h b/network/wlan/WDI/HAL/phydm/phydm_dynamictxpower.h new file mode 100644 index 00000000..db61bf85 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_dynamictxpower.h @@ -0,0 +1,98 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICTXPOWER_H__ +#define __PHYDMDYNAMICTXPOWER_H__ + +/*#define DYNAMIC_TXPWR_VERSION "1.0"*/ +#define DYNAMIC_TXPWR_VERSION "1.1" /*2015.01.13*/ + +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F +#define TX_POWER_NEAR_FIELD_THRESH_8812 60 + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 + +VOID +odm_DynamicTxPowerInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerNIC( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PVOID pDM_VOID, + IN u1Byte Value); + +VOID +odm_DynamicTxPower_92C( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPower_92D( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPower_8821( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId + ); + +#endif + +VOID +odm_DynamicTxPower( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerAP( + IN PVOID pDM_VOID + ); + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_edcaturbocheck.h b/network/wlan/WDI/HAL/phydm/phydm_edcaturbocheck.h new file mode 100644 index 00000000..d4cd8d84 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_edcaturbocheck.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMEDCATURBOCHECK_H__ +#define __PHYDMEDCATURBOCHECK_H__ + +/*#define EDCATURBO_VERSION "2.1"*/ +#define EDCATURBO_VERSION "2.2" /*2015.01.13*/ + +typedef struct _EDCA_TURBO_ +{ + BOOLEAN bCurrentTurboEDCA; + BOOLEAN bIsCurRDLState; + + #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) + u4Byte prv_traffic_idx; // edca turbo + #endif + +}EDCA_T,*pEDCA_T; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) +{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; + + +static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx) +{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; + +static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP +{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; + +#endif + + + +VOID +odm_EdcaTurboCheck( + IN PVOID pDM_VOID + ); +VOID +ODM_EdcaTurboInit( + IN PVOID pDM_VOID +); + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) +VOID +odm_EdcaTurboCheckMP( + IN PVOID pDM_VOID + ); + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PVOID pDM_VOID +); +//choose edca paramter for special IOT case +VOID +ODM_EdcaParaSelByIot( + IN PVOID pDM_VOID, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ); +//check if it is UL or DL +VOID +odm_EdcaChooseTrafficIdx( + IN PVOID pDM_VOID, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ); + +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) +VOID +odm_EdcaTurboCheckCE( + IN PVOID pDM_VOID + ); +#endif + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_hwconfig.h b/network/wlan/WDI/HAL/phydm/phydm_hwconfig.h new file mode 100644 index 00000000..a61ed3bd --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_hwconfig.h @@ -0,0 +1,517 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + + +/*--------------------------Define -------------------------------------------*/ + +#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) +#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) + +#define AGC_DIFF_CONFIG(ic, band) do {\ + if (pDM_Odm->bIsMPChip)\ + AGC_DIFF_CONFIG_MP(ic,band);\ + else\ + AGC_DIFF_CONFIG_TC(ic,band);\ + } while(0) + + +//============================================================ +// structure and define +//============================================================ + +__PACK typedef struct _Phy_Rx_AGC_Info +{ + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain:7,trsw:1; + #else + u1Byte trsw:1,gain:7; + #endif +} __WLAN_ATTRIB_PACK__ PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T; + +__PACK typedef struct _Phy_Status_Rpt_8192cd { + PHY_RX_AGC_INFO_T path_agc[2]; + u1Byte ch_corr[2]; + u1Byte cck_sig_qual_ofdm_pwdb_all; + u1Byte cck_agc_rpt_ofdm_cfosho_a; + u1Byte cck_rpt_b_ofdm_cfosho_b; + u1Byte rsvd_1;/*ch_corr_msb;*/ + u1Byte noise_power_db_msb; + s1Byte path_cfotail[2]; + u1Byte pcts_mask[2]; + s1Byte stream_rxevm[2]; + u1Byte path_rxsnr[2]; + u1Byte noise_power_db_lsb; + u1Byte rsvd_2[3]; + u1Byte stream_csi[2]; + u1Byte stream_target_csi[2]; + s1Byte sig_evm; + u1Byte rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ + u1Byte sgi_en: 1; + u1Byte rxsc: 2; + u1Byte idle_long: 1; + u1Byte r_ant_train_en: 1; + u1Byte ant_sel_b: 1; + u1Byte ant_sel: 1; +#else /*_BIG_ENDIAN_ */ + u1Byte ant_sel: 1; + u1Byte ant_sel_b: 1; + u1Byte r_ant_train_en: 1; + u1Byte idle_long: 1; + u1Byte rxsc: 2; + u1Byte sgi_en: 1; + u1Byte antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ +#endif +} __WLAN_ATTRIB_PACK__ PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T; + + +typedef struct _Phy_Status_Rpt_8812 { +/* DWORD 0*/ + u1Byte gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u1Byte chl_num_LSB; /*channel number[7:0]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte chl_num_MSB: 2; /*channel number[9:8]*/ + u1Byte sub_chnl: 4; /*sub-channel location[3:0]*/ + u1Byte r_RFMOD: 2; /*RF mode[1:0]*/ +#else /*_BIG_ENDIAN_ */ + u1Byte r_RFMOD: 2; + u1Byte sub_chnl: 4; + u1Byte chl_num_MSB: 2; +#endif + +/* DWORD 1*/ + u1Byte pwdb_all; /*CCK signal quality / OFDM pwdb all*/ + s1Byte cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM Path-A and Path-B short CFO*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + /*this should be checked again because the definition of 8812 and 8814 is different*/ +/* u1Byte r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ +/* u1Byte cck_rx_path:4; cck rx path[3:0]*/ + u1Byte resvd_0: 6; + u1Byte bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ +#else /*_BIG_ENDIAN_*/ + u1Byte bt_RF_ch_MSB: 2; + u1Byte resvd_0: 6; +#endif + +/* DWORD 2*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ + u1Byte ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ + u1Byte bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ +#else /*_BIG_ENDIAN_ */ + u1Byte bt_RF_ch_LSB: 6; + u1Byte ant_div_sw_b: 1; + u1Byte ant_div_sw_a: 1; +#endif + s1Byte cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u1Byte PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u1Byte PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + +/* DWORD 3*/ + s1Byte rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s1Byte rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + +/* DWORD 4*/ + u1Byte PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ + u1Byte pcts_rpt_valid: 1; /*pcts_rpt_valid*/ + u1Byte resvd_1: 1; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u1Byte resvd_1: 1; + u1Byte pcts_rpt_valid: 1; + u1Byte PCTS_MSK_RPT_3: 6; +#endif + s1Byte rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ + +/* DWORD 5*/ + u1Byte csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ + u1Byte gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ + +/* DWORD 6*/ + s1Byte sigevm; /*signal field EVM*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u1Byte antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u1Byte dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u1Byte GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ +#else /*_BIG_ENDIAN_*/ + u1Byte GNT_BT_keep: 1; + u1Byte dpdt_ctrl_keep: 1; + u1Byte antidx_antd: 3; + u1Byte antidx_antc: 3; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_anta: 3; /*antidx_anta[2:0]*/ + u1Byte antidx_antb: 3; /*antidx_antb[2:0]*/ + u1Byte hw_antsw_occur: 2; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u1Byte hw_antsw_occur: 2; + u1Byte antidx_antb: 3; + u1Byte antidx_anta: 3; +#endif +} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T; + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm + ); + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ); + +VOID +ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ); + +HAL_STATUS +ODM_ConfigRFWithTxPwrTrackHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_Config_Type ConfigType, + IN ODM_RF_RADIO_PATH_E eRFPath + ); + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ); + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + +HAL_STATUS +ODM_ConfigFWWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_FW_Config_Type ConfigType, + OUT u1Byte *pFirmware, + OUT u4Byte *pSize + ); + +u4Byte +ODM_GetHWImgVersion( + IN PDM_ODM_T pDM_Odm + ); + +s4Byte +odm_SignalScaleMapping( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig + ); + +#if (RTL8822B_SUPPORT == 1) +/*For 8822B only!! need to move to FW finally */ +/*==============================================*/ +VOID +phydm_RxPhyStatusJaguarSeries2( + IN PDM_ODM_T pPhydm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +); + +typedef struct _Phy_Status_Rpt_Jaguar2_Type0 { + /* DW0 */ + u1Byte page_num; + u1Byte pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain: 6; + u1Byte rsvd_0: 1; + u1Byte trsw: 1; +#else + u1Byte trsw: 1; + u1Byte rsvd_0: 1; + u1Byte gain: 6; +#endif + u1Byte rsvd_1; + + /* DW1 */ + u1Byte rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte rxsc: 4; + u1Byte agc_table: 4; +#else + u1Byte agc_table: 4; + u1Byte rxsc: 4; +#endif + u1Byte channel; + u1Byte band; + + /* DW2 */ + u2Byte length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_3: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_4:2; +#else + u1Byte rsvd_3: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_4:2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte vga:5; + u1Byte lna_l:3; + u1Byte bb_power:6; + u1Byte rsvd_9:1; + u1Byte lna_h:1; +#else + u1Byte lna_l:3; + u1Byte vga:5; + u1Byte lna_h:1; + u1Byte rsvd_9:1; + u1Byte bb_power:6; +#endif + u1Byte rsvd_5; + + /* DW4 */ + u4Byte rsvd_6; + + /* DW5 */ + u4Byte rsvd_7; + + /* DW6 */ + u4Byte rsvd_8; +} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; + +typedef struct _Phy_Status_Rpt_Jaguar2_Type1 { + /* DW0 and DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ + u2Byte lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_1: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_2: 2; +#else + u1Byte rsvd_1: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_2: 2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte paid_msb: 1; + u1Byte gid: 6; + u1Byte rsvd_3: 1; +#else + u1Byte rsvd_3: 1; + u1Byte gid: 6; + u1Byte paid_msb: 1; +#endif + u1Byte intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte intf_pos_msb: 1; + u1Byte rsvd_4: 2; + u1Byte nb_intf_flag: 1; + u1Byte rf_mode: 2; + u1Byte rsvd_5: 2; +#else + u1Byte rsvd_5: 2; + u1Byte rf_mode: 2; + u1Byte nb_intf_flag: 1; + u1Byte rsvd_4: 2; + u1Byte intf_pos_msb: 1; +#endif + + /* DW4 */ + s1Byte rxevm[4]; /* s(8,1) */ + + /* DW5 */ + s1Byte cfo_tail[4]; /* s(8,7) */ + + /* DW6 */ + s1Byte rxsnr[4]; /* s(8,1) */ +} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1; + +typedef struct _Phy_Status_Rpt_Jaguar2_Type2 { + /* DW0 ane DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte shift_l_map: 6; + u1Byte rsvd_1: 2; +#else + u1Byte rsvd_1: 2; + u1Byte shift_l_map: 6; +#endif + u1Byte cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte agc_table_a: 4; + u1Byte agc_table_b: 4; + u1Byte agc_table_c: 4; + u1Byte agc_table_d: 4; +#else + u1Byte agc_table_b: 4; + u1Byte agc_table_a: 4; + u1Byte agc_table_d: 4; + u1Byte agc_table_c: 4; +#endif + + /* DW3 ~ DW6*/ + u1Byte cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain_a: 6; + u1Byte rsvd_2: 1; + u1Byte trsw_a: 1; + u1Byte gain_b: 6; + u1Byte rsvd_3: 1; + u1Byte trsw_b: 1; + u1Byte gain_c: 6; + u1Byte rsvd_4: 1; + u1Byte trsw_c: 1; + u1Byte gain_d: 6; + u1Byte rsvd_5: 1; + u1Byte trsw_d: 1; + u1Byte aagc_step_a: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_d: 2; +#else + u1Byte trsw_a: 1; + u1Byte rsvd_2: 1; + u1Byte gain_a: 6; + u1Byte trsw_b: 1; + u1Byte rsvd_3: 1; + u1Byte gain_b: 6; + u1Byte trsw_c: 1; + u1Byte rsvd_4: 1; + u1Byte gain_c: 6; + u1Byte trsw_d: 1; + u1Byte rsvd_5: 1; + u1Byte gain_d: 6; + u1Byte aagc_step_d: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_a: 2; +#endif + u1Byte ht_aagc_gain[4]; + u1Byte dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte counter: 6; + u1Byte rsvd_6: 2; + u1Byte syn_count: 5; + u1Byte rsvd_7:3; +#else + u1Byte rsvd_6: 2; + u1Byte counter: 6; + u1Byte rsvd_7:3; + u1Byte syn_count: 5; +#endif +} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2; +/*==============================================*/ +#endif +#endif + diff --git a/network/wlan/WDI/HAL/phydm/phydm_interface.h b/network/wlan/WDI/HAL/phydm/phydm_interface.h new file mode 100644 index 00000000..e1433ffe --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_interface.h @@ -0,0 +1,434 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + +#define INTERFACE_VERSION "1.0" /*2015.01.13 Dino*/ + +// +// =========== Constant/Structure/Enum/... Define +// + + + +// +// =========== Macro Define +// + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +// _cat: implemented by Token-Pasting Operator. +#if 0 +#define _cat(_name, _ic_type, _func) \ + ( \ + _func##_all(_name) \ + ) +#endif + +/*=================================== + +#define ODM_REG_DIG_11N 0xC50 +#define ODM_REG_DIG_11AC 0xDDD + +ODM_REG(DIG,_pDM_Odm) +=====================================*/ + +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + +#ifdef __ECOS +#define _rtk_cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#else + +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#endif +/* +// only sample code +//#define _cat(_name, _ic_type, _func) \ +// ( \ +// ((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \ +// ((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \ +// ((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \ +// ((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \ +// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ +// _func##_ic(_name, _8195) \ +// ) +*/ + +// _name: name of register or bit. +// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" +// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. +#ifdef __ECOS +#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit) +#else +#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) +#endif +typedef enum _PHYDM_H2C_CMD +{ + ODM_H2C_RSSI_REPORT = 0, + ODM_H2C_PSD_RESULT = 1, + ODM_H2C_PathDiv = 2, + ODM_H2C_WIFI_CALIBRATION = 3, + ODM_H2C_IQ_CALIBRATION = 4, + ODM_H2C_RA_PARA_ADJUST = 5, + PHYDM_H2C_DYNAMIC_TX_PATH = 6, + PHYDM_H2C_FW_TRACE_EN = 7, + PHYDM_H2C_TXBF = 8, + ODM_MAX_H2CCMD +}PHYDM_H2C_CMD; + +typedef enum _PHYDM_C2H_EVT +{ + PHYDM_C2H_DBG = 0, + PHYDM_C2H_LB = 1, + PHYDM_C2H_XBF = 2, + PHYDM_C2H_TX_REPORT = 3, + PHYDM_C2H_INFO = 9, + PHYDM_C2H_BT_MP = 11, + PHYDM_C2H_RA_RPT = 12, + PHYDM_C2H_RA_PARA_RPT=14, + PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, + PHYDM_C2H_IQK_FINISH = 17, //0x11 + PHYDM_C2H_DBG_CODE = 0xFE, + PHYDM_C2H_EXTEND = 0xFF, +}PHYDM_C2H_EVT; + +typedef enum _PHYDM_EXTEND_C2H_EVT +{ + PHYDM_EXTEND_C2H_DBG_PRINT = 0 + +}PHYDM_EXTEND_C2H_EVT; + + +// +// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. +// Suggest HW team to use thread instead of workitem. Windows also support the feature. +// +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef void *PRT_WORK_ITEM ; +typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; +typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); + +#if 0 +typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; + +typedef struct _RT_WORK_ITEM +{ + + RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. + PVOID Adapter; // Pointer to Adapter object. + PVOID pContext; // Parameter to passed to CallBackFunc(). + RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. + u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. + PVOID pPlatformExt; // Pointer to platform-dependent extension. + BOOLEAN bFree; + char szID[36]; // An identity string of this workitem. +}RT_WORK_ITEM, *PRT_WORK_ITEM; + +#endif + + +#endif + +// +// =========== Extern Variable ??? It should be forbidden. +// + + +// +// =========== EXtern Function Prototype +// + + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ); + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ); + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ); + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + + +// +// Memory Relative Function. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ); +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ); + +VOID +ODM_MoveMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pDest, + IN PVOID pSrc, + IN u4Byte Length + ); + +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ); + +void ODM_Memory_Set + (IN PDM_ODM_T pDM_Odm, + IN PVOID pbuf, + IN s1Byte value, + IN u4Byte length); + +// +// ODM MISC-spin lock relative API. +// +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + + +// +// ODM MISC-workitem relative API. +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ); + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ); + +VOID +ODM_delay_ms(IN u4Byte ms); + + + +VOID +ODM_delay_us(IN u4Byte us); + +VOID +ODM_sleep_ms(IN u4Byte ms); + +VOID +ODM_sleep_us(IN u4Byte us); + +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ); + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +// +// ODM FW relative API. +// +VOID +ODM_FillH2CCmd( + IN PDM_ODM_T pDM_Odm, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +u1Byte +phydm_c2H_content_parsing( + IN PVOID pDM_VOID, + IN u1Byte c2hCmdId, + IN u1Byte c2hCmdLen, + IN pu1Byte tmpBuf +); + +u8Byte +ODM_GetCurrentTime( + IN PDM_ODM_T pDM_Odm + ); +u8Byte +ODM_GetProgressingTime( + IN PDM_ODM_T pDM_Odm, + IN u8Byte Start_Time + ); + +#endif // __ODM_INTERFACE_H__ + diff --git a/network/wlan/WDI/HAL/phydm/phydm_noisemonitor.h b/network/wlan/WDI/HAL/phydm/phydm_noisemonitor.h new file mode 100644 index 00000000..022cefe2 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_noisemonitor.h @@ -0,0 +1,49 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + *****************************************************************************/ +#ifndef __ODMNOISEMONITOR_H__ +#define __ODMNOISEMONITOR_H__ + +#define ODM_MAX_CHANNEL_NUM 38//14+24 +struct noise_level +{ + //u1Byte value_a, value_b; + u1Byte value[MAX_RF_PATH]; + //s1Byte sval_a, sval_b; + s1Byte sval[MAX_RF_PATH]; + + //s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0; + //s4Byte noise[ODM_RF_PATH_MAX]; + s4Byte sum[MAX_RF_PATH]; + //u1Byte valid_cnt_a=0, valid_cnt_b=0, + u1Byte valid[MAX_RF_PATH]; + u1Byte valid_cnt[MAX_RF_PATH]; + +}; + + +typedef struct _ODM_NOISE_MONITOR_ +{ + s1Byte noise[MAX_RF_PATH]; + s2Byte noise_all; +}ODM_NOISE_MONITOR; + +s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time); + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_pathdiv.h b/network/wlan/WDI/HAL/phydm/phydm_pathdiv.h new file mode 100644 index 00000000..020288ea --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_pathdiv.h @@ -0,0 +1,324 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPATHDIV_H__ +#define __PHYDMPATHDIV_H__ +/*#define PATHDIV_VERSION "2.0" //2014.11.04*/ +#define PATHDIV_VERSION "3.0" /*2015.01.13 Dino*/ + +#if(defined(CONFIG_PATH_DIVERSITY)) +#define USE_PATH_A_AS_DEFAULT_ANT //for 8814 dynamic TX path selection + +#define NUM_RESET_DTP_PERIOD 5 +#define ANT_DECT_RSSI_TH 3 + +#define PATH_A 1 +#define PATH_B 2 +#define PATH_C 3 +#define PATH_D 4 + +#define PHYDM_AUTO_PATH 0 +#define PHYDM_FIX_PATH 1 + +#define NUM_CHOOSE2_FROM4 6 +#define NUM_CHOOSE3_FROM4 4 + + +#define PHYDM_A BIT0 +#define PHYDM_B BIT1 +#define PHYDM_C BIT2 +#define PHYDM_D BIT3 +#define PHYDM_AB (BIT0 | BIT1) // 0 +#define PHYDM_AC (BIT0 | BIT2) // 1 +#define PHYDM_AD (BIT0 | BIT3) // 2 +#define PHYDM_BC (BIT1 | BIT2) // 3 +#define PHYDM_BD (BIT1 | BIT3) // 4 +#define PHYDM_CD (BIT2 | BIT3) // 5 + +#define PHYDM_ABC (BIT0 | BIT1 | BIT2) /* 0*/ +#define PHYDM_ABD (BIT0 | BIT1 | BIT3) /* 1*/ +#define PHYDM_ACD (BIT0 | BIT2 | BIT3) /* 2*/ +#define PHYDM_BCD (BIT1 | BIT2 | BIT3) /* 3*/ + +#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) + + +typedef enum dtp_state +{ + PHYDM_DTP_INIT=1, + PHYDM_DTP_RUNNING_1 + +}PHYDM_DTP_STATE; + +typedef enum path_div_type +{ + PHYDM_2R_PATH_DIV = 1, + PHYDM_4R_PATH_DIV = 2 +}PHYDM_PATH_DIV_TYPE; + +VOID +phydm_process_rssi_for_path_div( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + ); + +typedef struct _ODM_PATH_DIVERSITY_ +{ + u1Byte RespTxPath; + u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte path_div_type; + #if RTL8814A_SUPPORT + + u4Byte path_a_sum_all; + u4Byte path_b_sum_all; + u4Byte path_c_sum_all; + u4Byte path_d_sum_all; + + u4Byte path_a_cnt_all; + u4Byte path_b_cnt_all; + u4Byte path_c_cnt_all; + u4Byte path_d_cnt_all; + + u1Byte dtp_period; + BOOLEAN bBecomeLinked; + BOOLEAN is_u3_mode; + u1Byte num_tx_path; + u1Byte default_path; + u1Byte num_candidate; + u1Byte ant_candidate_1; + u1Byte ant_candidate_2; + u1Byte ant_candidate_3; + u1Byte dtp_state; + u1Byte dtp_check_patha_counter; + BOOLEAN fix_path_bfer; + u1Byte search_space_2[NUM_CHOOSE2_FROM4]; + u1Byte search_space_3[NUM_CHOOSE3_FROM4]; + + u1Byte pre_tx_path; + u1Byte use_path_a_as_default_ant; + BOOLEAN is_pathA_exist; + + #endif +}PATHDIV_T, *pPATHDIV_T; + + +#endif //#if(defined(CONFIG_PATH_DIVERSITY)) + +VOID +phydm_c2h_dtp_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen + ); + +VOID +odm_PathDiversityInit( + IN PVOID pDM_VOID + ); + +VOID +odm_PathDiversity( + IN PVOID pDM_VOID + ); + +VOID +odm_pathdiv_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + + + +//1 [OLD IC]-------------------------------------------------------------------------------- + + + + + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +//#define PATHDIV_ENABLE 1 +#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi +#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C + + + + +typedef struct _PathDiv_Parameter_define_ +{ + u4Byte org_5g_RegE30; + u4Byte org_5g_RegC14; + u4Byte org_5g_RegCA0; + u4Byte swt_5g_RegE30; + u4Byte swt_5g_RegC14; + u4Byte swt_5g_RegCA0; + //for 2G IQK information + u4Byte org_2g_RegC80; + u4Byte org_2g_RegC4C; + u4Byte org_2g_RegC94; + u4Byte org_2g_RegC14; + u4Byte org_2g_RegCA0; + + u4Byte swt_2g_RegC80; + u4Byte swt_2g_RegC4C; + u4Byte swt_2g_RegC94; + u4Byte swt_2g_RegC14; + u4Byte swt_2g_RegCA0; +}PATHDIV_PARA,*pPATHDIV_PARA; + +VOID +odm_PathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_2TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_1TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +odm_IsConnected_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +ODM_PathDiversityBeforeLink92C( + //IN PADAPTER Adapter + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_PathDiversityAfterLink_92C( + IN PADAPTER Adapter + ); + +VOID +odm_SetRespPath_92C( + IN PADAPTER Adapter, + IN u1Byte DefaultRespPath + ); + +VOID +odm_OFDMTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_ResetPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer + ); + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ); + +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer + ); + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ); + + +VOID +odm_PathDivChkAntSwitch( + PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CCKPathDiversityChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd, + pu1Byte pDesc + ); + +VOID +ODM_PathDivChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd + ); + +VOID +ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_FillTXPathInTXDESC( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN pu1Byte pDesc + ); + +VOID +odm_PathDivInit_92D( + IN PDM_ODM_T pDM_Odm + ); + +u1Byte +odm_SwAntDivSelectScanChnl( + IN PADAPTER Adapter + ); + +VOID +odm_SwAntDivConstructScanChnl( + IN PADAPTER Adapter, + IN u1Byte ScanChnl + ); + + #endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + + #endif //#ifndef __ODMPATHDIV_H__ + diff --git a/network/wlan/WDI/HAL/phydm/phydm_powertracking_ap.h b/network/wlan/WDI/HAL/phydm/phydm_powertracking_ap.h new file mode 100644 index 00000000..80dbcea2 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_powertracking_ap.h @@ -0,0 +1,313 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.0" + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifdef RTK_AC_SUPPORT +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#else +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#endif +#else +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 +#if (RTL8192D_SUPPORT==1) +#define IQK_BB_REG_NUM 10 +#else +#define IQK_BB_REG_NUM 9 +#endif +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +//#define IQK_Matrix_Settings_NUM 1+24+21 +#define IQK_Matrix_Settings_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G + +#if !defined(_OUTSRC_COEXIST) +#define OFDM_TABLE_SIZE_92D 43 +#define OFDM_TABLE_SIZE 37 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 + + + +//#define OFDM_TABLE_SIZE_92E 54 +//#define CCK_TABLE_SIZE_92E 54 +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; + +#endif + +#define ODM_OFDM_TABLE_SIZE 37 +#define ODM_CCK_TABLE_SIZE 33 +// <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +extern u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE]; +extern u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE]; + + +//extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; +//extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; +//extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; + +#ifdef CONFIG_WLAN_HAL_8192EE +#define OFDM_TABLE_SIZE_92E 54 +#define CCK_TABLE_SIZE_92E 54 +extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; +extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; +extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; +#endif + +#define OFDM_TABLE_SIZE_8812 43 +#define AVG_THERMAL_NUM_8812 4 + +#if(RTL8814A_SUPPORT == 1) +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; +#elif(ODM_IC_11AC_SERIES_SUPPORT) +extern unsigned int OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812]; +#endif + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[1][IQK_Matrix_REG_NUM]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + //u1Byte bTXPowerTracking; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + BOOLEAN bDPKenable; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset; + s1Byte DeltaPowerIndex; + s1Byte DeltaPowerIndexLast; + BOOLEAN bTxPowerChanged; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + BOOLEAN bNeedIQK; + u1Byte Delta_IQK; + u1Byte Delta_LCK; + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + + + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_powertracking_ce.h b/network/wlan/WDI/HAL/phydm/phydm_powertracking_ce.h new file mode 100644 index 00000000..4d22d1c1 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_powertracking_ce.h @@ -0,0 +1,298 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.0" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 + +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 4 + +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 +#if (RTL8192D_SUPPORT==1) +#define IQK_BB_REG_NUM 10 +#else +#define IQK_BB_REG_NUM 9 +#endif + + +#define IQK_Matrix_REG_NUM 8 +#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G + +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; + + +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; + +// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[3][IQK_Matrix_REG_NUM]; + BOOLEAN bBWIqkResultSaved[3]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + + //------------------------- Tx power Tracking -------------------------// + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset[MAX_RF_PATH]; + s1Byte DeltaPowerIndex[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; + BOOLEAN bTxPowerChanged; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} + u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} + u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + + + // <James> IQK time measurement + u8Byte IQK_StartTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + + // DPK + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[4]; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_powertracking_win.h b/network/wlan/WDI/HAL/phydm/phydm_powertracking_win.h new file mode 100644 index 00000000..f4eac12e --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_powertracking_win.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.0" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define CCK_TABLE_SIZE_88F 21 + + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#if (RTL8192D_SUPPORT==1) +#define IQK_BB_REG_NUM 10 +#else +#define IQK_BB_REG_NUM 9 +#endif + +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; +extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; + +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; + +// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[3][IQK_Matrix_REG_NUM]; + BOOLEAN bBWIqkResultSaved[3]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + //u1Byte bTXPowerTracking; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + + //------------------------- Tx power Tracking -------------------------// + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset[MAX_RF_PATH]; + s1Byte DeltaPowerIndex[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; + BOOLEAN bTxPowerChanged; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u4Byte TxIQC_8723D[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8723D[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + + + // <James> IQK time measurement + u8Byte IQK_StartTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + + // DPK + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[2]; + + s1Byte Modify_TxAGC_Value_OFDM; + s1Byte Modify_TxAGC_Value_CCK; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + + + + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_pre_define.h b/network/wlan/WDI/HAL/phydm/phydm_pre_define.h new file mode 100644 index 00000000..f3b5733d --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_pre_define.h @@ -0,0 +1,617 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __PHYDMPREDEFINE_H__ +#define __PHYDMPREDEFINE_H__ + +//1 ============================================================ +//1 Definition +//1 ============================================================ + +//Max path of IC +#define MAX_PATH_NUM_92CS 2 +#define MAX_PATH_NUM_8188E 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8723B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8814A 4 +#define MAX_PATH_NUM_8822B 2 +#define MAX_PATH_NUM_8821B 2 +#define MAX_PATH_NUM_8703B 1 +#define MAX_PATH_NUM_8723D 1 +#define MAX_PATH_NUM_8188F 1 + +//Max RF path +#define ODM_RF_PATH_MAX 2 +#define ODM_RF_PATH_MAX_JAGUAR 4 + +//number of entry +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/ + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + #define ASSOCIATE_ENTRY_NUM NUM_STAT + #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1) +#else + #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) +#endif + +/* -----MGN rate--------------------------------- */ + +#define ODM_MGN_1M 0x02 +#define ODM_MGN_2M 0x04 +#define ODM_MGN_5_5M 0x0b +#define ODM_MGN_11M 0x16 + +#define ODM_MGN_6M 0x0c +#define ODM_MGN_9M 0x12 +#define ODM_MGN_12M 0x18 +#define ODM_MGN_18M 0x24 +#define ODM_MGN_24M 0x30 +#define ODM_MGN_36M 0x48 +#define ODM_MGN_48M 0x60 +#define ODM_MGN_54M 0x6c + +/*TxHT = 1*/ +#define ODM_MGN_MCS0 0x80 +#define ODM_MGN_MCS1 0x81 +#define ODM_MGN_MCS2 0x82 +#define ODM_MGN_MCS3 0x83 +#define ODM_MGN_MCS4 0x84 +#define ODM_MGN_MCS5 0x85 +#define ODM_MGN_MCS6 0x86 +#define ODM_MGN_MCS7 0x87 +#define ODM_MGN_MCS8 0x88 +#define ODM_MGN_MCS9 0x89 +#define ODM_MGN_MCS10 0x8a +#define ODM_MGN_MCS11 0x8b +#define ODM_MGN_MCS12 0x8c +#define ODM_MGN_MCS13 0x8d +#define ODM_MGN_MCS14 0x8e +#define ODM_MGN_MCS15 0x8f +#define ODM_MGN_VHT1SS_MCS0 0x90 +#define ODM_MGN_VHT1SS_MCS1 0x91 +#define ODM_MGN_VHT1SS_MCS2 0x92 +#define ODM_MGN_VHT1SS_MCS3 0x93 +#define ODM_MGN_VHT1SS_MCS4 0x94 +#define ODM_MGN_VHT1SS_MCS5 0x95 +#define ODM_MGN_VHT1SS_MCS6 0x96 +#define ODM_MGN_VHT1SS_MCS7 0x97 +#define ODM_MGN_VHT1SS_MCS8 0x98 +#define ODM_MGN_VHT1SS_MCS9 0x99 +#define ODM_MGN_VHT2SS_MCS0 0x9a +#define ODM_MGN_VHT2SS_MCS1 0x9b +#define ODM_MGN_VHT2SS_MCS2 0x9c +#define ODM_MGN_VHT2SS_MCS3 0x9d +#define ODM_MGN_VHT2SS_MCS4 0x9e +#define ODM_MGN_VHT2SS_MCS5 0x9f +#define ODM_MGN_VHT2SS_MCS6 0xa0 +#define ODM_MGN_VHT2SS_MCS7 0xa1 +#define ODM_MGN_VHT2SS_MCS8 0xa2 +#define ODM_MGN_VHT2SS_MCS9 0xa3 + +#define ODM_MGN_MCS0_SG 0xc0 +#define ODM_MGN_MCS1_SG 0xc1 +#define ODM_MGN_MCS2_SG 0xc2 +#define ODM_MGN_MCS3_SG 0xc3 +#define ODM_MGN_MCS4_SG 0xc4 +#define ODM_MGN_MCS5_SG 0xc5 +#define ODM_MGN_MCS6_SG 0xc6 +#define ODM_MGN_MCS7_SG 0xc7 +#define ODM_MGN_MCS8_SG 0xc8 +#define ODM_MGN_MCS9_SG 0xc9 +#define ODM_MGN_MCS10_SG 0xca +#define ODM_MGN_MCS11_SG 0xcb +#define ODM_MGN_MCS12_SG 0xcc +#define ODM_MGN_MCS13_SG 0xcd +#define ODM_MGN_MCS14_SG 0xce +#define ODM_MGN_MCS15_SG 0xcf + +/* -----DESC rate--------------------------------- */ + +#define ODM_RATEMCS15_SG 0x1c +#define ODM_RATEMCS32 0x20 + + +// CCK Rates, TxHT = 0 +#define ODM_RATE1M 0x00 +#define ODM_RATE2M 0x01 +#define ODM_RATE5_5M 0x02 +#define ODM_RATE11M 0x03 +// OFDM Rates, TxHT = 0 +#define ODM_RATE6M 0x04 +#define ODM_RATE9M 0x05 +#define ODM_RATE12M 0x06 +#define ODM_RATE18M 0x07 +#define ODM_RATE24M 0x08 +#define ODM_RATE36M 0x09 +#define ODM_RATE48M 0x0A +#define ODM_RATE54M 0x0B +// MCS Rates, TxHT = 1 +#define ODM_RATEMCS0 0x0C +#define ODM_RATEMCS1 0x0D +#define ODM_RATEMCS2 0x0E +#define ODM_RATEMCS3 0x0F +#define ODM_RATEMCS4 0x10 +#define ODM_RATEMCS5 0x11 +#define ODM_RATEMCS6 0x12 +#define ODM_RATEMCS7 0x13 +#define ODM_RATEMCS8 0x14 +#define ODM_RATEMCS9 0x15 +#define ODM_RATEMCS10 0x16 +#define ODM_RATEMCS11 0x17 +#define ODM_RATEMCS12 0x18 +#define ODM_RATEMCS13 0x19 +#define ODM_RATEMCS14 0x1A +#define ODM_RATEMCS15 0x1B +#define ODM_RATEMCS16 0x1C +#define ODM_RATEMCS17 0x1D +#define ODM_RATEMCS18 0x1E +#define ODM_RATEMCS19 0x1F +#define ODM_RATEMCS20 0x20 +#define ODM_RATEMCS21 0x21 +#define ODM_RATEMCS22 0x22 +#define ODM_RATEMCS23 0x23 +#define ODM_RATEMCS24 0x24 +#define ODM_RATEMCS25 0x25 +#define ODM_RATEMCS26 0x26 +#define ODM_RATEMCS27 0x27 +#define ODM_RATEMCS28 0x28 +#define ODM_RATEMCS29 0x29 +#define ODM_RATEMCS30 0x2A +#define ODM_RATEMCS31 0x2B +#define ODM_RATEVHTSS1MCS0 0x2C +#define ODM_RATEVHTSS1MCS1 0x2D +#define ODM_RATEVHTSS1MCS2 0x2E +#define ODM_RATEVHTSS1MCS3 0x2F +#define ODM_RATEVHTSS1MCS4 0x30 +#define ODM_RATEVHTSS1MCS5 0x31 +#define ODM_RATEVHTSS1MCS6 0x32 +#define ODM_RATEVHTSS1MCS7 0x33 +#define ODM_RATEVHTSS1MCS8 0x34 +#define ODM_RATEVHTSS1MCS9 0x35 +#define ODM_RATEVHTSS2MCS0 0x36 +#define ODM_RATEVHTSS2MCS1 0x37 +#define ODM_RATEVHTSS2MCS2 0x38 +#define ODM_RATEVHTSS2MCS3 0x39 +#define ODM_RATEVHTSS2MCS4 0x3A +#define ODM_RATEVHTSS2MCS5 0x3B +#define ODM_RATEVHTSS2MCS6 0x3C +#define ODM_RATEVHTSS2MCS7 0x3D +#define ODM_RATEVHTSS2MCS8 0x3E +#define ODM_RATEVHTSS2MCS9 0x3F +#define ODM_RATEVHTSS3MCS0 0x40 +#define ODM_RATEVHTSS3MCS1 0x41 +#define ODM_RATEVHTSS3MCS2 0x42 +#define ODM_RATEVHTSS3MCS3 0x43 +#define ODM_RATEVHTSS3MCS4 0x44 +#define ODM_RATEVHTSS3MCS5 0x45 +#define ODM_RATEVHTSS3MCS6 0x46 +#define ODM_RATEVHTSS3MCS7 0x47 +#define ODM_RATEVHTSS3MCS8 0x48 +#define ODM_RATEVHTSS3MCS9 0x49 +#define ODM_RATEVHTSS4MCS0 0x4A +#define ODM_RATEVHTSS4MCS1 0x4B +#define ODM_RATEVHTSS4MCS2 0x4C +#define ODM_RATEVHTSS4MCS3 0x4D +#define ODM_RATEVHTSS4MCS4 0x4E +#define ODM_RATEVHTSS4MCS5 0x4F +#define ODM_RATEVHTSS4MCS6 0x50 +#define ODM_RATEVHTSS4MCS7 0x51 +#define ODM_RATEVHTSS4MCS8 0x52 +#define ODM_RATEVHTSS4MCS9 0x53 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) +#else + #if (RTL8192E_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1) + #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1) + #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1) + #elif (RTL8812A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1) + #elif(RTL8814A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1) + #else + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define CONFIG_SFW_SUPPORTED +#endif + +//1 ============================================================ +//1 enumeration +//1 ============================================================ + + +// ODM_CMNINFO_INTERFACE +typedef enum tag_ODM_Support_Interface_Definition +{ + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}ODM_INTERFACE_E; + +// ODM_CMNINFO_IC_TYPE +typedef enum tag_ODM_Support_IC_Type_Definition +{ + ODM_RTL8192S = BIT0, + ODM_RTL8192C = BIT1, + ODM_RTL8192D = BIT2, + ODM_RTL8723A = BIT3, + ODM_RTL8188E = BIT4, + ODM_RTL8812 = BIT5, + ODM_RTL8821 = BIT6, + ODM_RTL8192E = BIT7, + ODM_RTL8723B = BIT8, + ODM_RTL8814A = BIT9, + ODM_RTL8881A = BIT10, + ODM_RTL8821B = BIT11, + ODM_RTL8822B = BIT12, + ODM_RTL8703B = BIT13, + ODM_RTL8195A = BIT14, + ODM_RTL8188F = BIT15, + ODM_RTL8723D = BIT16 +}ODM_IC_TYPE_E; + + + + +#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D) +#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B) +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B) +#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D) +#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B) + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#ifdef RTK_AC_SUPPORT +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#else +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#endif + +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_CONFIG_BT_COEXIST 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_CONFIG_BT_COEXIST 1 + +#else + +#if((RTL8192C_SUPPORT == 1) || (RTL8192D_SUPPORT == 1) || (RTL8723A_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) ||\ +(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ +(RTL8188F_SUPPORT == 1)) +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#else +#define ODM_IC_11N_SERIES_SUPPORT 0 +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#ifdef CONFIG_BT_COEXIST +#define ODM_CONFIG_BT_COEXIST 1 +#else +#define ODM_CONFIG_BT_COEXIST 0 +#endif + +#endif + + +//ODM_CMNINFO_CUT_VER +typedef enum tag_ODM_Cut_Version_Definition +{ + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + + ODM_CUT_I = 8, + ODM_CUT_J = 9, + ODM_CUT_K = 10, + ODM_CUT_TEST = 15, +}ODM_CUT_VERSION_E; + +// ODM_CMNINFO_FAB_VER +typedef enum tag_ODM_Fab_Version_Definition +{ + ODM_TSMC = 0, + ODM_UMC = 1, +}ODM_FAB_E; + +// ODM_CMNINFO_RF_TYPE +// +// For example 1T2R (A+AB = BIT0|BIT4|BIT5) +// +typedef enum tag_ODM_RF_Path_Bit_Definition +{ + ODM_RF_A = BIT0, + ODM_RF_B = BIT1, + ODM_RF_C = BIT2, + ODM_RF_D = BIT3, +}ODM_RF_PATH_E; + +typedef enum tag_PHYDM_RF_TX_NUM { + ODM_1T = 1, + ODM_2T = 2, + ODM_3T = 3, + ODM_4T = 4, +} ODM_RF_TX_NUM_E; + +typedef enum tag_ODM_RF_Type_Definition { + ODM_1T1R, + ODM_1T2R, + ODM_2T2R, + ODM_2T2R_GREEN, + ODM_2T3R, + ODM_2T4R, + ODM_3T3R, + ODM_3T4R, + ODM_4T4R, + ODM_XTXR +}ODM_RF_TYPE_E; + + +typedef enum tag_ODM_MAC_PHY_Mode_Definition +{ + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}ODM_MAC_PHY_MODE_E; + + +typedef enum tag_BT_Coexist_Definition +{ + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}ODM_BT_COEXIST_E; + +// ODM_CMNINFO_OP_MODE +typedef enum tag_Operation_Mode_Definition +{ + ODM_NO_LINK = BIT0, + ODM_LINK = BIT1, + ODM_SCAN = BIT2, + ODM_POWERSAVE = BIT3, + ODM_AP_MODE = BIT4, + ODM_CLIENT_MODE = BIT5, + ODM_AD_HOC = BIT6, + ODM_WIFI_DIRECT = BIT7, + ODM_WIFI_DISPLAY = BIT8, +}ODM_OPERATION_MODE_E; + +// ODM_CMNINFO_WM_MODE +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT0, + ODM_WM_G = BIT1, + ODM_WM_A = BIT2, + ODM_WM_N24G = BIT3, + ODM_WM_N5G = BIT4, + ODM_WM_AUTO = BIT5, + ODM_WM_AC = BIT6, +}ODM_WIRELESS_MODE_E; +#else +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOWN = 0x00,/*0x0*/ + ODM_WM_A = BIT0, /* 0x1*/ + ODM_WM_B = BIT1, /* 0x2*/ + ODM_WM_G = BIT2,/* 0x4*/ + ODM_WM_AUTO = BIT3,/* 0x8*/ + ODM_WM_N24G = BIT4,/* 0x10*/ + ODM_WM_N5G = BIT5,/* 0x20*/ + ODM_WM_AC_5G = BIT6,/* 0x40*/ + ODM_WM_AC_24G = BIT7,/* 0x80*/ + ODM_WM_AC_ONLY = BIT8,/* 0x100*/ + ODM_WM_MAX = BIT11/* 0x800*/ + +}ODM_WIRELESS_MODE_E; +#endif + +// ODM_CMNINFO_BAND +typedef enum tag_Band_Type_Definition +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + ODM_BAND_2_4G = BIT0, + ODM_BAND_5G = BIT1, +#else + ODM_BAND_2_4G = 0, + ODM_BAND_5G, + ODM_BAND_ON_BOTH, + ODM_BANDMAX +#endif +}ODM_BAND_TYPE_E; + + +// ODM_CMNINFO_SEC_CHNL_OFFSET +typedef enum tag_Secondary_Channel_Offset_Definition +{ + ODM_DONT_CARE = 0, + ODM_BELOW = 1, + ODM_ABOVE = 2 +}ODM_SEC_CHNL_OFFSET_E; + +// ODM_CMNINFO_SEC_MODE +typedef enum tag_Security_Definition +{ + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, // WEP + WPA + ODM_SEC_SMS4 = 7, +}ODM_SECURITY_E; + +// ODM_CMNINFO_BW +typedef enum tag_Bandwidth_Definition +{ + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW5M = 4, + ODM_BW10M = 5, + ODM_BW_MAX = 6 +}ODM_BW_E; + +// ODM_CMNINFO_CHNL + +// ODM_CMNINFO_BOARD_TYPE +typedef enum tag_Board_Definition +{ + ODM_BOARD_DEFAULT = 0, // The DEFAULT case. + ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. + ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card + ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT + ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA + ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA + ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW + ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA + ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA +}ODM_BOARD_TYPE_E; + +typedef enum tag_ODM_Package_Definition +{ + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), +}ODM_Package_TYPE_E; + +typedef enum tag_ODM_TYPE_GPA_Definition { + TYPE_GPA0 = 0x0000, + TYPE_GPA1 = 0x0055, + TYPE_GPA2 = 0x00AA, + TYPE_GPA3 = 0x00FF, + TYPE_GPA4 = 0x5500, + TYPE_GPA5 = 0x5555, + TYPE_GPA6 = 0x55AA, + TYPE_GPA7 = 0x55FF, + TYPE_GPA8 = 0xAA00, + TYPE_GPA9 = 0xAA55, + TYPE_GPA10 = 0xAAAA, + TYPE_GPA11 = 0xAAFF, + TYPE_GPA12 = 0xFF00, + TYPE_GPA13 = 0xFF55, + TYPE_GPA14 = 0xFFAA, + TYPE_GPA15 = 0xFFFF, +}ODM_TYPE_GPA_E; + +typedef enum tag_ODM_TYPE_APA_Definition { + TYPE_APA0 = 0x0000, + TYPE_APA1 = 0x0055, + TYPE_APA2 = 0x00AA, + TYPE_APA3 = 0x00FF, + TYPE_APA4 = 0x5500, + TYPE_APA5 = 0x5555, + TYPE_APA6 = 0x55AA, + TYPE_APA7 = 0x55FF, + TYPE_APA8 = 0xAA00, + TYPE_APA9 = 0xAA55, + TYPE_APA10 = 0xAAAA, + TYPE_APA11 = 0xAAFF, + TYPE_APA12 = 0xFF00, + TYPE_APA13 = 0xFF55, + TYPE_APA14 = 0xFFAA, + TYPE_APA15 = 0xFFFF, +}ODM_TYPE_APA_E; + +typedef enum tag_ODM_TYPE_GLNA_Definition { + TYPE_GLNA0 = 0x0000, + TYPE_GLNA1 = 0x0055, + TYPE_GLNA2 = 0x00AA, + TYPE_GLNA3 = 0x00FF, + TYPE_GLNA4 = 0x5500, + TYPE_GLNA5 = 0x5555, + TYPE_GLNA6 = 0x55AA, + TYPE_GLNA7 = 0x55FF, + TYPE_GLNA8 = 0xAA00, + TYPE_GLNA9 = 0xAA55, + TYPE_GLNA10 = 0xAAAA, + TYPE_GLNA11 = 0xAAFF, + TYPE_GLNA12 = 0xFF00, + TYPE_GLNA13 = 0xFF55, + TYPE_GLNA14 = 0xFFAA, + TYPE_GLNA15 = 0xFFFF, +}ODM_TYPE_GLNA_E; + +typedef enum tag_ODM_TYPE_ALNA_Definition { + TYPE_ALNA0 = 0x0000, + TYPE_ALNA1 = 0x0055, + TYPE_ALNA2 = 0x00AA, + TYPE_ALNA3 = 0x00FF, + TYPE_ALNA4 = 0x5500, + TYPE_ALNA5 = 0x5555, + TYPE_ALNA6 = 0x55AA, + TYPE_ALNA7 = 0x55FF, + TYPE_ALNA8 = 0xAA00, + TYPE_ALNA9 = 0xAA55, + TYPE_ALNA10 = 0xAAAA, + TYPE_ALNA11 = 0xAAFF, + TYPE_ALNA12 = 0xFF00, + TYPE_ALNA13 = 0xFF55, + TYPE_ALNA14 = 0xFFAA, + TYPE_ALNA15 = 0xFFFF, +}ODM_TYPE_ALNA_E; + + +typedef enum _ODM_RF_RADIO_PATH { + ODM_RF_PATH_A = 0, //Radio Path A + ODM_RF_PATH_B = 1, //Radio Path B + ODM_RF_PATH_C = 2, //Radio Path C + ODM_RF_PATH_D = 3, //Radio Path D + ODM_RF_PATH_AB, + ODM_RF_PATH_AC, + ODM_RF_PATH_AD, + ODM_RF_PATH_BC, + ODM_RF_PATH_BD, + ODM_RF_PATH_CD, + ODM_RF_PATH_ABC, + ODM_RF_PATH_ACD, + ODM_RF_PATH_BCD, + ODM_RF_PATH_ABCD, + // ODM_RF_PATH_MAX, //Max RF number 90 support +} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; + +typedef enum _ODM_PARAMETER_INIT { + ODM_PRE_SETTING = 0, + ODM_POST_SETTING = 1, +} ODM_PARAMETER_INIT_E; + +#endif diff --git a/network/wlan/WDI/HAL/phydm/phydm_precomp.h b/network/wlan/WDI/HAL/phydm/phydm_precomp.h new file mode 100644 index 00000000..7cc6ad27 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_precomp.h @@ -0,0 +1,335 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "phydm_types.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. +#else +#define TEST_FALG___ 1 +#endif + +#if (DM_ODM_SUPPORT_TYPE ==ODM_CE) +#define RTL8192CE_SUPPORT 0 +#define RTL8192CU_SUPPORT 0 +#define RTL8192C_SUPPORT 0 + +#define RTL8192DE_SUPPORT 0 +#define RTL8192DU_SUPPORT 0 +#define RTL8192D_SUPPORT 0 + +#define RTL8723AU_SUPPORT 0 +#define RTL8723AS_SUPPORT 0 +#define RTL8723AE_SUPPORT 0 +#define RTL8723A_SUPPORT 0 +#define RTL8723_FPGA_VERIFICATION 0 +#endif + +//2 Config Flags and Structs - defined by each ODM Type + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../8192cd_cfg.h" + #include "../odm_inc.h" + + #include "../8192cd.h" + #include "../8192cd_util.h" + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #ifdef AP_BUILD_WORKAROUND + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "mp_precomp.h" + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#endif + +//2 OutSrc Header Files + +#include "phydm.h" +#include "phydm_hwconfig.h" +#include "phydm_debug.h" +#include "phydm_regdefine11ac.h" +#include "phydm_regdefine11n.h" +#include "phydm_interface.h" +#include "phydm_reg.h" + + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +#define RTL8821B_SUPPORT 0 +#define RTL8822B_SUPPORT 0 +#define RTL8723D_SUPPORT 0 + +VOID +PHY_SetTxPowerLimit( + IN PDM_ODM_T pDM_Odm, + IN u8 *Regulation, + IN u8 *Band, + IN u8 *Bandwidth, + IN u8 *RateSection, + IN u8 *RfPath, + IN u8 *Channel, + IN u8 *PowerLimit +); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#define RTL8821B_SUPPORT 0 +#define RTL8822B_SUPPORT 0 +#define RTL8703B_SUPPORT 0 +#define RTL8188F_SUPPORT 0 +#define RTL8723D_SUPPORT 0 +#endif + +//#if RTL8188E_SUPPORT == 1 +//#define RTL8188E_T_SUPPORT 1 +//#ifdef CONFIG_SFW_SUPPORTED +//#define RTL8188E_S_SUPPORT 1 +//#else +//#define RTL8188E_S_SUPPORT 0 +//#endif +//#endif +// +//#include "rtl8188e/hal8188erateadaptive.h"//for RA,Power training +//#include "rtl8188e/halhwimg8188e_mac.h" +//#include "rtl8188e/halhwimg8188e_rf.h" +//#include "rtl8188e/halhwimg8188e_bb.h" +//#include "rtl8188e/halhwimg8188e_t_fw.h" +//#include "rtl8188e/halhwimg8188e_s_fw.h" +//#include "rtl8188e/phydm_regconfig8188e.h" +//#include "rtl8188e/phydm_rtl8188e.h" +//#include "rtl8188e/hal8188ereg.h" +//#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8188e_hal.h" +// #include "rtl8188e/halphyrf_8188e_ce.h" +//#endif +//#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +// #include "rtl8188e/halphyrf_8188e_win.h" +//#endif +//#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +// #include "rtl8188e/halphyrf_8188e_ap.h" +//#endif + +//#if (RTL8192E_SUPPORT==1) +// +// #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +// #include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/ +// #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) +// #include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/ +// #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/ +// #endif +// +//#include "rtl8192e/phydm_rtl8192e.h" //FOR_8192E_IQK +//#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +// #include "rtl8192e/halhwimg8192e_bb.h" +// #include "rtl8192e/halhwimg8192e_mac.h" +// #include "rtl8192e/halhwimg8192e_rf.h" +// #include "rtl8192e/phydm_regconfig8192e.h" +// #include "rtl8192e/halhwimg8192e_fw.h" +// #include "rtl8192e/hal8192ereg.h" +//#endif +//#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8192e_hal.h" +//#endif +//#endif //92E END + + +//#if (RTL8723D_SUPPORT==1) +// #if (DM_ODM_SUPPORT_TYPE != ODM_AP) +// #include "rtl8723d/HalHWImg8723D_BB.h" +// #include "rtl8723d/HalHWImg8723D_MAC.h" +// #include "rtl8723d/HalHWImg8723D_RF.h" +// #include "rtl8723d/phydm_RegConfig8723D.h" +// #include "rtl8723d/HalHWImg8723D_FW.h" +// #include "rtl8723d/Hal8723DReg.h" +// #include "rtl8723d/phydm_rtl8723d.h" +// #endif +// #if (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8723d_hal.h" +// #endif +//#endif //8723D End + +//#if (RTL8812A_SUPPORT==1) +// +// #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +// #include "rtl8812a/halphyrf_8812a_win.h" +// #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) +// #include "rtl8812a/halphyrf_8812a_ap.h" +// #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8812a/halphyrf_8812a_ce.h" +// #endif +// +// //#include "rtl8812a/HalPhyRf_8812A.h" //FOR_8812_IQK +// #if (DM_ODM_SUPPORT_TYPE != ODM_AP) +// #include "rtl8812a/halhwimg8812a_bb.h" +// #include "rtl8812a/halhwimg8812a_mac.h" +// #include "rtl8812a/halhwimg8812a_rf.h" +// #include "rtl8812a/phydm_regconfig8812a.h" +// #include "rtl8812a/halhwimg8812a_fw.h" +// #include "rtl8812a/phydm_rtl8812a.h" +// #endif +// +// #if (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8812a_hal.h" +// #endif +// +//#endif //8812 END + +//#if (RTL8814A_SUPPORT==1) +// +//#include "rtl8814a/halhwimg8814a_mac.h" +//#include "rtl8814a/halhwimg8814a_rf.h" +//#include "rtl8814a/halhwimg8814a_bb.h" +//#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +// #include "rtl8814a/halhwimg8814a_fw.h" +// #include "rtl8814a/phydm_rtl8814a.h" +//#endif +//#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +// #include "rtl8814a/halphyrf_8814a_win.h" +//#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8814a/halphyrf_8814a_ce.h" +//#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) +// #include "rtl8814a/halphyrf_8814a_ap.h" +//#endif +// #include "rtl8814a/phydm_regconfig8814a.h" +//#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8814a_hal.h" +// #include "rtl8814a/phydm_iqk_8814a.h" +//#endif +//#endif //8814 END + +//#if (RTL8881A_SUPPORT==1)//FOR_8881_IQK +//#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//#include "rtl8821a/phydm_iqk_8821a_win.h" +//#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +//#include "rtl8821a/phydm_iqk_8821a_ce.h" +//#else +//#include "rtl8821a/phydm_iqk_8821a_ap.h" +//#endif +//#include "rtl8881a/HalHWImg8881A_BB.h" +//#include "rtl8881a/HalHWImg8881A_MAC.h" +//#include "rtl8881a/HalHWImg8881A_RF.h" +//#include "rtl8881a/odm_RegConfig8881A.h" +//#endif + +#if (RTL8723B_SUPPORT==1) +#include "rtl8723b/halhwimg8723b_mac.h" +#include "rtl8723b/halhwimg8723b_rf.h" +#include "rtl8723b/halhwimg8723b_bb.h" +#include "rtl8723b/halhwimg8723b_fw.h" +#include "rtl8723b/phydm_regconfig8723b.h" +#include "rtl8723b/phydm_rtl8723b.h" +#include "rtl8723b/hal8723breg.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8723b/halphyrf_8723b_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8723b/halphyrf_8723b_ce.h" + #include "rtl8723b/halhwimg8723b_mp.h" + #include "rtl8723b_hal.h" +#endif +#endif + +//#if (RTL8821A_SUPPORT==1) +//#include "rtl8821a/halhwimg8821a_mac.h" +//#include "rtl8821a/halhwimg8821a_rf.h" +//#include "rtl8821a/halhwimg8821a_bb.h" +//#include "rtl8821a/halhwimg8821a_fw.h" +//#include "rtl8821a/phydm_regconfig8821a.h" +//#include "rtl8821a/phydm_rtl8821a.h" +//#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +// #include "rtl8821a/halphyrf_8821a_win.h" +//#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +// #include "rtl8821a/halphyrf_8821a_ce.h" +// #include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/ +// #include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/ +// #include "rtl8812a_hal.h" +//#else +//#endif +//#endif + +//#if (RTL8821B_SUPPORT==1) +//#include "rtl8821b/halhwimg8821b_mac.h" +//#include "rtl8821b/halhwimg8821b_rf.h" +//#include "rtl8821b/halhwimg8821b_bb.h" +//#include "rtl8821b/halhwimg8821b_fw.h" +//#include "rtl8821b/phydm_regconfig8821b.h" +//#include "rtl8821b/halhwimg8821b_testchip_mac.h" +//#include "rtl8821b/halhwimg8821b_testchip_rf.h" +//#include "rtl8821b/halhwimg8821b_testchip_bb.h" +//#include "rtl8821b/halhwimg8821b_testchip_fw.h" +//#include "rtl8821b/halphyrf_8821b.h" +//#endif + + +//#include "rtl8822b/halhwimg8822b_mac.h" +//#include "rtl8822b/halhwimg8822b_rf.h" +//#include "rtl8822b/halhwimg8822b_bb.h" +///*#include "rtl8822b/halhwimg8822b_fw.h"*/ +//#include "rtl8822b/phydm_regconfig8822b.h" +//#include "rtl8822b/halphyrf_8822b.h" +//#include "rtl8822b/phydm_rtl8822b.h" +//#include "rtl8822b/phydm_hal_api8822b.h" +//#include "rtl8822b/version_rtl8822b.h" + + +//#if (RTL8703B_SUPPORT==1) +//#include "rtl8703b/phydm_regconfig8703b.h" +//#include "rtl8703b/halhwimg8703b_mac.h" +//#include "rtl8703b/halhwimg8703b_rf.h" +//#include "rtl8703b/halhwimg8703b_bb.h" +//#include "rtl8703b/halhwimg8703b_fw.h" +//#include "rtl8703b/halphyrf_8703b.h" +//#include "rtl8703b/version_rtl8703b.h" +//#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +//#include "rtl8703b_hal.h" +//#endif +//#endif + +//#if (RTL8188F_SUPPORT == 1) +//#include "rtl8188f/halhwimg8188f_mac.h" +//#include "rtl8188f/halhwimg8188f_rf.h" +//#include "rtl8188f/halhwimg8188f_bb.h" +//#include "rtl8188f/halhwimg8188f_fw.h" +//#include "rtl8188f/hal8188freg.h" +//#include "rtl8188f/phydm_rtl8188f.h" +//#include "rtl8188f/phydm_regconfig8188f.h" +//#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */ +//#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +//#include "rtl8188f_hal.h" +//#endif +//#endif + +#endif // __ODM_PRECOMP_H__ + diff --git a/network/wlan/WDI/HAL/phydm/phydm_rainfo.h b/network/wlan/WDI/HAL/phydm/phydm_rainfo.h new file mode 100644 index 00000000..4f62282a --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_rainfo.h @@ -0,0 +1,443 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMRAINFO_H__ +#define __PHYDMRAINFO_H__ + +/*#define RAINFO_VERSION "2.0" //2014.11.04*/ +/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/ +/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/ +#define RAINFO_VERSION "3.2" /*2015.01.14 Dino*/ + +#define HIGH_RSSI_THRESH 50 +#define LOW_RSSI_THRESH 20 + +#define ACTIVE_TP_THRESHOLD 150 +#define RA_RETRY_DESCEND_NUM 2 +#define RA_RETRY_LIMIT_LOW 4 +#define RA_RETRY_LIMIT_HIGH 32 + +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8821B|ODM_RTL8822B) + +#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL +#define RAINFO_STBC_STATE BIT1 +//#define RAINFO_LDPC_STATE BIT2 +#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection +#define RAINFO_SHURTCUT_STATE BIT3 +#define RAINFO_SHURTCUT_FLAG BIT4 +#define RAINFO_INIT_RSSI_RATE_STATE BIT5 +#define RAINFO_BF_STATE BIT6 +#define RAINFO_BE_TX_STATE BIT7 // 1:TX + +#define RA_MASK_CCK 0xf +#define RA_MASK_OFDM 0xff0 +#define RA_MASK_HT1SS 0xff000 +#define RA_MASK_HT2SS 0xff00000 +/*#define RA_MASK_MCS3SS */ +#define RA_MASK_HT4SS 0xff0 +#define RA_MASK_VHT1SS 0x3ff000 +#define RA_MASK_VHT2SS 0xffc00000 + +#if(DM_ODM_SUPPORT_TYPE == ODM_AP) +#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8812 |ODM_RTL8814A|ODM_RTL8822B) +#define RA_FIRST_MACID 1 +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8188F) +#define RA_FIRST_MACID 0 +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723B|ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8703B) */ +#define RA_FIRST_MACID 0 +#endif + + +#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit + +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) +#define DM_RATR_STA_ULTRA_LOW 4 +#endif + +#define DM_RA_RATE_UP 1 +#define DM_RA_RATE_DOWN 2 + +typedef enum _phydm_arfr_num { + ARFR_0_RATE_ID = 0x9, + ARFR_1_RATE_ID = 0xa, + ARFR_2_RATE_ID = 0xb, + ARFR_3_RATE_ID = 0xc, + ARFR_4_RATE_ID = 0xd, + ARFR_5_RATE_ID = 0xe +} PHYDM_RA_ARFR_NUM_E; + +typedef enum _Phydm_ra_dbg_para { + RADBG_RTY_PENALTY = 1, //u8 + RADBG_N_HIGH = 2, + RADBG_N_LOW = 3, + RADBG_TRATE_UP_TABLE = 4, + RADBG_TRATE_DOWN_TABLE = 5, + RADBG_TRYING_NECESSARY = 6, + RADBG_TDROPING_NECESSARY = 7, + RADBG_RATE_UP_RTY_RATIO = 8, //u8 + RADBG_RATE_DOWN_RTY_RATIO = 9, //u8 + + RADBG_DEBUG_MONITOR1 = 0xc, + RADBG_DEBUG_MONITOR2 = 0xd, + RADBG_DEBUG_MONITOR3 = 0xe, + RADBG_DEBUG_MONITOR4 = 0xf, + NUM_RA_PARA +} PHYDM_RA_DBG_PARA_E; + + +#if 1//88E RA +typedef struct _ODM_RA_Info_ { + u1Byte RateID; + u4Byte RateMask; + u4Byte RAUseRate; + u1Byte RateSGI; + u1Byte RssiStaRA; + u1Byte PreRssiStaRA; + u1Byte SGIEnable; + u1Byte DecisionRate; + u1Byte PreRate; + u1Byte HighestRate; + u1Byte LowestRate; + u4Byte NscUp; + u4Byte NscDown; + u2Byte RTY[5]; + u4Byte TOTAL; + u2Byte DROP; + u1Byte Active; + u2Byte RptTime; + u1Byte RAWaitingCounter; + u1Byte RAPendingCounter; +#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! + u1Byte PTActive; // on or off + u1Byte PTTryState; // 0 trying state, 1 for decision state + u1Byte PTStage; // 0~6 + u1Byte PTStopCount; //Stop PT counter + u1Byte PTPreRate; // if rate change do PT + u1Byte PTPreRssi; // if RSSI change 5% do PT + u1Byte PTModeSS; // decide whitch rate should do PT + u1Byte RAstage; // StageRA, decide how many times RA will be done between PT + u1Byte PTSmoothFactor; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + u1Byte RateDownCounter; + u1Byte RateUpCounter; + u1Byte RateDirection; + u1Byte BoundingType; + u1Byte BoundingCounter; + u1Byte BoundingLearningTime; + u1Byte RateDownStartTime; +#endif +} ODM_RA_INFO_T, *PODM_RA_INFO_T; +#endif + + +typedef struct _Rate_Adaptive_Table_ { + u1Byte firstconnect; +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + BOOLEAN PT_collision_pre; +#endif + +#if (defined(CONFIG_RA_DBG_CMD)) + BOOLEAN is_ra_dbg_init; + + u1Byte RTY_P[ODM_NUM_RATE_IDX]; + u1Byte RTY_P_default[ODM_NUM_RATE_IDX]; + BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX]; + + u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; + u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + + u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; + u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + + BOOLEAN RA_Para_feedback_req; + + u1Byte para_idx; + u1Byte rate_idx; + u1Byte value; + u2Byte value_16; + u1Byte rate_length; +#endif + u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; + + #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; + u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; + u1Byte retry_descend_num; + u1Byte retrylimit_low; + u1Byte retrylimit_high; + #endif + + +} RA_T, *pRA_T; + +typedef struct _ODM_RATE_ADAPTIVE { + u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver + u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH + u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW + u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC + BOOLEAN bLowerRtsRate; +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + u1Byte RtsThres; +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + BOOLEAN bUseLdpc; +#else + u1Byte UltraLowRSSIThresh; + u4Byte LastRATR; // RATR Register Content +#endif + +} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; + +VOID +ODM_C2HRaParaReportHandler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +odm_RA_ParaAdjust_Send_H2C( + IN PVOID pDM_VOID +); + +VOID +odm_RA_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value +); + +VOID +odm_RA_ParaAdjust_init( + IN PVOID pDM_VOID +); + +VOID +odm_RA_ParaAdjust( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_retry_count( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_retry_limit( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_rate_id_on_assoc( + IN PVOID pDM_VOID, + IN u1Byte wireless_mode, + IN u1Byte init_rate_id +); + +VOID +phydm_c2h_ra_report_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +phydm_ra_info_init( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorInit( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorCheck( + IN PVOID pDM_VOID +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +s4Byte +phydm_FindMinimumRSSI( +IN PDM_ODM_T pDM_Odm, +IN PADAPTER pAdapter, +IN OUT BOOLEAN *pbLink_temp + + ); +#endif + +VOID +odm_RSSIMonitorCheckMP( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorCheckCE( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorCheckAP( + IN PVOID pDM_VOID +); + + +VOID +odm_RateAdaptiveMaskInit( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMask( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PVOID pDM_VOID +); + +BOOLEAN +ODM_RAStateCheck( + IN PVOID pDM_VOID, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState +); + +VOID +odm_RefreshBasicRateMask( + IN PVOID pDM_VOID +); +VOID +ODM_RAPostActionOnAssoc( + IN PVOID pDM_Odm +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + +u1Byte +odm_Find_RTS_Rate( + IN PVOID pDM_VOID, + IN u1Byte Tx_Rate, + IN BOOLEAN bErpProtect +); + +VOID +ODM_UpdateNoisyState( + IN PVOID pDM_VOID, + IN BOOLEAN bNoisyStateFromC2H +); + +u4Byte +Set_RA_DM_Ratrbitmap_by_Noisy( + IN PVOID pDM_VOID, + IN WIRELESS_MODE WirelessMode, + IN u4Byte ratr_bitmap, + IN u1Byte rssi_level +); + +VOID +ODM_UpdateInitRate( + IN PVOID pDM_VOID, + IN u1Byte Rate +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_RSSIDumpToRegister( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshLdpcRtsMP( + IN PADAPTER pAdapter, + IN PDM_ODM_T pDM_Odm, + IN u1Byte mMacId, + IN u1Byte IOTPeer, + IN s4Byte UndecoratedSmoothedPWDB +); + +VOID +ODM_DynamicARFBSelect( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN BOOLEAN Collision_State +); + +VOID +ODM_RateAdaptiveStateApInit( + IN PVOID PADAPTER_VOID, + IN PRT_WLAN_STA pEntry +); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +static void +FindMinimumRSSI( + IN PADAPTER pAdapter +); + +u8Byte +PhyDM_Get_Rate_Bitmap_Ex( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u8Byte ra_mask, + IN u1Byte rssi_level, + OUT u8Byte *dm_RA_Mask, + OUT u1Byte *dm_RteID +); +u4Byte +ODM_Get_Rate_Bitmap( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level +); +#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + +#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ + +#endif /*#ifndef __ODMRAINFO_H__*/ + + diff --git a/network/wlan/WDI/HAL/phydm/phydm_reg.h b/network/wlan/WDI/HAL/phydm/phydm_reg.h new file mode 100644 index 00000000..e8424139 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_reg.h @@ -0,0 +1,208 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// File Name: odm_reg.h +// +// Description: +// +// This file is for general register definition. +// +// +//============================================================ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +// +// Register Definition +// + +//MAC REG +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define RF_T_METER_OLD 0x24 +#define RF_T_METER_NEW 0x42 + +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +//BB REG +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +//RF REG +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 +#define ODM_RF_T_METER 0x24 +#define ODM_RF_T_METER_92D 0x42 +#define ODM_RF_T_METER_88E 0x42 +#define ODM_RF_T_METER_92E 0x42 +#define ODM_RF_T_METER_8812 0x42 + +//Ant Detect Reg +#define ODM_DPDT 0x300 + +//PSD Init +#define ODM_PSDREG 0x808 + +//92D Path Div +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +// +// Bitmap Definition +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) +// TX AGC +#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 +#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 +#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 +#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c +#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 +#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 +#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 +#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c +#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 +#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 +#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 +#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8 +#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc +#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0 +#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4 +#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8 +#endif +#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 +#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 +#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 +#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c +#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 +#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 +#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 +#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c +#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 +#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 +#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 +#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8 +#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc +#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0 +#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4 +#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8 +#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820 +#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824 +#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828 +#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c +#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830 +#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834 +#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838 +#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c +#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840 +#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844 +#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848 +#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c +#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8 +#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc +#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0 +#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4 +#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8 +#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20 +#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24 +#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28 +#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c +#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30 +#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34 +#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38 +#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c +#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40 +#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44 +#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48 +#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c +#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8 +#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc +#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0 +#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4 +#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8 +#endif + +#define bTxAGC_byte0_Jaguar 0xff +#define bTxAGC_byte1_Jaguar 0xff00 +#define bTxAGC_byte2_Jaguar 0xff0000 +#define bTxAGC_byte3_Jaguar 0xff000000 +#endif + +#define BIT_FA_RESET BIT0 + + + +#endif + diff --git a/network/wlan/WDI/HAL/phydm/phydm_regdefine11ac.h b/network/wlan/WDI/HAL/phydm/phydm_regdefine11ac.h new file mode 100644 index 00000000..c8a551d1 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_regdefine11ac.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +//2 RF REG LIST + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 +#define ODM_REG_BB_RX_PATH_11AC 0x808 +#define ODM_REG_BB_TX_PATH_11AC 0x80c +#define ODM_REG_BB_ATC_11AC 0x860 +#define ODM_REG_EDCCA_POWER_CAL 0x8dc +#define ODM_REG_DBG_RPT_11AC 0x8fc +//PAGE 9 +#define ODM_REG_EDCCA_DOWN_OPT 0x900 +#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +#define ODM_REG_NHM_TIMER_11AC 0x990 +#define ODM_REG_CLM_TIME_PERIOD_11AC 0x990 +#define ODM_REG_NHM_TH9_TH10_11AC 0x994 +#define ODM_REG_CLM_11AC 0x994 +#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 +#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c +#define ODM_REG_NHM_TH8_11AC 0x9a0 +#define ODM_REG_NHM_9E8_11AC 0x9e8 +#define ODM_REG_CSI_CONTENT_VALUE 0x9b4 +//PAGE A +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +//PAGE B +#define ODM_REG_RST_RPT_11AC 0xB58 +//PAGE C +#define ODM_REG_TRMUX_11AC 0xC08 +#define ODM_REG_IGI_A_11AC 0xC50 +//PAGE E +#define ODM_REG_IGI_B_11AC 0xE50 +#define ODM_REG_TRMUX_11AC_B 0xE08 +//PAGE F +#define ODM_REG_CCK_CCA_CNT_11AC 0xF08 +#define ODM_REG_OFDM_FA_11AC 0xF48 +#define ODM_REG_RPT_11AC 0xfa0 +#define ODM_REG_CLM_RESULT_11AC 0xfa4 +#define ODM_REG_NHM_CNT_11AC 0xfa8 +#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 + +#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac +#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 +#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +//PAGE 18 +#define ODM_REG_IGI_C_11AC 0x1850 +//PAGE 1A +#define ODM_REG_IGI_D_11AC 0x1A50 + +//2 MAC REG LIST +#define ODM_REG_RESP_TX_11AC 0x6D8 + + + +//DIG Related +#define ODM_BIT_IGI_11AC 0xFFFFFFFF +#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16 +#define ODM_BIT_BB_RX_PATH_11AC 0xF +#define ODM_BIT_BB_TX_PATH_11AC 0xF +#define ODM_BIT_BB_ATC_11AC BIT14 + +#endif + diff --git a/network/wlan/WDI/HAL/phydm/phydm_regdefine11n.h b/network/wlan/WDI/HAL/phydm/phydm_regdefine11n.h new file mode 100644 index 00000000..8826dfb2 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_regdefine11n.h @@ -0,0 +1,199 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + + +//2 RF REG LIST +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C +#define ODM_REG_RX_DEFUALT_A_11N 0x858 +#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_NHM_TIMER_11N 0x894 +#define ODM_REG_CLM_TIME_PERIOD_11N 0x894 +#define ODM_REG_NHM_TH9_TH10_11N 0x890 +#define ODM_REG_CLM_11N 0x890 +#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 +#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c +#define ODM_REG_NHM_TH8_11N 0xe28 +#define ODM_REG_CLM_READY_11N 0x8b4 +#define ODM_REG_CLM_RESULT_11N 0x8d0 +#define ODM_REG_NHM_CNT_11N 0x8d8 + +// For ACS, Jeffery, 2014-12-26 +#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc +#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 +#define ODM_REG_NHM_CNT10_11N 0x8d4 + + + +//PAGE 9 +#define ODM_REG_DBG_RPT_11N 0x908 +#define ODM_REG_BB_TX_PATH_11N 0x90c +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 + +//PAGE A +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +//PAGE B +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +//PAGE C +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_BB_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_L1SBD_PD_CH_11N 0XC6C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +//PAGE D +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_BB_ATC_11N 0xD2C +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +#define ODM_REG_RPT_11N 0xDF4 +//PAGE E +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_EDCCA_DCNF_11N 0xE24 +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC +#define ODM_REG_IGI_C_11N 0xF84 +#define ODM_REG_IGI_D_11N 0xF88 + +//2 MAC REG LIST +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + + +//DIG Related +#define ODM_BIT_IGI_11N 0x0000007F +#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9 +#define ODM_BIT_BB_RX_PATH_11N 0xF +#define ODM_BIT_BB_TX_PATH_11N 0xF +#define ODM_BIT_BB_ATC_11N BIT11 + +#endif + diff --git a/network/wlan/WDI/HAL/phydm/phydm_rxhp.h b/network/wlan/WDI/HAL/phydm/phydm_rxhp.h new file mode 100644 index 00000000..98b3aa6a --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_rxhp.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PHYDMRXHP_H__ +#define __PHYDMRXHP_H__ + +#define RXHP_VERSION "1.0" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD +#define MODE_40M 0 //0:20M, 1:40M +#define PSD_TH2 3 +#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#define PSD_RESCAN 4 +#define PSD_SCAN_INTERVAL 700 //ms + +typedef struct _RX_High_Power_ +{ + u1Byte RXHP_flag; + u1Byte PSD_func_trigger; + u1Byte PSD_bitmap_RXHP[80]; + u1Byte Pre_IGI; + u1Byte Cur_IGI; + u1Byte Pre_pw_th; + u1Byte Cur_pw_th; + BOOLEAN First_time_enter; + BOOLEAN RXHP_enable; + u1Byte TP_Mode; + RT_TIMER PSDTimer; + #if USE_WORKITEM + RT_WORK_ITEM PSDTimeWorkitem; + #endif +}RXHP_T, *pRXHP_T; + +#define dm_PSDMonitorCallback odm_PSDMonitorCallback +VOID odm_PSDMonitorCallback(PRT_TIMER pTimer); + +VOID +odm_PSDMonitorInit( + IN PVOID pDM_VOID + ); + +void odm_RXHPInit( + IN PVOID pDM_VOID); + +void odm_RXHP( + IN PVOID pDM_VOID); + +VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +); + + VOID +ODM_PSDDbgControl( + IN PADAPTER Adapter, + IN u4Byte mode, + IN u4Byte btRssi + ); + + VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +); + +VOID +odm_PSD_RXHPWorkitemCallback( + IN PVOID pContext + ); + +VOID +odm_PSDMonitorWorkItemCallback( + IN PVOID pContext + ); + + #endif + + #endif +
\ No newline at end of file diff --git a/network/wlan/WDI/HAL/phydm/phydm_types.h b/network/wlan/WDI/HAL/phydm/phydm_types.h new file mode 100644 index 00000000..85be00b1 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/phydm_types.h @@ -0,0 +1,314 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + +// +// Define Different SW team support +// +#define ODM_AP 0x01 //BIT0 +#define ODM_ADSL 0x02 //BIT1 +#define ODM_CE 0x04 //BIT2 +#define ODM_WIN 0x08 //BIT3 + +// Deifne HW endian support +#define ODM_ENDIAN_BIG 0 +#define ODM_ENDIAN_LITTLE 1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc))) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv))) +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +#define RT_PCI_INTERFACE 1 +#define RT_USB_INTERFACE 2 +#define RT_SDIO_INTERFACE 3 +#endif + +typedef enum _HAL_STATUS{ + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, + /*RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED,*/ +}HAL_STATUS,*PHAL_STATUS; + +#if( DM_ODM_SUPPORT_TYPE == ODM_AP) +#define MP_DRIVER 0 +#endif +#if(DM_ODM_SUPPORT_TYPE != ODM_WIN) + +#define VISTA_USB_RX_REVISE 0 + +// +// Declare for ODM spin lock defintion temporarily fro compile pass. +// +typedef enum _RT_SPINLOCK_TYPE{ + RT_TX_SPINLOCK = 1, + RT_RX_SPINLOCK = 2, + RT_RM_SPINLOCK = 3, + RT_CAM_SPINLOCK = 4, + RT_SCAN_SPINLOCK = 5, + RT_LOG_SPINLOCK = 7, + RT_BW_SPINLOCK = 8, + RT_CHNLOP_SPINLOCK = 9, + RT_RF_OPERATE_SPINLOCK = 10, + RT_INITIAL_SPINLOCK = 11, + RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. +#if VISTA_USB_RX_REVISE + RT_USBRX_CONTEXT_SPINLOCK = 13, + RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR +#endif + //Shall we define Ndis 6.2 SpinLock Here ? + RT_PORT_SPINLOCK=16, + RT_VNIC_SPINLOCK=17, + RT_HVL_SPINLOCK=18, + RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. + + RT_BTData_SPINLOCK=25, + + RT_WAPI_OPTION_SPINLOCK=26, + RT_WAPI_RX_SPINLOCK=27, + + // add for 92D CCK control issue + RT_CCK_PAGEA_SPINLOCK = 28, + RT_BUFFER_SPINLOCK = 29, + RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, + RT_GEN_TEMP_BUF_SPINLOCK = 31, + RT_AWB_SPINLOCK = 32, + RT_FW_PS_SPINLOCK = 33, + RT_HW_TIMER_SPIN_LOCK = 34, + RT_MPT_WI_SPINLOCK = 35, + RT_P2P_SPIN_LOCK = 36, // Protect P2P context + RT_DBG_SPIN_LOCK = 37, + RT_IQK_SPINLOCK = 38, + RT_PENDED_OID_SPINLOCK = 39, + RT_CHNLLIST_SPINLOCK = 40, + RT_INDIC_SPINLOCK = 41, //protect indication + RT_RFD_SPINLOCK = 42, + RT_SYNC_IO_CNT_SPINLOCK = 43, + RT_LAST_SPINLOCK, +}RT_SPINLOCK_TYPE; + +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define STA_INFO_T RT_WLAN_STA + #define PSTA_INFO_T PRT_WLAN_STA + + #define CONFIG_HW_ANTENNA_DIVERSITY + #define CONFIG_SW_ANTENNA_DIVERSITY + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + #define CONFIG_ANT_DETECTION + #define CONFIG_RA_DBG_CMD + + #define __func__ __FUNCTION__ + #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT + #define bMaskH3Bytes 0xffffff00 + #define SUCCESS 0 + #define FAIL (-1) + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. + #define ADSL_AP_BUILD_WORKAROUND + #define AP_BUILD_WORKAROUND + + //2 [ Configure RA Debug H2C CMD ] + #define CONFIG_RA_DBG_CMD + + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + + //2 [ Configure Antenna Diversity ] +#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) + #define CONFIG_HW_ANTENNA_DIVERSITY + #define ODM_EVM_ENHANCE_ANTDIV + + //---------- + #if(!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_2G_DIVERSITY + #endif + + #ifdef CONFIG_NO_5G_DIVERSITY_8881A + #define CONFIG_NO_5G_DIVERSITY + #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) + #define CONFIG_5G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_5G_CG_TRX_DIVERSITY + #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_2G5G_CG_TRX_DIVERSITY + #endif + #if(!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_5G_DIVERSITY + #endif + //---------- + #if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) ) + #define CONFIG_NOT_SUPPORT_ANTDIV + #elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) ) + #define CONFIG_2G_SUPPORT_ANTDIV + #elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) ) + #define CONFIG_5G_SUPPORT_ANTDIV + #elif( (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY) ) + #define CONFIG_2G5G_SUPPORT_ANTDIV + #endif + //---------- +#endif + #ifdef AP_BUILD_WORKAROUND + #include "../typedef.h" + #else + typedef void VOID,*PVOID; + typedef unsigned char BOOLEAN,*PBOOLEAN; + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; +#if 1 +/* In ARM platform, system would use the type -- "char" as "unsigned char" + * And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/ + typedef signed char s1Byte,*ps1Byte; +#else + typedef char s1Byte,*ps1Byte; +#endif + typedef short s2Byte,*ps2Byte; + typedef long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + #endif + + typedef struct rtl8192cd_priv *prtl8192cd_priv; + typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + +#ifdef CONFIG_PCI_HCI + #define DEV_BUS_TYPE RT_PCI_INTERFACE +#endif + + #define _TRUE 1 + #define _FALSE 0 + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include <drv_types.h> + + /*#define CONFIG_RA_DBG_CMD*/ + /*#define CONFIG_ANT_DETECTION*/ + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + +#if 0 + typedef u8 u1Byte, *pu1Byte; + typedef u16 u2Byte,*pu2Byte; + typedef u32 u4Byte,*pu4Byte; + typedef u64 u8Byte,*pu8Byte; + typedef s8 s1Byte,*ps1Byte; + typedef s16 s2Byte,*ps2Byte; + typedef s32 s4Byte,*ps4Byte; + typedef s64 s8Byte,*ps8Byte; +#else + #define u1Byte u8 + #define pu1Byte u8* + + #define u2Byte u16 + #define pu2Byte u16* + + #define u4Byte u32 + #define pu4Byte u32* + + #define u8Byte u64 + #define pu8Byte u64* + + #define s1Byte s8 + #define ps1Byte s8* + + #define s2Byte s16 + #define ps2Byte s16* + + #define s4Byte s32 + #define ps4Byte s32* + + #define s8Byte s64 + #define ps8Byte s64* + +#endif + #ifdef CONFIG_USB_HCI + #define DEV_BUS_TYPE RT_USB_INTERFACE + #elif defined(CONFIG_PCI_HCI) + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #elif defined(CONFIG_SDIO_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_GSPI_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #endif + + + #if defined(CONFIG_LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined (CONFIG_BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #endif + + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + #define STA_INFO_T struct sta_info + #define PSTA_INFO_T struct sta_info * + + + + #define TRUE _TRUE + #define FALSE _FALSE + + + #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) + #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) + #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + + //define useless flag to avoid compile warning + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif +#endif + +#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) +#define COND_ELSE 2 +#define COND_ENDIF 3 + +#endif // __ODM_TYPES_H__ + diff --git a/network/wlan/WDI/HAL/phydm/rtchnlplan.h b/network/wlan/WDI/HAL/phydm/rtchnlplan.h new file mode 100644 index 00000000..78a31dcd --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtchnlplan.h @@ -0,0 +1,699 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __RT_CHANNELPLAN_H__ +#define __RT_CHANNELPLAN_H__ + +typedef enum _RT_CHANNEL_DOMAIN_NEW +{ + + //===== Add new channel plan above this line ===============// + + // For new architecture we define different 2G/5G CH area for all country. + // 2.4 G only + RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20, + RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21, + RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22, + RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23, + RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24, + // 2.4 G + 5G type 1 + RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25, + RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26, + //RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27, + // ..... + + RT_CHANNEL_DOMAIN_MAX_NEW, + +}RT_CHANNEL_DOMAIN_NEW, *PRT_CHANNEL_DOMAIN_NEW; + + +#if 0 +#define DOMAIN_CODE_2G_WORLD \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define DOMAIN_CODE_2G_ETSI1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define DOMAIN_CODE_2G_ETSI2 \ + {1,2,3,4,5,6,7,8,9,10,11}, 11 +#define DOMAIN_CODE_2G_FCC1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 +#define DOMAIN_CODE_2G_MKK1 \ + {10,11,12,13}, 4 + +#define DOMAIN_CODE_5G_ETSI1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define DOMAIN_CODE_5G_ETSI2 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_ETSI3 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define DOMAIN_CODE_5G_FCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_FCC2 \ + {36,40,44,48,149,153,157,161,165}, 9 +#define DOMAIN_CODE_5G_FCC3 \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define DOMAIN_CODE_5G_FCC4 \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define DOMAIN_CODE_5G_FCC5 \ + {149,153,157,161,165}, 5 +#define DOMAIN_CODE_5G_FCC6 \ + {36,40,44,48,52,56,60,64}, 8 +#define DOMAIN_CODE_5G_FCC7 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_IC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_KCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_MKK1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define DOMAIN_CODE_5G_MKK2 \ + {36,40,44,48,52,56,60,64}, 8 +#define DOMAIN_CODE_5G_MKK3 \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define DOMAIN_CODE_5G_NCC1 \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_NCC2 \ + {56,60,64,149,153,157,161,165}, 8 +#define UNDEFINED \ + {0}, 0 +#endif + +// +// +// +/* + +Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz + 2G 5G Ch# of 40MHz +"Albania�����ڥ���" AL Local Test + +"Algeria�����ΧQ��" DZ CE TCF + +"Antigua & Barbuda�w���ʮq&�ڥ��F" AG 2G_WORLD FCC TCF + +"Argentina���ڧ�" AR 2G_WORLD Local Test + +"Armenia�Ȭ�����" AM 2G_WORLD ETSI + +"Aruba���|�ڮq" AW 2G_WORLD FCC TCF + +"Australia�D�w" AU 2G_WORLD 5G_ETSI2 + +"Austria���a�Q" AT 2G_WORLD 5G_ETSI1 CE + +"Azerbaijan�������" AZ 2G_WORLD CE TCF + +"Bahamas�ګ���" BS 2G_WORLD + +"Barbados�ڤڦh��" BB 2G_WORLD FCC TCF + +"Belgium��Q��" BE 2G_WORLD 5G_ETSI1 CE + +"Bermuda�ʼ}�F" BM 2G_WORLD FCC TCF + +"Brazil�ڦ�" BR 2G_WORLD Local Test + +"Bulgaria�O�[�Q��" BG 2G_WORLD 5G_ETSI1 CE + +"Canada�[���j" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC + +"Cayman Islands�}�Ҹs�q" KY 2G_WORLD 5G_ETSI1 CE + +"Chile���Q" CL 2G_WORLD FCC TCF + +"China����" CN 2G_WORLD 5G_FCC5 �H��?�i2002�j353? + +"Columbia���ۤ��" CO 2G_WORLD Voluntary + +"Costa Rica�����F���[" CR 2G_WORLD FCC TCF + +"Cyprus�������" CY 2G_WORLD 5G_ETSI1 CE + +"Czech ���J" CZ 2G_WORLD 5G_ETSI1 CE + +"Denmark����" DK 2G_WORLD 5G_ETSI1 CE + +"Dominican Republic�h�����[�@�M��" DO 2G_WORLD FCC TCF + +"Egypt�J��" EG 2G_WORLD CE T CF + +"El Salvador�ĺ��˦h" SV 2G_WORLD Voluntary + +"Estonia�R�F����" EE 2G_WORLD 5G_ETSI1 CE + +"Finland����" FI 2G_WORLD 5G_ETSI1 CE + +"France�k��" FR 5G_E TSI1 CE + +"Germany�w��" DE 2G_WORLD 5G_ETSI1 CE + +"Greece ��þ" GR 2G_WORLD 5G_ETSI1 CE + +"Guam���q" GU 2G_WORLD + +"Guatemala�ʦa����" GT 2G_WORLD + +"Haiti���a" HT 2G_WORLD FCC TCF + +"Honduras�����Դ�" HN 2G_WORLD FCC TCF + +"Hungary�I���Q" HU 2G_WORLD 5G_ETSI1 CE + +"Iceland�B�q" IS 2G_WORLD 5G_ETSI1 CE + +"India�L��" IN 2G_WORLD 5G_FCC3 FCC/CE TCF + +"Ireland�R����" IE 2G_WORLD 5G_ETSI1 CE + +"Israel�H��C" IL 5G_F CC6 CE TCF + +"Italy�q�j�Q" IT 2G_WORLD 5G_ETSI1 CE + +"Japan�饻" JP 2G_MKK1 5G_MKK1 MKK MKK + +"Korea����" KR 2G_WORLD 5G_KCC1 KCC KCC + +"Latvia�Բ����" LV 2G_WORLD 5G_ETSI1 CE + +"Lithuania�߳��{" LT 2G_WORLD 5G_ETSI1 CE + +"Luxembourg�c�˳�" LU 2G_WORLD 5G_ETSI1 CE + +"Malaysia���Ӧ��" MY 2G_WORLD Local Test + +"Malta�����L" MT 2G_WORLD 5G_ETSI1 CE + +"Mexico�����" MX 2G_WORLD 5G_FCC3 Local Test + +"Morocco������" MA CE TCF + +"Netherlands����" NL 2G_WORLD 5G_ETSI1 CE + +"New Zealand�æ���" NZ 2G_WORLD 5G_ETSI2 + +"Norway����" NO 2G_WORLD 5G_ETSI1 CE + +"Panama�ڮ��� " PA 2G_FCC1 Voluntary + +"Philippines���" PH 2G_WORLD FCC TCF + +"Poland�i��" PL 2G_WORLD 5G_ETSI1 CE + +"Portugal�����" PT 2G_WORLD 5G_ETSI1 CE + +"Romaniaù������" RO 2G_WORLD 5G_ETSI1 CE + +"Russia�Xù��" RU 2G_WORLD 5G_ETSI3 CE TCF + +"Saudi Arabia�F�a���ԧB" SA 2G_WORLD CE TCF + +"Singapore�s�[�Y" SG 2G_WORLD + +"Slovakia������J" SK 2G_WORLD 5G_ETSI1 CE + +"Slovenia����������" SI 2G_WORLD 5G_ETSI1 CE + +"South Africa�n�D" ZA 2G_WORLD CE TCF + +"Spain��Z��" ES 5G_ETSI1 CE + +"Sweden���" SE 2G_WORLD 5G_ETSI1 CE + +"Switzerland��h" CH 2G_WORLD 5G_ETSI1 CE + +"Taiwan�O�W" TW 2G_FCC1 5G_NCC1 NCC + +"Thailand����" TH 2G_WORLD FCC/CE TCF + +"Turkey�g�ը�" TR 2G_WORLD + +"Ukraine�Q�J��" UA 2G_WORLD Local Test + +"United Kingdom�^��" GB 2G_WORLD 5G_ETSI1 CE ETSI + +"United States����" US 2G_FCC1 5G_FCC7 FCC FCC + +"Venezuela�e�����" VE 2G_WORLD 5G_FCC4 FCC TCF + +"Vietnam�V�n" VN 2G_WORLD FCC/CE TCF + + + +*/ + +// Counter abbervation. +typedef enum _RT_COUNTRY_DEFINE_NUM +{ + RT_CTRY_AL, // "Albania�����ڥ���" + RT_CTRY_DZ, // "Algeria�����ΧQ��" + RT_CTRY_AG, // "Antigua & Barbuda�w���ʮq&�ڥ��F" + RT_CTRY_AR, // "Argentina���ڧ�" + RT_CTRY_AM, // "Armenia�Ȭ�����" + RT_CTRY_AW, // "Aruba���|�ڮq" + RT_CTRY_AU, // "Australia�D�w" + RT_CTRY_AT, // "Austria���a�Q" + RT_CTRY_AZ, // "Azerbaijan�������" + RT_CTRY_BS, // "Bahamas�ګ���" + RT_CTRY_BB, // "Barbados�ڤڦh��" + RT_CTRY_BE, // "Belgium��Q��" + RT_CTRY_BM, // "Bermuda�ʼ}�F" + RT_CTRY_BR, // "Brazil�ڦ�" + RT_CTRY_BG, // "Bulgaria�O�[�Q��" + RT_CTRY_CA, // "Canada�[���j" + RT_CTRY_KY, // "Cayman Islands�}�Ҹs�q" + RT_CTRY_CL, // "Chile���Q" + RT_CTRY_CN, // "China����" + RT_CTRY_CO, // "Columbia���ۤ��" + RT_CTRY_CR, // "Costa Rica�����F���[" + RT_CTRY_CY, // "Cyprus�������" + RT_CTRY_CZ, // "Czech ���J" + RT_CTRY_DK, // "Denmark����" + RT_CTRY_DO, // "Dominican Republic�h�����[�@�M��" + RT_CTRY_CE, // "Egypt�J��" EG 2G_WORLD + RT_CTRY_SV, // "El Salvador�ĺ��˦h" + RT_CTRY_EE, // "Estonia�R�F����" + RT_CTRY_FI, // "Finland����" + RT_CTRY_FR, // "France�k��" + RT_CTRY_DE, // "Germany�w��" + RT_CTRY_GR, // "Greece ��þ" + RT_CTRY_GU, // "Guam���q" + RT_CTRY_GT, // "Guatemala�ʦa����" + RT_CTRY_HT, // "Haiti���a" + RT_CTRY_HN, // "Honduras�����Դ�" + RT_CTRY_HU, // "Hungary�I���Q" + RT_CTRY_IS, // "Iceland�B�q" + RT_CTRY_IN, // "India�L��" + RT_CTRY_IE, // "Ireland�R����" + RT_CTRY_IL, // "Israel�H��C" + RT_CTRY_IT, // "Italy�q�j�Q" + RT_CTRY_JP, // "Japan�饻" + RT_CTRY_KR, // "Korea����" + RT_CTRY_LV, // "Latvia�Բ����" + RT_CTRY_LT, // "Lithuania�߳��{" + RT_CTRY_LU, // "Luxembourg�c�˳�" + RT_CTRY_MY, // "Malaysia���Ӧ��" + RT_CTRY_MT, // "Malta�����L" + RT_CTRY_MX, // "Mexico�����" + RT_CTRY_MA, // "Morocco������" + RT_CTRY_NL, // "Netherlands����" + RT_CTRY_NZ, // "New Zealand�æ���" + RT_CTRY_NO, // "Norway����" + RT_CTRY_PA, // "Panama�ڮ��� " + RT_CTRY_PH, // "Philippines���" + RT_CTRY_PL, // "Poland�i��" + RT_CTRY_PT, // "Portugal�����" + RT_CTRY_RO, // "Romaniaù������" + RT_CTRY_RU, // "Russia�Xù��" + RT_CTRY_SA, // "Saudi Arabia�F�a���ԧB" + RT_CTRY_SG, // "Singapore�s�[�Y" + RT_CTRY_SK, // "Slovakia������J" + RT_CTRY_SI, // "Slovenia����������" + RT_CTRY_ZA, // "South Africa�n�D" + RT_CTRY_ES, // "Spain��Z��" + RT_CTRY_SE, // "Sweden���" + RT_CTRY_CH, // "Switzerland��h" + RT_CTRY_TW, // "Taiwan�O�W" + RT_CTRY_TH, // "Thailand����" + RT_CTRY_TR, // "Turkey�g�ը�" + RT_CTRY_UA, // "Ukraine�Q�J��" + RT_CTRY_GB, // "United Kingdom�^��" + RT_CTRY_US, // "United States����" + RT_CTRY_VE, // "Venezuela�e�����" + RT_CTRY_VN, // "Vietnam�V�n" + RT_CTRY_MAX, // + +}RT_COUNTRY_NAME, *PRT_COUNTRY_NAME; + +// Scan type including active and passive scan. +typedef enum _RT_SCAN_TYPE_NEW +{ + SCAN_NULL, + SCAN_ACT, + SCAN_PAS, + SCAN_BOTH, +}RT_SCAN_TYPE_NEW, *PRT_SCAN_TYPE_NEW; + + +// Power table sample. + +typedef struct _RT_CHNL_PLAN_LIMIT +{ + u2Byte Chnl_Start; + u2Byte Chnl_end; + + u2Byte Freq_Start; + u2Byte Freq_end; +}RT_CHNL_PLAN_LIMIT, *PRT_CHNL_PLAN_LIMIT; + + +// +// 2.4G Regulatory Domains +// +typedef enum _RT_REGULATION_DOMAIN_2G +{ + RT_2G_NULL, + RT_2G_WORLD, + RT_2G_ETSI1, + RT_2G_FCC1, + RT_2G_MKK1, + RT_2G_ETSI2 + +}RT_REGULATION_2G, *PRT_REGULATION_2G; + + +//typedef struct _RT_CHANNEL_BEHAVIOR +//{ +// u1Byte Chnl; +// RT_SCAN_TYPE_NEW +// +//}RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; + +//typedef struct _RT_CHANNEL_PLAN_TYPE +//{ +// RT_CHANNEL_BEHAVIOR +// u1Byte Chnl_num; +//}RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; + +// +// 2.4G Channel Number +// Channel definition & number +// +#define CHNL_RT_2G_NULL \ + {0}, 0 +#define CHNL_RT_2G_WORLD \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define CHNL_RT_2G_WORLD_TEST \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 + +#define CHNL_RT_2G_EFSI1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define CHNL_RT_2G_FCC1 \ + {1,2,3,4,5,6,7,8,9,10,11}, 11 +#define CHNL_RT_2G_MKK1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 +#define CHNL_RT_2G_ETSI2 \ + {10,11,12,13}, 4 + +// +// 2.4G Channel Active or passive scan. +// +#define CHNL_RT_2G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_2G_WORLD_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,0,0} +#define CHNL_RT_2G_EFSI1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_FCC1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_MKK1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_ETSI2_SCAN_TYPE \ + {1,1,1,1} + + +// +// 2.4G Band & Frequency Section +// Freqency start & end / band number +// +#define FREQ_RT_2G_NULL \ + {0}, 0 + // Passive scan CH 12, 13 +#define FREQ_RT_2G_WORLD \ + {2412, 2472}, 1 +#define FREQ_RT_2G_EFSI1 \ + {2412, 2472}, 1 +#define FREQ_RT_2G_FCC1 \ + {2412, 2462}, 1 +#define FREQ_RT_2G_MKK1 \ + {2412, 2484}, 1 +#define FREQ_RT_2G_ETSI2 \ + {2457, 2472}, 1 + + +// +// 5G Regulatory Domains +// +typedef enum _RT_REGULATION_DOMAIN_5G +{ + RT_5G_NULL, + RT_5G_WORLD, + RT_5G_ETSI1, + RT_5G_ETSI2, + RT_5G_ETSI3, + RT_5G_FCC1, + RT_5G_FCC2, + RT_5G_FCC3, + RT_5G_FCC4, + RT_5G_FCC5, + RT_5G_FCC6, + RT_5G_FCC7, + RT_5G_IC1, + RT_5G_KCC1, + RT_5G_MKK1, + RT_5G_MKK2, + RT_5G_MKK3, + RT_5G_NCC1, + +}RT_REGULATION_5G, *PRT_REGULATION_5G; + +// +// 5G Channel Number +// +#define CHNL_RT_5G_NULL \ + {0}, 0 +#define CHNL_RT_5G_WORLD \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_ETSI1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_ETSI2 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define CHNL_RT_5G_ETSI3 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_FCC1 \ + {36,40,44,48,149,153,157,161,165}, 9 +#define CHNL_RT_5G_FCC2 \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define CHNL_RT_5G_FCC3 \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define CHNL_RT_5G_FCC4 \ + {149,153,157,161,165}, 5 +#define CHNL_RT_5G_FCC5 \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_FCC6 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_FCC7 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_IC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define CHNL_RT_5G_KCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_MKK1 \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_MKK2 \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define CHNL_RT_5G_MKK3 \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_NCC1 \ + {56,60,64,149,153,157,161,165}, 8 + +// +// 5G Channel Active or passive scan. +// +#define CHNL_RT_5G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_5G_WORLD_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_5G_ETSI1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_5G_ETSI2_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define CHNL_RT_5G_ETSI3_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_FCC1_SCAN_TYPE \ + {36,40,44,48,149,153,157,161,165}, 9 +#define CHNL_RT_5G_FCC2_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define CHNL_RT_5G_FCC3_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define CHNL_RT_5G_FCC4_SCAN_TYPE \ + {149,153,157,161,165}, 5 +#define CHNL_RT_5G_FCC5_SCAN_TYPE \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_FCC6_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_FCC7_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_IC1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define CHNL_RT_5G_KCC1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_MKK1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_MKK2_SCAN_TYPE \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define CHNL_RT_5G_MKK3_SCAN_TYPE \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_NCC1_SCAN_TYPE \ + {56,60,64,149,153,157,161,165}, 8 + +// +// Global Regulation +// +typedef enum _RT_REGULATION_COMMON +{ + RT_WORLD, + RT_FCC, + RT_MKK, + RT_ETSI, + RT_IC, + RT_CE, + RT_NCC, + +}RT_REGULATION_CMN, *PRT_REGULATION_CMN; + + + +// +// Special requirement for different regulation domain. +// For internal test or customerize special request. +// +typedef enum _RT_CHNLPLAN_SREQ +{ + RT_SREQ_NA = 0x0, + RT_SREQ_2G_ADHOC_11N = 0x00000001, + RT_SREQ_2G_ADHOC_11B = 0x00000002, + RT_SREQ_2G_ALL_PASS = 0x00000004, + RT_SREQ_2G_ALL_ACT = 0x00000008, + RT_SREQ_5G_ADHOC_11N = 0x00000010, + RT_SREQ_5G_ADHOC_11AC = 0x00000020, + RT_SREQ_5G_ALL_PASS = 0x00000040, + RT_SREQ_5G_ALL_ACT = 0x00000080, + RT_SREQ_C1_PLAN = 0x00000100, + RT_SREQ_C2_PLAN = 0x00000200, + RT_SREQ_C3_PLAN = 0x00000400, + RT_SREQ_C4_PLAN = 0x00000800, + RT_SREQ_NFC_ON = 0x00001000, + RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */ + +}RT_CHNLPLAN_SREQ, *PRT_CHNLPLAN_SREQ; + + +// +// RT_COUNTRY_NAME & RT_REGULATION_2G & RT_REGULATION_5G transfer table +// +// +typedef struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE +{ + // + // Define countery domain and corresponding + // + RT_COUNTRY_NAME Country_Enum; + char Country_Name[3]; + + //char Domain_Name[12]; + RT_REGULATION_2G Domain_2G; + + RT_REGULATION_5G Domain_5G; + + RT_CHANNEL_DOMAIN RtChDomain; + //u1Byte Country_Area; + +}RT_CHNL_CTRY_TBL, *PRT_CHNL_CTRY_TBL; + + +#define RT_MAX_CHNL_NUM_2G 13 +#define RT_MAX_CHNL_NUM_5G 44 + +// Power table sample. + +typedef struct _RT_CHNL_PLAN_PWR_LIMIT +{ + u2Byte Chnl_Start; + u2Byte Chnl_end; + u1Byte dB_Max; + u2Byte mW_Max; +}RT_CHNL_PWR_LIMIT, *PRT_CHNL_PWR_LIMIT; + + +#define RT_MAX_BAND_NUM 5 + +typedef struct _RT_CHANNEL_PLAN_MAXPWR +{ +// STRING_T + RT_CHNL_PWR_LIMIT Chnl[RT_MAX_BAND_NUM]; + u1Byte Band_Useful_Num; + + +}RT_CHANNEL_PLAN_MAXPWR, *PRT_CHANNEL_PLAN_MAXPWR; + + +// +// Power By Rate Table. +// + + + +typedef struct _RT_CHANNEL_PLAN_NEW +{ + // + // Define countery domain and corresponding + // + //char Country_Name[36]; + //u1Byte Country_Enum; + + //char Domain_Name[12]; + + + PRT_CHNL_CTRY_TBL pCtryTransfer; + + RT_CHANNEL_DOMAIN RtChDomain; + + RT_REGULATION_2G Domain_2G; + + RT_REGULATION_5G Domain_5G; + + RT_REGULATION_CMN Regulator; + + RT_CHNLPLAN_SREQ ChnlSreq; + + //RT_CHNL_PLAN_LIMIT RtChnl; + + u1Byte Chnl2G[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD + u1Byte Len2G; + u1Byte Chnl2GScanTp[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD_SCAN_TYPE + //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD + + u1Byte Chnl5G[MAX_CHANNEL_NUM]; + u1Byte Len5G; + u1Byte Chnl5GScanTp[MAX_CHANNEL_NUM]; + //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD + + RT_CHANNEL_PLAN_MAXPWR ChnlMaxPwr; + + +}RT_CHANNEL_PLAN_NEW, *PRT_CHANNEL_PLAN_NEW; + + +#endif // __RT_CHANNELPLAN_H__ + + + + + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/hal8723breg.h b/network/wlan/WDI/HAL/phydm/rtl8723b/hal8723breg.h new file mode 100644 index 00000000..e34fe98b --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/hal8723breg.h @@ -0,0 +1,861 @@ +/***************************************************************************** + * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8723BREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HAL8723BREG_H +#define __INC_HAL8723BREG_H + + + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL_8723B 0x0000 // 2 Byte +#define REG_SYS_FUNC_EN_8723B 0x0002 // 2 Byte +#define REG_APS_FSMCO_8723B 0x0004 // 4 Byte +#define REG_SYS_CLKR_8723B 0x0008 // 2 Byte +#define REG_9346CR_8723B 0x000A // 2 Byte +#define REG_EE_VPD_8723B 0x000C // 2 Byte +#define REG_AFE_MISC_8723B 0x0010 // 1 Byte +#define REG_SPS0_CTRL_8723B 0x0011 // 7 Byte +#define REG_SPS_OCP_CFG_8723B 0x0018 // 4 Byte +#define REG_RSV_CTRL_8723B 0x001C // 3 Byte +#define REG_RF_CTRL_8723B 0x001F // 1 Byte +#define REG_LPLDO_CTRL_8723B 0x0023 // 1 Byte +#define REG_AFE_XTAL_CTRL_8723B 0x0024 // 4 Byte +#define REG_AFE_PLL_CTRL_8723B 0x0028 // 4 Byte +#define REG_MAC_PLL_CTRL_EXT_8723B 0x002c // 4 Byte +#define REG_EFUSE_CTRL_8723B 0x0030 +#define REG_EFUSE_TEST_8723B 0x0034 +#define REG_PWR_DATA_8723B 0x0038 +#define REG_CAL_TIMER_8723B 0x003C +#define REG_ACLK_MON_8723B 0x003E +#define REG_GPIO_MUXCFG_8723B 0x0040 +#define REG_GPIO_IO_SEL_8723B 0x0042 +#define REG_MAC_PINMUX_CFG_8723B 0x0043 +#define REG_GPIO_PIN_CTRL_8723B 0x0044 +#define REG_GPIO_INTM_8723B 0x0048 +#define REG_LEDCFG0_8723B 0x004C +#define REG_LEDCFG1_8723B 0x004D +#define REG_LEDCFG2_8723B 0x004E +#define REG_LEDCFG3_8723B 0x004F +#define REG_FSIMR_8723B 0x0050 +#define REG_FSISR_8723B 0x0054 +#define REG_HSIMR_8723B 0x0058 +#define REG_HSISR_8723B 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_MULTI_FUNC_CTRL_8723B 0x0068 +#define REG_GPIO_STATUS_8723B 0x006C +#define REG_SDIO_CTRL_8723B 0x0070 +#define REG_OPT_CTRL_8723B 0x0074 +#define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 +#define REG_MCUFWDL_8723B 0x0080 +#define REG_FW_DBG_STATUS_8723B 0x0088 +#define REG_FW_DBG_CTRL_8723B 0x008F +#define REG_SYSON_FSM_MON_8723B 0x00A0 +#define REG_HIMR0_8723B 0x00B0 +#define REG_HISR0_8723B 0x00B4 +#define REG_HIMR1_8723B 0x00B8 +#define REG_HISR1_8723B 0x00BC +#define REG_PMC_DBG_CTRL2_8723B 0x00CC +#define REG_EFUSE_BURN_GNT_8723B 0x00CF +#define REG_HPON_FSM_8723B 0x00EC +#define REG_SYS_CFG_8723B 0x00F0 +#define REG_SYS_CFG1_8723B 0x00FC +#define REG_ROM_VERSION 0x00FD + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR_8723B 0x0100 +#define REG_PBP_8723B 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 +#define REG_TRXDMA_CTRL_8723B 0x010C +#define REG_TRXFF_BNDY_8723B 0x0114 +#define REG_TRXFF_STATUS_8723B 0x0118 +#define REG_RXFF_PTR_8723B 0x011C +#define REG_CPWM_8723B 0x012F +#define REG_FWIMR_8723B 0x0130 +#define REG_FWISR_8723B 0x0134 +#define REG_FTIMR_8723B 0x0138 +#define REG_PKTBUF_DBG_CTRL_8723B 0x0140 +#define REG_RXPKTBUF_CTRL_8723B 0x0142 +#define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 + +#define REG_TC0_CTRL_8723B 0x0150 +#define REG_TC1_CTRL_8723B 0x0154 +#define REG_TC2_CTRL_8723B 0x0158 +#define REG_TC3_CTRL_8723B 0x015C +#define REG_TC4_CTRL_8723B 0x0160 +#define REG_TCUNIT_BASE_8723B 0x0164 +#define REG_RSVD3_8723B 0x0168 +#define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE +#define REG_C2HEVT_CLEAR_8723B 0x01AF +#define REG_MCUTST_1_8723B 0x01C0 +#define REG_MCUTST_WOWLAN_8723B 0x01C7 +#define REG_FMETHR_8723B 0x01C8 +#define REG_HMETFR_8723B 0x01CC +#define REG_HMEBOX_0_8723B 0x01D0 +#define REG_HMEBOX_1_8723B 0x01D4 +#define REG_HMEBOX_2_8723B 0x01D8 +#define REG_HMEBOX_3_8723B 0x01DC +#define REG_LLT_INIT_8723B 0x01E0 +#define REG_HMEBOX_EXT0_8723B 0x01F0 +#define REG_HMEBOX_EXT1_8723B 0x01F4 +#define REG_HMEBOX_EXT2_8723B 0x01F8 +#define REG_HMEBOX_EXT3_8723B 0x01FC + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN_8723B 0x0200 +#define REG_FIFOPAGE_8723B 0x0204 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define REG_DWBCN0_CTRL_8723B REG_TDECTRL +#else +#define REG_TDECTRL_8723B 0x0208 +#endif +#define REG_TXDMA_OFFSET_CHK_8723B 0x020C +#define REG_TXDMA_STATUS_8723B 0x0210 +#define REG_RQPN_NPQ_8723B 0x0214 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define REG_DWBCN1_CTRL_8723B 0x0228 +#else +#define REG_TDECTRL1_8723B 0x0228 +#endif + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH_8723B 0x0280 +#define REG_FW_UPD_RDPTR_8723B 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 +#define REG_RXDMA_CONTROL_8723B 0x0286 // Control the RX DMA. +#define REG_RXPKT_NUM_8723B 0x0287 // The number of packets in RXPKTBUF. +#define REG_RXDMA_STATUS_8723B 0x0288 +#define REG_RXDMA_PRO_8723B 0x0290 +#define REG_EARLY_MODE_CONTROL_8723B 0x02BC +#define REG_RSVD5_8723B 0x02F0 +#define REG_RSVD6_8723B 0x02F4 + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8723B 0x0300 +#define REG_INT_MIG_8723B 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA_8723B 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA_8723B 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA_8723B 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA_8723B 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA_8723B 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA_8723B 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA_8723B 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA_8723B 0x0340 // RX Queue Descriptor Address +#define REG_DBI_WDATA_8723B 0x0348 // DBI Write Data +#define REG_DBI_RDATA_8723B 0x034C // DBI Read Data +#define REG_DBI_ADDR_8723B 0x0350 // DBI Address +#define REG_DBI_FLAG_8723B 0x0352 // DBI Read/Write Flag +#define REG_MDIO_WDATA_8723B 0x0354 // MDIO for Write PCIE PHY +#define REG_MDIO_RDATA_8723B 0x0356 // MDIO for Reads PCIE PHY +#define REG_MDIO_CTL_8723B 0x0358 // MDIO for Control +#define REG_DBG_SEL_8723B 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM_8723B 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM_8723B 0x0363 //PCIe CPWM +#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A //PCIE Multi-Fethc Control + +// spec version 11 +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_VOQ_INFORMATION_8723B 0x0400 +#define REG_VIQ_INFORMATION_8723B 0x0404 +#define REG_BEQ_INFORMATION_8723B 0x0408 +#define REG_BKQ_INFORMATION_8723B 0x040C +#define REG_MGQ_INFORMATION_8723B 0x0410 +#define REG_HGQ_INFORMATION_8723B 0x0414 +#define REG_BCNQ_INFORMATION_8723B 0x0418 +#define REG_TXPKT_EMPTY_8723B 0x041A + +#define REG_FWHW_TXQ_CTRL_8723B 0x0420 +#define REG_HWSEQ_CTRL_8723B 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 +#define REG_LIFECTRL_CTRL_8723B 0x0426 +#define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 +#define REG_SPEC_SIFS_8723B 0x0428 +#define REG_RL_8723B 0x042A +#define REG_TXBF_CTRL_8723B 0x042C +#define REG_DARFRC_8723B 0x0430 +#define REG_RARFRC_8723B 0x0438 +#define REG_RRSR_8723B 0x0440 +#define REG_ARFR0_8723B 0x0444 +#define REG_ARFR1_8723B 0x044C +#define REG_CCK_CHECK_8723B 0x0454 +#define REG_AMPDU_MAX_TIME_8723B 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8723B 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D +#define REG_NDPA_OPT_CTRL_8723B 0x045F +#define REG_FAST_EDCA_CTRL_8723B 0x0460 +#define REG_RD_RESP_PKT_TH_8723B 0x0463 +#define REG_DATA_SC_8723B 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8723B 0x04B4 +#define REG_POWER_STAGE2_8723B 0x04B8 +#define REG_AMPDU_BURST_MODE_8723B 0x04BC +#define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 +#define REG_STBC_SETTING_8723B 0x04C4 +#define REG_HT_SINGLE_AMPDU_8723B 0x04C7 +#define REG_PROT_MODE_CTRL_8723B 0x04C8 +#define REG_MAX_AGGR_NUM_8723B 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB +#define REG_BAR_MODE_CTRL_8723B 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF +#define REG_MACID_PKT_DROP0_8723B 0x04D0 +#define REG_MACID_PKT_SLEEP_8723B 0x04D4 + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_EDCA_VO_PARAM_8723B 0x0500 +#define REG_EDCA_VI_PARAM_8723B 0x0504 +#define REG_EDCA_BE_PARAM_8723B 0x0508 +#define REG_EDCA_BK_PARAM_8723B 0x050C +#define REG_BCNTCFG_8723B 0x0510 +#define REG_PIFS_8723B 0x0512 +#define REG_RDG_PIFS_8723B 0x0513 +#define REG_SIFS_CTX_8723B 0x0514 +#define REG_SIFS_TRX_8723B 0x0516 +#define REG_AGGR_BREAK_TIME_8723B 0x051A +#define REG_SLOT_8723B 0x051B +#define REG_TX_PTCL_CTRL_8723B 0x0520 +#define REG_TXPAUSE_8723B 0x0522 +#define REG_DIS_TXREQ_CLR_8723B 0x0523 +#define REG_RD_CTRL_8723B 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT_8723B 0x0540 +#define REG_RD_NAV_NXT_8723B 0x0544 +#define REG_NAV_PROT_LEN_8723B 0x0546 +#define REG_BCN_CTRL_8723B 0x0550 +#define REG_BCN_CTRL_1_8723B 0x0551 +#define REG_MBID_NUM_8723B 0x0552 +#define REG_DUAL_TSF_RST_8723B 0x0553 +#define REG_BCN_INTERVAL_8723B 0x0554 +#define REG_DRVERLYINT_8723B 0x0558 +#define REG_BCNDMATIM_8723B 0x0559 +#define REG_ATIMWND_8723B 0x055A +#define REG_USTIME_TSF_8723B 0x055C +#define REG_BCN_MAX_ERR_8723B 0x055D +#define REG_RXTSF_OFFSET_CCK_8723B 0x055E +#define REG_RXTSF_OFFSET_OFDM_8723B 0x055F +#define REG_TSFTR_8723B 0x0560 +#define REG_CTWND_8723B 0x0572 +#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 +#define REG_PSTIMER_8723B 0x0580 +#define REG_TIMER0_8723B 0x0584 +#define REG_TIMER1_8723B 0x0588 +#define REG_ACMHWCTRL_8723B 0x05C0 +#define REG_SCH_TXCMD_8723B 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +#define REG_MAC_CR_8723B 0x0600 +#define REG_TCR_8723B 0x0604 +#define REG_RCR_8723B 0x0608 +#define REG_RX_PKT_LIMIT_8723B 0x060C +#define REG_RX_DLK_TIME_8723B 0x060D +#define REG_RX_DRVINFO_SZ_8723B 0x060F + +#define REG_MACID_8723B 0x0610 +#define REG_BSSID_8723B 0x0618 +#define REG_MAR_8723B 0x0620 +#define REG_MBIDCAMCFG_8723B 0x0628 + +#define REG_USTIME_EDCA_8723B 0x0638 +#define REG_MAC_SPEC_SIFS_8723B 0x063A +#define REG_RESP_SIFP_CCK_8723B 0x063C +#define REG_RESP_SIFS_OFDM_8723B 0x063E +#define REG_ACKTO_8723B 0x0640 +#define REG_CTS2TO_8723B 0x0641 +#define REG_EIFS_8723B 0x0642 + +#define REG_NAV_UPPER_8723B 0x0652 // unit of 128 +#define REG_TRXPTCL_CTL_8723B 0x0668 + +// Security +#define REG_CAMCMD_8723B 0x0670 +#define REG_CAMWRITE_8723B 0x0674 +#define REG_CAMREAD_8723B 0x0678 +#define REG_CAMDBG_8723B 0x067C +#define REG_SECCFG_8723B 0x0680 + +// Power +#define REG_WOW_CTRL_8723B 0x0690 +#define REG_PS_RX_INFO_8723B 0x0692 +#define REG_UAPSD_TID_8723B 0x0693 +#define REG_WKFMCAM_CMD_8723B 0x0698 +#define REG_WKFMCAM_NUM_8723B 0x0698 +#define REG_WKFMCAM_RWD_8723B 0x069C +#define REG_RXFLTMAP0_8723B 0x06A0 +#define REG_RXFLTMAP1_8723B 0x06A2 +#define REG_RXFLTMAP2_8723B 0x06A4 +#define REG_BCN_PSR_RPT_8723B 0x06A8 +#define REG_BT_COEX_TABLE_8723B 0x06C0 +#define REG_BFMER0_INFO_8723B 0x06E4 +#define REG_BFMER1_INFO_8723B 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC + +// Hardware Port 2 +#define REG_MACID1_8723B 0x0700 +#define REG_BSSID1_8723B 0x0708 +#define REG_BFMEE_SEL_8723B 0x0714 +#define REG_SND_PTCL_CTRL_8723B 0x0718 + + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. +#define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B // E-Fuse Control. +#define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B // E-Fuse Test. +#define MSR_8723B (REG_CR_8723B + 2) // Media Status register +#define ISR_8723B REG_HISR0_8723B +#define TSFR_8723B REG_TSFTR_8723B // Timing Sync Function Timer Register. + +#define PBP_8723B REG_PBP_8723B + +// Redifine MACID register, to compatible prior ICs. +#define IDR0_8723B REG_MACID_8723B // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4_8723B (REG_MACID_8723B + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM_8723B REG_CAMCMD_8723B //IN 8190 Data Sheet is called CAMcmd +#define WCAMI_8723B REG_CAMWRITE_8723B // Software write CAM input content +#define RCAMO_8723B REG_CAMREAD_8723B // Software read/write CAM config +#define CAMDBG_8723B REG_CAMDBG_8723B +#define SECR_8723B REG_SECCFG_8723B //Security Configuration Register + + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0xB0, 8bits) +//---------------------------------------------------------------------------- +#define IMR_DISABLED_8723B 0 +// IMR DW0(0x00B0-00B3) Bit 0-31 +#define IMR_TIMER2_8723B BIT31 // Timeout interrupt 2 +#define IMR_TIMER1_8723B BIT30 // Timeout interrupt 1 +#define IMR_PSTIMEOUT_8723B BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_8723B BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_8723B BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TXBCN0ERR_8723B BIT26 // Transmit Beacon0 Error +#define IMR_TXBCN0OK_8723B BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_8723B BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_8723B BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_8723B BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_8723B BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_8723B BIT12 // CTWidnow End or ATIM Window End +#define IMR_C2HCMD_8723B BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_8723B BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_8723B BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_8723B BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_8723B BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8723B BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8723B BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8723B BIT3 // AC_VI DMA OK +#define IMR_VODOK_8723B BIT2 // AC_VO DMA OK +#define IMR_RDU_8723B BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8723B BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_8723B BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_8723B BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_8723B BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_8723B BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_8723B BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_8723B BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_8723B BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_8723B BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_8723B BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_8723B BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_8723B BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_8723B BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_8723B BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_8723B BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_8723B BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_8723B BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_8723B BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_8723B BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_8723B BIT8 // Receive FIFO Overflow + + + + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +//---------------------------------------------------------------------------- +// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +/* +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 +*/ + + +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +/* +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + +//2 EFUSE_TEST (For RTL8723 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +*/ +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +/* + +//2 Function Enable Registers +//2 CR 0x0100-0x0103 + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + + +//2 PBP - Page Size Register 0x0104 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA 0x010C +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 REG_C2HEVT_CLEAR 0x01AF +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +//2 LLT_INIT 0x01E0 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +*/ +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +/* +//2 TDECTL 0x0208 +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK 0x020C +#define DROP_DATA_EN BIT(9) +*/ +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- +/* +//2 REG_RXDMA_CONTROL, 0x0286h + +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) +*/ +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +/* +//2 FWHW_TXQ_CTRL 0x0420 +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 REG_LIFECTRL_CTRL 0x0426 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + + +//2 SPEC SIFS 0x0428 +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL 0x042A +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) +*/ + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +/* +//2 EDCA setting 0x050C +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +//2 BCN_CTRL 0x0550 +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) + +//2 TxPause 0x0522 +#define STOP_BCNQ BIT(6) +*/ + + +//2 ACMHWCTRL 0x05C0 +#define AcmHw_HwEn_8723B BIT(0) +#define AcmHw_VoqEn_8723B BIT(1) +#define AcmHw_ViqEn_8723B BIT(2) +#define AcmHw_BeqEn_8723B BIT(3) +#define AcmHw_VoqStatus_8723B BIT(5) +#define AcmHw_ViqStatus_8723B BIT(6) +#define AcmHw_BeqStatus_8723B BIT(7) + + + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +/* + +//2 TCR 0x0604 +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) +*/ + +//---------------------------------------------------------------------------- +// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +/* +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_RSVD_BIT26 BIT26 // Reserved +*/ +#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload + +#endif // #ifndef __INC_HAL8723BREG_H diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_bb.h b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_bb.h new file mode 100644 index 00000000..af170089 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_bb.h @@ -0,0 +1,59 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.14*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8723B_H +#define __INC_MP_BB_HW_IMG_8723B_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_fw.h b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_fw.h new file mode 100644 index 00000000..0fd2d1d2 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_fw.h @@ -0,0 +1,62 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8723B_H +#define __INC_MP_FW_HW_IMG_8723B_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723B_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723B_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723B_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_mac.h b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_mac.h new file mode 100644 index 00000000..3ac3f15d --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_mac.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.14*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8723B_H +#define __INC_MP_MAC_HW_IMG_8723B_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_mp.h b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_mp.h new file mode 100644 index 00000000..be51ee4c --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_mp.h @@ -0,0 +1,45 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#if (RTL8723B_SUPPORT==1) +#ifndef __INC_MP_HW_IMG_8723B_H + +#define __INC_MP_HW_IMG_8723B_H + +#ifdef CONFIG_MP_INCLUDED + +#define Rtl8723BFwBTImgArrayLength 20564 + +#define Rtl8723B_PHYREG_Array_MPLength 4 + +extern u8 Rtl8723BFwBTImgArray[Rtl8723BFwBTImgArrayLength]; +extern const u32 Rtl8723B_PHYREG_Array_MP[Rtl8723B_PHYREG_Array_MPLength]; + +void +ODM_ReadFirmware_MP_8723B_FW_MP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + + +#endif //CONFIG_MP_INCLUDED +#endif +#endif diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_rf.h b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_rf.h new file mode 100644 index 00000000..7a478c18 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/halhwimg8723b_rf.h @@ -0,0 +1,89 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.14*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8723B_H +#define __INC_MP_RF_HW_IMG_8723B_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_PCIE(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TXPWR_LMT(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/halphyrf_8723b_ce.h b/network/wlan/WDI/HAL/phydm/rtl8723b/halphyrf_8723b_ce.h new file mode 100644 index 00000000..feb77d86 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/halphyrf_8723b_ce.h @@ -0,0 +1,134 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8723B_H__ +#define __HAL_PHY_RF_8723B_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8723B 20 //ms +#define IQK_DEFERRED_TIME_8723B 4 +#define index_mapping_NUM_8723B 15 +#define AVG_THERMAL_NUM_8723B 4 +#define RF_T_METER_8723B 0x42 // + + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8723B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore, + IN BOOLEAN Is2ant, + IN u1Byte RF_Path); + +VOID +ODM_SetIQCbyRFpath( +//#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +//#else + //IN PADAPTER pAdapter, +//#endif + IN u4Byte RFpath + ); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8723B( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8723B( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/halphyrf_8723b_win.h b/network/wlan/WDI/HAL/phydm/rtl8723b/halphyrf_8723b_win.h new file mode 100644 index 00000000..8924706f --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/halphyrf_8723b_win.h @@ -0,0 +1,131 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8723B_H__ +#define __HAL_PHY_RF_8723B_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define index_mapping_NUM_8723B 15 +#define AVG_THERMAL_NUM_8723B 4 +#define IQK_DELAY_TIME_8723B 20 //ms + + +#include "halphyrf_win.h" + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8723B( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + +BOOLEAN +ODM_SetIQCbyRFpath( +//#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +//#else + //IN PADAPTER pAdapter, +//#endif + IN u4Byte RFpath + ); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8723B( + IN PDM_ODM_T pDM_Odm +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8723B( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/mp_precomp.h b/network/wlan/WDI/HAL/phydm/rtl8723b/mp_precomp.h new file mode 100644 index 00000000..4e376e79 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/mp_precomp.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//#include <Precomp.h> +//#include "phydm_precomp.h" +//#include "../phydm_precomp.h" + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/phydm_regconfig8723b.h b/network/wlan/WDI/HAL/phydm/rtl8723b/phydm_regconfig8723b.h new file mode 100644 index 00000000..4f2d3884 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/phydm_regconfig8723b.h @@ -0,0 +1,96 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8723B +#define __INC_ODM_REGCONFIG_H_8723B + +#if (RTL8723B_SUPPORT == 1) + +void +odm_ConfigRFReg_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8723B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif // end of SUPPORT + diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/phydm_rtl8723b.h b/network/wlan/WDI/HAL/phydm/rtl8723b/phydm_rtl8723b.h new file mode 100644 index 00000000..a7739ef1 --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/phydm_rtl8723b.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8723B_H__ +#define __ODM_RTL8723B_H__ + +s1Byte +odm_CCKRSSI_8723B( + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ); + +#endif diff --git a/network/wlan/WDI/HAL/phydm/rtl8723b/version_rtl8723b.h b/network/wlan/WDI/HAL/phydm/rtl8723b/version_rtl8723b.h new file mode 100644 index 00000000..93f2189f --- /dev/null +++ b/network/wlan/WDI/HAL/phydm/rtl8723b/version_rtl8723b.h @@ -0,0 +1,5 @@ +/*RTL8723B PHY Parameters*/ +#define SVN_COMMIT_VERSION_8723B 26 +#define RELEASE_DATE_8723B 20150617 +#define COMMIT_BY_8723B "BB_STANLEY" +#define RELEASE_VERSION_8723B 24 diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BDefCom.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BDefCom.h new file mode 100644 index 00000000..f32ba53a --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BDefCom.h @@ -0,0 +1,212 @@ +#ifndef __REALTEK_HAL8723BDEFCOM_H__ +#define __REALTEK_HAL8723BDEFCOM_H__ + + +typedef enum _RTL8723B_SRAM_DATA +{ + LOC_8723B_SRFF, + LOC_8723B_TXRPT, + LOC_8723B_BCN_RPT, + LOC_8723B_AMPDU_BU_RST_CTRL, + LOC_8723B_RA_MASK +}RTL8723B_SRAM_DATA; + +u1Byte +GetEEPROMSize8723B( + IN PADAPTER Adapter + ); + +VERSION_8192C +ReadChipVersion8723B( + IN PADAPTER Adapter + ); + +VOID +ReadSdramData_8723B( + IN PADAPTER Adapter, + IN u1Byte macId, + IN RTL8723B_SRAM_DATA Type, + OUT pu4Byte data, + IN u1Byte dataLen + ); + + +VOID +Hal_ReadPROMContent_BT_8723B( + IN PADAPTER Adapter + ); + +VOID +HalSetRegMACID0AID_8723B( + IN PADAPTER Adapter + ); + +VOID +SetBcnCtrlReg_8723B( + IN PADAPTER Adapter, + IN u1Byte SetBits, + IN u1Byte ClearBits + ); + + + +//2 WoWLAN + +VOID +SetWoWLANCAMEntry8723B( + PADAPTER Adapter +); + +RT_STATUS +HalSetFWWoWlanMode8723B( + IN PADAPTER pAdapter, + IN BOOLEAN bFuncEn + ); + +VOID +GetPortsCommonBasicRate_8723B( + IN PADAPTER Adapter, + OUT pu1Byte SupportRate, + OUT pu2Byte SupportRateLen +); + +u1Byte +SelectRTSInitialRate8723B( + IN PADAPTER Adapter +); + + +VOID +HalSetBrateCfg_8723B( + IN PADAPTER Adapter, + IN OCTET_STRING *mBratesOS, + OUT pu2Byte pBrateCfg +); + +VOID +HalUpdateDefaultSetting8723B( + IN PADAPTER pAdapter + ); + +VOID +UpdateHalRAMask8723B( + IN PADAPTER Adapter, + IN u1Byte macId, + IN PRT_WLAN_STA pEntry, + IN u1Byte rssi_level + ); + +VOID +ActUpdateChannelAccessSetting_8723B( + PADAPTER Adapter, + WIRELESS_MODE WirelessMode, + PCHANNEL_ACCESS_SETTING ChnlAccessSetting + ); + + +#if RX_AGGREGATION +VOID +RxAggrSettingWorkItemCallback_8723B( + IN PVOID pContext + ); +#endif + +VOID +Dbg_IQK_TriggerWorkItemCallback_8723B( + IN PVOID pContext +); +VOID +Dbg_LCK_TriggerWorkItemCallback_8723B( + IN PVOID pContext +); + + +u4Byte +H2CCmdAction8723B( + IN PADAPTER Adapter, + IN PVOID pBuf, + IN u2Byte bufLen + ); + +VOID +SetFwRelatedForWoWLAN8723B( + IN PADAPTER Adapter, + IN BOOLEAN bUsedWoWLANFw +); + +u1Byte +GetFwPsStateDef8723B( + IN PADAPTER Adapter, + IN u1Byte FwPsState +); + +BOOLEAN +CheckCPWMInterrupt8723B( + IN PADAPTER Adapter +); + +u1Byte +GetTxBufferRsvdPageNum8723B( + IN PADAPTER Adapter, + IN BOOLEAN bWoWLANBoundary +); + +VOID +HalSetFwKeepAliveCmd8723B( + IN PADAPTER pAdapter, + IN BOOLEAN bFuncEn + ); + +RT_STATUS +InitLLTTable8723B( + IN PADAPTER Adapter, + IN u4Byte boundary + ); + +VOID +SetPowerDownReg_8723B( + IN PADAPTER Adapter, + IN BOOLEAN bFuncEnable + ); + +RT_STATUS +HalDynamicRQPN8723B( + IN PADAPTER Adapter, + IN u4Byte boundary, + IN u2Byte NPQ_RQPNValue, + IN u4Byte RQPNValue + ); + +BOOLEAN +IsHwAutoRFOff8723B( + IN PADAPTER Adapter + ); + +VOID +ForceLeaveHwClock32K8723B( + IN PADAPTER Adapter + ); + +RT_STATUS +RecoverTxBoundarySetting8723B( + IN PADAPTER Adapter, + IN BOOLEAN bWoWLANSetting + ); + +VOID +HalGetAOACReport8723B( + IN PADAPTER Adapter, + IN pu1Byte AOACRptBuf + ); + +VOID +HalSetFcsAdjustTsf_8723B( + IN PADAPTER Adapter + ); + +VOID +ex_hal8723b_wifi_only_hw_config( + IN PADAPTER Adapter + ); + +#endif diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BDesc.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BDesc.h new file mode 100644 index 00000000..412b0652 --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BDesc.h @@ -0,0 +1,286 @@ +#ifndef __INC_HAL8723BDESC_H +#define __INC_HAL8723BDESC_H + + +#define RX_STATUS_DESC_SIZE_8723B 24 +#define RX_DRV_INFO_SIZE_UNIT_8723B 8 + + +//DWORD 0 +#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value) +#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value) +#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value) + +#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) +#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1) +#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1) +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4) +#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3) +#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1) +#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2) +#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1) +#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1) +#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1) +#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1) +#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1) +#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1) + +//DWORD 1 +#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) +#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) +#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) +#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1) +#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1) +#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4) +#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1) +#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) +#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) +#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) +#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1) +#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1) +#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1) +#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1) +#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2) +#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1) +#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1) + +//DWORD 2 +#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12) +#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4) +#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1) +#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6) +#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1) + +//DWORD 3 +#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7) +#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1) +#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1) +#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2) +#if RX_AGGREGATION +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8) +#endif +#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1) +#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1) +#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1) + +//DWORD 6 +#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1) +#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1) +#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1) +#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2) + +//DWORD 5 +#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + +#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) +#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) + +#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) + + +// Dword 0 +#define GET_TX_DESC_OWN_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) + +#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) +#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) +#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) +#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) +#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) +#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) +#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) +#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) +#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +// Dword 1 +#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) +#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) +#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) +#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) +#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) +#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) +#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) +#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) +#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) + + +// Dword 2 +#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) +#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) +#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) +#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) +#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) +#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) +#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) +#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) +#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) +#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) +#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) + + +// Dword 3 +#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) +#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) +#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) +#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) +#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) +#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) +#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) +#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) +#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) +#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) +#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) +#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) +#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) +#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) + +// Dword 4 +#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) +#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) +#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) +#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) +#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) + + +// Dword 5 +#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) +#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) +#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) +#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) +#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) +#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) +#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) +#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) + + +// Dword 6 +#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) +#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) +#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) +#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) +#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) + +// Dword 7 + +#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) + +#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) + +#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) + + +// Dword 8 +#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) + +// Dword 9 +#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) + +// Dword 10 +#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) + + +// Dword 11 +#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) + + +#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) +#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) +#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) +#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) +#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) +#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) + +#endif + + +#define RX_HAL_IS_CCK_RATE_8723B(pDesc)\ + (GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC_RATE1M ||\ + GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC_RATE2M ||\ + GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC_RATE5_5M ||\ + GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC_RATE11M) + +#ifdef REMOVE_PACK +#pragma pack(1) +#endif + +typedef struct _RX_DRIVER_INFO_8723B{ + //DWORD 0 + u1Byte gain_trsw[2]; + u2Byte chl_num:10; + u2Byte sub_chnl:4; + u2Byte r_RFMOD:2; + + //DWORD 1 + u1Byte pwdb_all; + u1Byte cfosho[4]; // DW 1 byte 1 DW 2 byte 0 + + //DWORD 2 + u1Byte cfotail[4]; // DW 2 byte 1 DW 3 byte 0 + + //DWORD 3 + s1Byte rxevm[2]; // DW 3 byte 1 DW 3 byte 2 + s1Byte rxsnr[2]; // DW 3 byte 3 DW 4 byte 0 + + //DWORD 4 + u1Byte PCTS_MSK_RPT[2]; + u1Byte pdsnr[2]; // DW 4 byte 3 DW 5 Byte 0 + + //DWORD 5 + u1Byte csi_current[2]; + u1Byte rx_gain_c; + + //DWORD 6 + u1Byte rx_gain_d; + s1Byte sigevm; + u1Byte resvd_0; + u1Byte antidx_anta:3; + u1Byte antidx_antb:3; + u1Byte resvd_1:2; +}RX_DRIVER_INFO_8723B, *PRX_DRIVER_INFO_8723B; + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +VOID +TxDescriptorChecksum_8723B( + IN pu1Byte txDesc +); + + +u1Byte +BWMapping_8723B( + IN PADAPTER Adapter, + IN PRT_TCB pTcb +); + +u1Byte +SCMapping_8723B( + IN PADAPTER Adapter, + IN PRT_TCB pTcb +); + +VOID +InsertEMContent_8723B( + IN u1Byte bEarlyModeEnable, + IN PRT_TCB pTcb, + IN pu1Byte VirtualAddress +); + + +VOID +TranslateRxSignalStuff8723B( + IN PADAPTER Adapter, + IN OUT PRT_RFD pRfd, + IN pu1Byte pDesc, + IN PRX_DRIVER_INFO_8723B pDrvInfo ); + +u4Byte +RxCommandPacketHandle8723B( + IN PADAPTER Adapter, + IN PRT_RFD pRfd + ); + + diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BEfuse.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BEfuse.h new file mode 100644 index 00000000..699ec082 --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BEfuse.h @@ -0,0 +1,221 @@ +/****************************************************************************** + * + * (c) Copyright 2012, RealTEK Technologies Inc. All Rights Reserved. + * + * Module: Hal8723BEfuse.c ( Source C File) + * + * Note: Copy from WMAC for the first version!!!! + * + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 07/10/2012 Kordan Set an independent files. + * +******************************************************************************/ +#ifndef __8723B_EFUSE_H__ +#define __8723B_EFUSE_H__ + +#define HWSET_MAX_SIZE_8723B 512 + +#define EFUSE_REAL_CONTENT_LEN_8723B 512 + +#define EFUSE_MAP_LEN_8723B 512 +#define EFUSE_MAX_SECTION_8723B 64 +#define EFUSE_MAX_WORD_UNIT_8723B 4 +#define EFUSE_IC_ID_OFFSET_8723B 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. +#define AVAILABLE_EFUSE_ADDR_8723B(addr) (addr < EFUSE_REAL_CONTENT_LEN_8723B) + + +//======================================================== +// EFUSE for BT definition +//======================================================== +#define EFUSE_BT_REAL_BANK_CONTENT_LEN_8723B 512 +#define EFUSE_BT_REAL_CONTENT_LEN_8723B 1024 // 512*2 +#define EFUSE_BT_MAP_LEN_8723B 1024 // 1k bytes +#define EFUSE_BT_MAX_SECTION_8723B 128 // 1024/8 + +#define EFUSE_PROTECT_BYTES_BANK_8723B 16 +#define EFUSE_MAX_BANK_8723B 3 +//=========================================================== + +// EFUSE Parsing +//=========================================================== +VOID +Hal_EfuseParseBTCoexistInfo8723B( + IN PADAPTER Adapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_ReadChannelPlan8723B( + IN PADAPTER pAdapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_EfuseParseEEPROMVer8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); +VOID +Hal_EfuseParseChnlPlan8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); +VOID +Hal_EfuseParseCustomerID8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); +VOID +Hal_EfuseParseAntennaDiversity8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_EfuseParseIDCode8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo + ); + +VOID +Hal_InitChannelPlan8723B( + IN PADAPTER pAdapter + ); + + +VOID +Hal_EfuseParseRateIndicationOption8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_EfuseParseXtal_8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_ReadThermalMeter_8723B( + IN PADAPTER Adapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoloadFail + ); + +VOID +Hal_ReadAntennaDiversity8723B( + IN PADAPTER pAdapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_EfuseReadEFuse8723B( + PADAPTER Adapter, + u2Byte _offset, + u2Byte _size_byte, + u1Byte *pbuf, + IN BOOLEAN bPseudoTest + ); + +VOID +Hal_EfuseReadEFuse8723B( + PADAPTER Adapter, + u2Byte _offset, + u2Byte _size_byte, + u1Byte *pbuf, + IN BOOLEAN bPseudoTest + ); + + + +VOID +Hal_ReadTxPowerInfo8723B( + IN PADAPTER Adapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoLoadFail + ); + +VOID +Hal_ReadBoardType8723B( + IN PADAPTER Adapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoloadFail + ); + + + + +BOOLEAN +Hal_EfuseSwitchToBank8723B( + IN PADAPTER pAdapter, + IN u1Byte bank, + IN BOOLEAN bPseudoTest + ); + + +BOOLEAN +Hal_GetChnlGroup8723B( + IN u1Byte Channel, + OUT pu1Byte pGroup + ); + +VOID +Hal_ReadPROMVersion8723B( + IN PADAPTER Adapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoloadFail + ); + +VOID +Hal_ReadPAType_8723B( + IN PADAPTER Adapter, + IN pu1Byte PROMContent, + IN BOOLEAN AutoloadFail + ); + +VOID +Hal_InitEfuseVars_8723B( + IN PEFUSE_HAL pEfuseHal + ); + +VOID +Hal_EfusePowerSwitch8723B( + IN PADAPTER pAdapter, + IN UINT8 bWrite, + IN UINT8 PwrState); + +VOID +Hal_EfusePowerSwitch8723B_TestChip( + IN PADAPTER pAdapter, + IN UINT8 bWrite, + IN UINT8 PwrState); + +VOID +Hal_EfuseParsePackageType_8723B( + IN PADAPTER pAdapter, + IN pu1Byte hwinfo, + IN BOOLEAN AutoLoadFail + ); + + +#endif + + diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BFirmware.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BFirmware.h new file mode 100644 index 00000000..867c2545 --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BFirmware.h @@ -0,0 +1,465 @@ +#ifndef __INC_FIRMWARE8723B_H__ +#define __INC_FIRMWARE8723B_H__ + + +#define IS_FW_HEADER_EXIST_8723B(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr) &0xFFF0) == 0x5300) + +//-------------------------------------------- +//3 Host Message Box +//-------------------------------------------- + +// Keep Alive Control +#define SET_8723B_H2CCMD_KEEP_ALIVE_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_KEEP_ALIVE_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +//_RSVDPAGE_LOC_CMD0 +#define SaaasET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_CTS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + + +//_MEDIA_STATUS_RPT_PARM_CMD1 +#define SET_8723B_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) + + +// _WoWLAN PARAM_CMD5 +#define SET_8723B_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIO_PULSE_CNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 8, __Value) + + +//WLANINFO_PARM +#define SET_8723B_H2CCMD_WLANINFO_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_WLANINFO_PARM_CHANNEL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_WLANINFO_PARM_BW40MHZ(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +// _REMOTE_WAKEUP_CMD7 +#define SET_8723B_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_NETWORK_LIST_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_REALWOWV2_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) + + +// _AP_OFFLOAD_CMD8 +#define SET_8723B_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +// FCS_LOC_CMD10 +#define SET_8723B_H2CCMD_RSVDPAGE_FCS_LOC_NULL_DATA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_FCS_LOC_NULL_DATA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_FCS_LOC_NULL_DATA2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +// FCS_INFO_CMD11 +#define SET_8723B_H2CCMD_FCS_INFO_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_TOTAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+1), 0, 8, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 0, 2, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_BWSC_40(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 2, 3, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_BWSC_80(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 5, 3, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+3), 0, 8, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_MACID0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+4), 0, 8, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+5), 0, 8, __Value) + +// FCS_MACID_BITMAP16 +#define SET_8723B_H2CCMD_FCS_MACID_BITMAP0(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE(__pH2CCmd, 0, 16, __Value) +#define SET_8723B_H2CCMD_FCS_MACID_BITMAP1(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((__pH2CCmd)+2, 0, 16, __Value) +#define SET_8723B_H2CCMD_FCS_MACID_BITMAP2(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((__pH2CCmd)+4, 0, 16, __Value) + +// FCS_LOC_CMD17 (v2) +#define SET_8723B_H2CCMD_RSVDPAGE_FCS_LOC_V2_NULL_DATA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_FCS_LOC_V2_NULL_DATA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_FCS_LOC_V2_NULL_DATA2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +// FCS_INFO_CMD18 (v2) +#define SET_8723B_H2CCMD_FCS_INFO_V2_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_TOTAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+1), 0, 8, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 0, 2, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_BWSC_40(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 2, 3, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_BWSC_80(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+2), 5, 3, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+3), 0, 8, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+4), 0, 3, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_IN_CUR_CH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+4), 3, 1, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_DISTXNULL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+6), 4, 1, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+6), 5, 2, __Value) +#define SET_8723B_H2CCMD_FCS_INFO_V2_ChNLSCAN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd+6), 7, 1, __Value) + +// _PWR_MOD_CMD20 +#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_TWO_ANTENNA_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + +#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) + +// AOAC_GLOBAL_INFO +#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +// AOAC_RSVDPAGE_LOC +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_NS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_PROT_OFFLOAD_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value) + +// AOAC_RSVDPAGE_LOC For Real-WOW +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REALWOW_RSPACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REALWOW_BUBBPACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REALWOW_TEREDONFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +// AOAC_RSVDPAGE_LOC For Real-WOW V2 +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REALWOW_V2INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REALWOW_V2KEEPPACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REALWOW_V2ACKPATTERN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REALWOW_V2WAKEUPPATTERN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value) + +// + +// RSVDPAGE_LOC_3 +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_3_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_3_AOAC_REPORT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +#define GET_8723B_H2CCMD_RSVDPAGE_LOC_3_AOAC_REPORT(__pH2CCmd) LE_BITS_TO_1BYTE((__pH2CCmd)+1, 0, 8) + +//_SCAN_OFFLOAD_CTRL +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_D0_SCAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_RTD3_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_U3_SCAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_NLO_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_IPS_DEPENDENT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_CHNL_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_SSID_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +#define GET_8723B_H2CCMD_SCAN_OFFLOAD_CTRL_PARM_ENABLE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) + +//_CHANNEL_PATTERN +#define SET_8723B_H2CCMD_CHANNEL_PATTERN_PARM_CHNL_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_CHANNEL_PATTERN_PARM_TXPWRIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_CHANNEL_PATTERN_PARM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_CHANNEL_PATTERN_PARM_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +// BT_FW_PATCH +//#define SET_8723B_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+5, 0, 8, __Value) + +//_INACTIVE_PS_CTRL +#define SET_8723B_H2CCMD_INACTIVE_PS_PARM_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_INACTIVE_PS_PARM_IGNORE_PS_CONDITION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_INACTIVE_PS_PARM_SCAN_FREQUENCY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_INACTIVE_PS_PARM_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +#define GET_8723B_H2CCMD_INACTIVE_PS_PARM_FUNC_ENABLE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 1) + +// Disconnect_Decision_Control +// <Note> +// 1. The value "CHECK_PERIOD" should be larger than 5 which Fw checks beacon lost period. +// 2. "TRY_OK_BCN_LOST_CNT" should be smaller than "CHECK_PERIOD". +#define SET_8723B_H2CCMD_DISCONNECT_DECISION_CTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_DISCONNECT_DECISION_CTRL_USER_SETTING(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_DISCONNECT_DECISION_CTRL_CNT_BCN_LOST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_8723B_H2CCMD_DISCONNECT_DECISION_CTRL_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) // unit: beacon period +#define SET_8723B_H2CCMD_DISCONNECT_DECISION_CTRL_TRYPKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_DISCONNECT_DECISION_CTRL_TRY_OK_BCN_LOST_CNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +// WIFI_CALIBRATION +#define SET_8723B_H2CCMD_WIFI_CALIBRATION_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) + + +//------------------------------------ +// C2H format +//------------------------------------ + +// TX Beamforming +#define GET_8723B_C2H_TXBF_ORIGINATE(_Header) LE_BITS_TO_1BYTE(_Header, 0, 8) +#define GET_8723B_C2H_TXBF_MACID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8) + +/// TX Feedback Content +#define USEC_UNIT_FOR_8723B_C2H_TX_RPT_QUEUE_TIME 256 + +#define GET_8723B_C2H_TX_RPT_QUEUE_SELECT(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 5) +#define GET_8723B_C2H_TX_RPT_PKT_BROCAST(_Header) LE_BITS_TO_1BYTE((_Header + 0), 5, 1) +#define GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1) +#define GET_8723B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1) +#define GET_8723B_C2H_TX_RPT_MAC_ID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8) +#define GET_8723B_C2H_TX_RPT_DATA_RETRY_CNT(_Header) LE_BITS_TO_1BYTE((_Header + 2), 0, 6) +#define GET_8723B_C2H_TX_RPT_QUEUE_TIME(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) // In unit of 256 microseconds. +#define GET_8723B_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) + +#define GET_8723B_C2H_FCS_STATUS(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8) + +typedef enum _RTL8723B_H2C_CMD +{ + H2C_8723B_RSVDPAGE = 0, + H2C_8723B_MSRRPT = 1, + H2C_8723B_SCAN = 2, + H2C_8723B_KEEP_ALIVE_CTRL = 3, + H2C_8723B_DISCONNECT_DECISION = 4, + + H2C_8723B_INIT_OFFLOAD = 6, + H2C_8723B_AP_OFFLOAD = 8, + H2C_8723B_BCN_RSVDPAGE = 9, + H2C_8723B_PROBERSP_RSVDPAGE = 10, + + H2C_8723B_FCS_LOCATION = 0x10, + H2C_8723B_FCS_INFO = 0x11, + H2C_8723B_FCS_UPDATE_PARAM = 0x15, + H2C_8723B_FCS_MACID_BITMAP = 0x16, + H2C_8723B_FCS_INFO_V2 = 0x18, + + H2C_8723B_SETPWRMODE = 0x20, + H2C_8723B_PS_TUNING_PARA = 0x21, + H2C_8723B_PS_TUNING_PARA2 = 0x22, + H2C_8723B_PS_LPS_PARA = 0x23, + H2C_8723B_P2P_PS_OFFLOAD = 0x24, + H2C_8723B_INACTIVE_PS = 0x27, + + H2C_8723B_RA_MASK = 0x40, + H2C_8723B_RSSI_REPORT = 0x42, + + H2C_8723B_BT_FW_PATCH = 0x6a, + H2C_8723B_WIFI_CALIBRATION = 0x6d, + + H2C_8723B_WO_WLAN = 0x80, + H2C_8723B_REMOTE_WAKE_CTRL = 0x81, + H2C_8723B_AOAC_GLOBAL_INFO = 0x82, + H2C_8723B_AOAC_RSVDPAGE = 0x83, + H2C_8723B_AOAC_RSVDPAGE2 = 0x84, + H2C_8723B_SCAN_OFFLOAD_CTRL = 0x86, + H2C_8723B_AOAC_RSVDPAGE3 = 0x88, + + //Not defined in new 88E H2C CMD Format + H2C_8723B_SELECTIVE_SUSPEND_ROF_CMD, + H2C_8723B_P2P_PS_MODE, + H2C_8723B_PSD_RESULT, + MAX_8723B_H2CCMD +}RTL8723B_H2C_CMD; + + +typedef enum _RTL8723B_C2H_EVT +{ + C2H_8723B_DBG = 0, + C2H_8723B_LB = 1, + C2H_8723B_TXBF = 2, + C2H_8723B_TX_REPORT = 3, + C2H_8723B_BT_INFO = 9, + C2H_8723B_BT_MP = 11, + C2H_8723B_RA_RPT = 12, + C2H_8723B_RA_PARA_RPT = 14, + C2H_8723B_FCS = 0x17, + C2H_8723B_DBG_CODE = 0xFE, + C2H_8723B_EXTEND = 0xFF, + MAX_8723B_C2HEVENT +}RTL8723B_C2H_EVT; + + +typedef enum _RTL8723B_EXTEND_C2H_EVT +{ + EXTEND_C2H_8723B_DBG_PRINT = 0 + +}RTL8723B_EXTEND_C2H_EVT; + + +//========================================================== + +VOID +SetBcnCtrlReg_8192C( + IN PADAPTER Adapter, + IN u1Byte SetBits, + IN u1Byte ClearBits +); + + +RT_STATUS +BTFwPatch8723B( + IN PADAPTER Adapter +); + + +RT_STATUS +FirmwareDownload8723B( + IN PADAPTER Adapter, + IN BOOLEAN bUsedWoWLANFw +); + + +VOID +FillH2CCmd8723B( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +u4Byte +FillH2CCommand8723B( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + + +VOID +SetFwPwrModeCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte Mode +); + +VOID +SetFwMediaStatusRptCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte mstatus, + IN BOOLEAN macId_Ind, + IN u1Byte macId, + IN u1Byte macId_End + ); + +VOID +SetFwRemoteWakeCtrlCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte Enable +); + +VOID +SetFwGlobalInfoCmd_8723B( + IN PADAPTER Adapter +); + +VOID +SetFwScanOffloadCtrlCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte Type, + IN u1Byte ScanOffloadEnable, + IN u1Byte NLOEnable +); + +VOID +SetFwInactivePSCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte Enable, + IN BOOLEAN bActiveWakeup, + IN BOOLEAN bForceClkOff +); + +VOID +SetFwDisconnectDecisionCtrlCmd_8723B( + IN PADAPTER Adapter, + IN BOOLEAN bEnabled +); + +VOID +SetFwWiFiCalibrationCmd_8723B( + IN PADAPTER Adapter, + IN u1Byte u1Enable +); + +VOID +C2HPacketHandler_8723B( + IN PADAPTER Adapter, + IN pu1Byte Buffer, + IN u1Byte Length + ); + +VOID +ExtendC2HPacketHandler_8723B( + IN pu1Byte Buffer, + IN u1Byte c2hCmdLen + ); + + +VOID +C2HCommandHandler_8723B( + IN PADAPTER Adapter +); + +VOID +CheckFwRsvdPageContent_8723B( + IN PADAPTER Adapter +); + +VOID +SetFwRsvdPagePkt_8723B( + IN PADAPTER Adapter, + IN BOOLEAN bDLFinished +); + +VOID +FillFakeTxDescriptor_8723B( + IN PADAPTER Adapter, + IN pu1Byte pDesc, + IN u4Byte BufferLen, + IN BOOLEAN IsPsPoll, + IN BOOLEAN IsBTQosNull, + IN BOOLEAN bDataFrame +); +#if(FW_QUEME_MECHANISM_NEW != 1) +VOID +AddH2CCmdQueue_8723B( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +BOOLEAN +RetriveH2CCmdQueue_8723B( + IN PADAPTER Adapter, + IN pu1Byte pH2CCmdBuf +); +VOID +_WriteFW_8723B( + IN PADAPTER Adapter, + IN PVOID buffer, + IN u4Byte size +); +VOID +_FWDownloadEnable_8723B( + IN PADAPTER Adapter, + IN BOOLEAN enable +); + +#endif +#endif + +VOID +SetFwFcsLocCmd_8723B( + IN PADAPTER Adapter +); + +VOID +SetFwFcsInfoCmd_8723B( + IN PADAPTER Adapter, + IN pu1Byte pContext, + IN BOOLEAN bSet +); + diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BPhyCfg.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BPhyCfg.h new file mode 100644 index 00000000..997443ff --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BPhyCfg.h @@ -0,0 +1,301 @@ +/***************************************************************************** + * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8188EPHYCFG_H + * + * + * Note: + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * + *****************************************************************************/ + /* Check to see if the file has been included already. */ +#ifndef __INC_HAL8723BPHYCFG_H +#define __INC_HAL8723BPHYCFG_H + + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_92E 10 //ms +#define index_mapping_NUM_92E 15 +#define AVG_THERMAL_NUM_92E 4 + +#define MAX_TXPWR_IDX_NMODE_92E 63 + +#define IQK_MAC_REG_NUM_92E 4 +#define IQK_ADDA_REG_NUM_92E 16 + +#define HP_THERMAL_NUM_92E 8 + +#define IQK_BB_REG_NUM_92E 9 + +#define RF_PATH_MAX_92E 2 + + +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +//1 1. BB register R/W API + +extern u4Byte +PHY_QueryBBReg8723B( IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask ); + + +VOID +PHY_SetBBReg8723B( IN PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data ); + + +extern u4Byte +PHY_QueryRFReg8723B( IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask ); + + +void +PHY_SetRFReg8723B( IN PADAPTER Adapter, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data ); + +//1 3. Initial BB/RF config by reading MAC/BB/RF txt. +RT_STATUS +phy_BB8723B_Config_ParaFile( + IN PADAPTER Adapter + ); + +RT_STATUS +PHY_RFConfig8723B( + IN PADAPTER Adapter + ); + +// +// RF Power setting +// +BOOLEAN +PHY_SetRFPowerState8723B( IN PADAPTER Adapter, + IN RT_RF_POWER_STATE eRFPowerState); + +//1 5. Tx Power setting API +VOID +PHY_SetTxPowerIndex_8723B( + IN PADAPTER Adapter, + IN u4Byte PowerIndex, + IN u1Byte RFPath, + IN u1Byte Rate + ); + +u1Byte +PHY_GetTxPowerIndex_8723B( + IN PADAPTER pAdapter, + IN u1Byte RFPath, + IN u1Byte Rate, + IN CHANNEL_WIDTH BandWidth, + IN u1Byte Channel + ); + +VOID +PHY_GetTxPowerLevel8723B( + IN PADAPTER Adapter, + OUT ps4Byte powerlevel + ); + +VOID +PHY_SetTxPowerLevel8723B( + IN PADAPTER Adapter, + IN u1Byte channel + ); + +BOOLEAN +PHY_UpdateTxPowerDbm8723B( IN PADAPTER Adapter, + IN s4Byte powerInDbm ); + +//1 5. BandWidth setting API + +VOID +PHY_SetBWModeWorkItemCallback8723B( + IN PVOID pContext + ); + + +VOID +PHY_SetBWModeTimerCallback8723B( IN PRT_TIMER pTimer ); + +VOID +PHY_HandleSetBWMode8723B( IN PADAPTER pAdapter, + IN CHANNEL_WIDTH ChnlWidth, + IN EXTCHNL_OFFSET Offset ); + + +//1 6. Channel setting API + +void +PHY_SwChnlTimerCallback8723B( IN PRT_TIMER pTimer ); + +void +PHY_HandleSwChnl8723B( IN PADAPTER pAdapter, + IN u1Byte channel ); + +void +PHY_SwChnlSynchronously8723B( IN PADAPTER pAdapter, + IN u1Byte channel ); +VOID +PHY_SwChnlWorkItemCallback8723B( + IN PVOID pContext + ); + +#if 0 + +//1 7. IQK + +void +PHY_IQCalibrate_8188E( IN PADAPTER pAdapter, + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8188E( IN PADAPTER pAdapter); + +// +// AP calibrate +// +void +PHY_APCalibrate_8188E( IN PADAPTER pAdapter, + IN s1Byte delta); +void +PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); + +#endif + +extern VOID +PHY_SetRFPathSwitch_8723B( IN PADAPTER pAdapter, + IN BOOLEAN bMain); + +extern BOOLEAN +PHY_QueryRFPathSwitch_8723B( IN PADAPTER pAdapter); + + +void +PHY_SetMonitorMode8723B(IN PADAPTER pAdapter, + IN BOOLEAN bEnableMonitorMode ); + +#if (USE_WORKITEM || PCI_USE_WATCHDOG_WI) +VOID +RtCheckForHangWorkItemCallback8723B( + IN PVOID pContext +); +#endif + +VOID +PHY_ScanOperationBackup8723B( IN PADAPTER Adapter, + IN u1Byte Operation ); + + + +BOOLEAN +HalSetIO8723B( IN PADAPTER Adapter, + IN IO_TYPE IOType); + +VOID +PHY_HandleSwChnl8723B( // Call after initialization + IN PADAPTER pAdapter, + IN u1Byte channel + ); + + +#if USE_WORKITEM +void SetIOWorkItemCallback8723B( IN PVOID pContext ); +#endif +void SetIOTimerCallback8723B( IN PRT_TIMER pTimer); + + + +BOOLEAN +SetAntennaConfig8723B( + IN PADAPTER Adapter, + IN u1Byte DefaultAnt + ); + +RT_STATUS +PHY_SwitchWirelessBand8723B( + IN PADAPTER Adapter, + IN u1Byte Band + ); + +u4Byte PHY_GetTxBBSwing_8723B( + IN PADAPTER Adapter, + IN BAND_TYPE Band, + IN u1Byte RFPath + ); + +VOID +HAL_HandleSwChnl8723B( // Call after initialization + IN PADAPTER pAdapter, + IN u1Byte channel + ); + +VOID +PHY_HandleSwChnlAndSetBW8723B( + IN PADAPTER Adapter, + IN BOOLEAN bSwitchChannel, + IN BOOLEAN bSetBandWidth, + IN u1Byte ChannelNum, + IN CHANNEL_WIDTH ChnlWidth, + IN EXTCHNL_OFFSET ExtChnlOffsetOf40MHz, + IN EXTCHNL_OFFSET ExtChnlOffsetOf80MHz, + IN u1Byte CenterFrequencyIndex1 + ); + +VOID +PHY_BB8723B_Config_1T( + IN PADAPTER Adapter + ); + +VOID +PHY_SwChnlAndSetBWModeCallback8723B( + IN PVOID pContext + ); + +VOID +PHY_InitAntennaSelection8723B( + IN PADAPTER Adapter + ); + +VOID +PHY_SetIO_8723B( + PADAPTER pAdapter + ); + +#endif // __INC_HAL8188EPHYCFG_H + diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BPhyReg.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BPhyReg.h new file mode 100644 index 00000000..bb86cab7 --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BPhyReg.h @@ -0,0 +1,983 @@ +/***************************************************************************** + * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8192SPHYREG_H + * + * + * Note: 1. Define PMAC/BB register map + * 2. Define RF register map + * 3. PMAC/BB register bit mask. + * 4. RF reg bit mask. + * 5. Other BB/RF relative definition. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * 09/25/2008 MH 1. Add RL6052 register definition + * + *****************************************************************************/ +#ifndef __INC_HAL8723BPHYREG_H +#define __INC_HAL8723BPHYREG_H + + +/*--------------------------Define Parameters-------------------------------*/ + +//============================================================ +// 8192S Regsiter offset definition +//============================================================ + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + + +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 1. Page1(0x100) +// +#define rSYM_WLBT_PAPE_SEL 0x64 +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + + +// +// 3. Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? + +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? + +#define rFPGA0_RFTiming1 0x810 // Useless now +#define rFPGA0_RFTiming2 0x814 + +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c + +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 + +#define rFPGA0_RFWakeUpParameter 0x850 // Useless now +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 + +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 +#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 // Useless now +#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback +#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + +// +// 4. Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? + +#define rFPGA1_TxBlock 0x904 // Useless now +#define rFPGA1_DebugSelect 0x908 // Useless now +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? +#define rDPDT_control 0x92c +#define rfe_ctrl_anta_src 0x930 +#define rS0S1_PathSwitch 0x948 +#define rAGC_table_select 0xb2c + +// +// 5. PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI +#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain + +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c + +// +// PageB(0xB00) +// +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rConfig_Pmpd_AntB 0xb98 +#define rAPK 0xbd8 + + + +// +// 6. PageC(0xC00) +// +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI + +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA + +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 + + +// +// 7. PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 // No setting now +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support + +#define rOFDM_ShortCFOAB 0xdac // No setting now +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +// +// 8. PageE(0xE00) +// +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + +// +// 7. RF Register 0x00-0x2E (RF 8256) +// RF-0222D 0x00-3F +// +//Zebra1 +#define rZebra1_HSSIEnable 0x0 // Useless now +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 // RF channel switch + +//#endif +#define rZebra1_TxGain 0x8 // Useless now +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +//Zebra4 +#define rGlobalCtrl 0 // Useless now +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_TxLPF 0x11 // Useless now +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +// +// RL6052 Register definition +// +#define RF_AC 0x00 // + +#define RF_IQADJ_G1 0x01 // +#define RF_IQADJ_G2 0x02 // + +#define RF_POW_TRSW 0x05 // + +#define RF_GAIN_RX 0x06 // +#define RF_GAIN_TX 0x07 // + +#define RF_TXM_IDAC 0x08 // +#define RF_IPA_G 0x09 // +#define RF_TXBIAS_G 0x0A +#define RF_TXPA_AG 0x0B +#define RF_IPA_A 0x0C // +#define RF_TXBIAS_A 0x0D +#define RF_BS_PA_APSET_G9_G11 0x0E +#define RF_BS_IQGEN 0x0F // + +#define RF_MODE1 0x10 // +#define RF_MODE2 0x11 // + +#define RF_RX_AGC_HP 0x12 // +#define RF_TX_AGC 0x13 // +#define RF_BIAS 0x14 // +#define RF_IPA 0x15 // +#define RF_TXBIAS 0x16 +#define RF_POW_ABILITY 0x17 // +#define RF_CHNLBW 0x18 // RF channel and BW switch +#define RF_TOP 0x19 // + +#define RF_RX_G1 0x1A // +#define RF_RX_G2 0x1B // + +#define RF_RX_BB2 0x1C // +#define RF_RX_BB1 0x1D // + +#define RF_RCK1 0x1E // +#define RF_RCK2 0x1F // + +#define RF_TX_G1 0x20 // +#define RF_TX_G2 0x21 // +#define RF_TX_G3 0x22 // + +#define RF_TX_BB1 0x23 // + +//#if HARDWARE_TYPE_IS_RTL8192D == 1 +#define RF_T_METER_92D 0x42 // +//#else +#define RF_T_METER_88E 0x42 // +#define RF_T_METER 0x24 // + +//#endif + +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C // +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_WE_LUT 0xEF +#define RF_S0S1 0xB0 + + +// +//Bit Mask +// +// 1. Page1(0x100) +#define bBBResetB 0x100 // Useless now? +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +// 2. Page8(0x800) +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 // Useless now +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bAntennaSelect 0x0300 + +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 // Useless now +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 // Useless now +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW + +#define bRFSI_TRSW 0x20 // Useless now +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +#define bLSSIReadAddress 0x7f800000 // T65 RF + +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal + +#define bLSSIReadBackData 0xfffff // T65 RF + +#define bLSSIReadOKFlag 0x1000 // Useless now +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define b80MClkDelay 0x18000000 // Useless +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 // Useless +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +// 3. Page9(0x900) +#define bOFDMTxSC 0x30000000 // Useless +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +// 4. PageA(0xA00) +#define bCCKBBMode 0x3 // Useless +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch + +#define bCCKScramble 0x8 // Useless +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +// 5. PageC(0xC00) +#define bNumOfSTF 0x3 // Useless +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +// 6. PageE(0xE00) +#define bSTBCEn 0x4 // Useless +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +//#define bRxPath1 0x01 +//#define bRxPath2 0x02 +//#define bRxPath3 0x04 +//#define bRxPath4 0x08 +//#define bTxPath1 0x10 +//#define bTxPath2 0x20 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +/*--------------------------Define Parameters-------------------------------*/ + + +#endif //__INC_HAL8188EPHYREG_H + diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BPwrSeq.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BPwrSeq.h new file mode 100644 index 00000000..f570e384 --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BPwrSeq.h @@ -0,0 +1,183 @@ +#ifndef REALTEK_POWER_SEQUENCE_8723B +#define REALTEK_POWER_SEQUENCE_8723B + + +/* + Check document WM-20150115-JackieLau-RTL8723B_Power_Architecture v10.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 25 +#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15 +#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15 +#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8723B_TRANS_END_STEPS 1 + + +#define RTL8723B_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ + {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ + {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ + {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */ \ + {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ + {0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* RF HW Power down disabled*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ + {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ + {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ + {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ + {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\ + + +#define RTL8723B_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ + + +#define RTL8723B_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8723B_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + + +#define RTL8723B_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8723B_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8723B_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ + + +#define RTL8723B_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8723B_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; + +#endif diff --git a/network/wlan/WDI/HAL/rtl8723B/Hal8723BRf.h b/network/wlan/WDI/HAL/rtl8723B/Hal8723BRf.h new file mode 100644 index 00000000..a06a299b --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/Hal8723BRf.h @@ -0,0 +1,54 @@ +/****************************************************************************** + * + * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + * + * Module: HalRf.h ( Header File) + * + * Note: Collect every HAL RF type exter API or constant. + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 09/25/2008 MHC Create initial version. + * + * +******************************************************************************/ +/* Check to see if the file has been included already. */ + + +/*--------------------------Define Parameters-------------------------------*/ + +// +// For RF 6052 Series +// +/*--------------------------Define Parameters-------------------------------*/ + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +// +// RF RL6052 Series API +// +void PHY_RF6052SetBandwidth8723B( + IN PADAPTER Adapter, + IN CHANNEL_WIDTH Bandwidth); + +RT_STATUS PHY_RF6052_Config_8723B( IN PADAPTER Adapter ); + +/*--------------------------Exported Function prototype---------------------*/ + + +/* End of HalRf.h */ diff --git a/network/wlan/WDI/HAL/rtl8723B/rtl8723bs/Hal8723BSdioDef.h b/network/wlan/WDI/HAL/rtl8723B/rtl8723bs/Hal8723BSdioDef.h new file mode 100644 index 00000000..74726b90 --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/rtl8723bs/Hal8723BSdioDef.h @@ -0,0 +1,426 @@ +#ifndef __INC_HAL8723BSDIODEF_H +#define __INC_HAL8723BSDIODEF_H + + +/*--------------------------Define MACRO--------------------------------------*/ + +extern u1Byte DescString8723BSdio[]; +extern EEPROM_OFFSET EEPROMOffset8723BSdio; + +extern u1Byte DescString8192ESdio[]; +extern EEPROM_OFFSET EEPROMOffset8192ESdio; + +#define DRIVER_EARLY_INT_TIME_8723B 0x05 + +#define HAL92CSDIO_DEFAULT_BEACON_TYPE BEACON_SEND_AUTO_HW + +#define SDIO_8723B_DUMMY_UNIT 8 +#define SDIO_8723B_DUMMY_OFFSET 1 +#define SDIO_8723B_ALL_DUMMY_LENGTH SDIO_8723B_DUMMY_OFFSET * SDIO_8723B_DUMMY_UNIT +#define HWDESC_HEADER_LEN_SDIO_8812 40 +#define SDIO_8723B_HWDESC_HEADER_LEN (HWDESC_HEADER_LEN_SDIO_8812 + SDIO_8723B_ALL_DUMMY_LENGTH) // 8byte dummy + +#define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80 +#define MAX_RX_DMA_BUFFER_SIZE_8723B 0x2800 // RX 10K + +#define TX_TOTAL_PAGE_NUMBER_8723B 0xF3 // TX 32K + +#define TX_PAGE_BOUNDARY_8723B (TX_TOTAL_PAGE_NUMBER_8723B + 1) +#define TX_PAGE_BOUNDARY_WOWLAN_8723B 0xE0 + +// For Normal Chip Setting +// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER +#define NORMAL_PAGE_NUM_PUBQ_8723B 0xC2 //0xD9 +#define NORMAL_PAGE_NUM_LPQ_8723B 0x08 //0x0d +#define NORMAL_PAGE_NUM_HPQ_8723B 0x08 //0x0d +#define NORMAL_PAGE_NUM_NPQ_8723B 0x20 //0x00 + + +//Note: For WMM Normal Chip Setting ,modify later +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B TX_PAGE_BOUNDARY_8723B +#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723B (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B + 1) + +#define WMM_NORMAL_PAGE_NUM_PUBQ_8723B NORMAL_PAGE_NUM_PUBQ_8723B +#define WMM_NORMAL_PAGE_NUM_HPQ_8723B NORMAL_PAGE_NUM_HPQ_8723B +#define WMM_NORMAL_PAGE_NUM_LPQ_8723B NORMAL_PAGE_NUM_LPQ_8723B +#define WMM_NORMAL_PAGE_NUM_NPQ_8723B NORMAL_PAGE_NUM_NPQ_8723B + +// RQPN setting for WoWLAN +#define WOWLAN_NORMAL_PAGE_NUM_NPQ_8723B 0x03 +#define WOWLAN_RSVD_QUEUE_PAGE_NUM_8723B 0x80c20d0d + +#define TX_SELE_HQ BIT(0) // High Queue +#define TX_SELE_LQ BIT(1) // Low Queue +#define TX_SELE_NQ BIT(2) // Normal Queue + +#define RX_PAGE_SIZE_REG_VALUE PBP_128 +#define BCN_DMA_ATIME_INT_TIME 0x02 + + +#endif // #ifndef __INC_HAL8723BSDIODEF_H + +VOID +DumpHardwareProfile8723BSdio( + IN PADAPTER Adapter + ); + +VOID +DisableInterrupt8723BSdio ( + IN PADAPTER Adapter + ); + +VOID +ClearInterrupt8723BSdio( + IN PADAPTER Adapter + ); + +VOID +ClearSysInterrupt8723BSdio( + IN PADAPTER Adapter + ); + +VOID +InitInterrupt8723BSdio( + IN PADAPTER Adapter + ); + +VOID +InitSysInterrupt8723BSdio( + IN PADAPTER Adapter + ); + +VOID +EnableInterrupt8723BSdio( + IN PADAPTER Adapter + ); + +VOID +DumpLoggedInterruptHistory8723BSdio( + PADAPTER Adapter + ); + +BOOLEAN +InterruptRecognized8723BSdio( + IN PADAPTER Adapter, + IN PVOID pContent, + IN u4Byte ContentLen + ); + +//1====================================================== +// Tx Related +// Function prototypes for Hal8190PciGen.c +//1====================================================== + +VOID +InitializeVariables8723BSdio( + IN PADAPTER Adapter + ); + +VOID +DeInitializeVariables8723BSdio( + IN PADAPTER Adapter + ); + +VOID +CancelAllTimer8723BSdio( + IN PADAPTER Adapter + ); + +VOID +ReleaseAllTimer8723BSdio( + PADAPTER Adapter + ); + +VOID +HalSdioUpdateDefSet8723BS( + IN PADAPTER pAdapter + ); + +BOOLEAN +HalSdioSetQueueMapping8723BSdio( + IN PADAPTER pAdapter, + IN u1Byte NumIn, + IN u1Byte NumOut + ); + +VOID +GetInitialRQPValue8723BS( + IN PADAPTER Adapter, + OUT pu2Byte pNPQRQPNVaule, + OUT pu4Byte pRQPNValue + ); + +u1Byte +GetInitialTxBufferBoundary8723BS( + IN PADAPTER Adapter + ); + +RT_STATUS +InitializeAdapter8723BSdio( + IN PADAPTER Adapter, + IN u1Byte Channel + ); + +RT_STATUS +ReadAdapterInfo8723BS( + IN PADAPTER Adapter + ); + +VOID +FillH2CCmd8723BSdioWorkItemCallback( + IN PVOID pContext + ); + +VOID +FillH2CCmd8723BSdioTimerCallback( + IN PRT_TIMER pTimer + ); + +VOID +HaltAdapter8723BSdio( + IN PADAPTER Adapter, + IN BOOLEAN bReset + ); + +VOID +SleepAdapter8723BSdio( + IN PADAPTER Adapter + ); + +VOID +ShutdownAdapter8723BSdio( + IN PADAPTER Adapter, + IN BOOLEAN bReset + ); + +VOID +SetHwReg8723BSdio( + IN PADAPTER pAdapter, + IN u1Byte variable, + IN pu1Byte val + ); + +VOID +GetHwReg8723BSdio( + IN PADAPTER Adapter, + IN u1Byte variable, + OUT pu1Byte val + ); + +BOOLEAN +GetHalDefVar8723BSdio( + IN PADAPTER Adapter, + IN HAL_DEF_VARIABLE eVariable, + IN PVOID pValue + ); + +BOOLEAN +GetInterrupt8723BSdio( + IN PADAPTER pAdapter, + IN HAL_INT_TYPE intType + ); + +BOOLEAN +SetHalDefVar8723BSdio( + IN PADAPTER Adapter, + IN HAL_DEF_VARIABLE eVariable, + IN PVOID pValue + ); + +VOID +ActSetWirelessMode8723BSdio( + PADAPTER pAdapter, + u2Byte btWirelessMode + ); + +VOID +SetBeaconRelatedRegisters8723BSdio( + IN PADAPTER Adapter, + IN PVOID pOpMode, + IN u2Byte BcnInterval, + IN u2Byte AtimWindow + ); + +VOID +ResetAllHWTimer8723BSdio( + IN PADAPTER Adapter + ); + +VOID +UpdateLPSStatus8723BSdio( + IN PADAPTER Adapter, + IN u1Byte RegLeisurePsMode, + IN u1Byte RegPowerSaveMode + ); + +VOID +UpdateIPSStatus8723BSdio( + IN PADAPTER Adapter, + IN u1Byte RegInactivePsMode + ); + +VOID +EnableHWSecurityConfig8723BSdio( + IN PADAPTER Adapter + ); + +VOID +DisableHWSecurityConfig8723BSdio( + IN PADAPTER Adapter + ); + +VOID +SetKey8723BSdio( + IN PADAPTER Adapter, + IN u4Byte KeyIndex, + IN pu1Byte pMacAddr, + IN BOOLEAN IsGroup, + IN u4Byte EncAlgo, + IN BOOLEAN IsWEPKey, //if OID = OID_802_11_WEP + IN BOOLEAN ClearAll + ); + +VOID +TxFillCmdDesc8723BSdio( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN u1Byte QueueIndex, + IN u2Byte index, + IN BOOLEAN bFirstSeg, + IN BOOLEAN bLastSeg, + IN pu1Byte VirtualAddress, + IN u4Byte PhyAddressLow, + IN u4Byte BufferLen, + IN u4Byte DescPacketType, + IN u4Byte PktLen + ); + +VOID +TxFillDescriptor8723BSdio( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN u2Byte nBufIndex, + IN u2Byte nFragIndex, + IN u2Byte nFragBufferIndex, + IN u2Byte nCurDesc + ); + +VOID +AllowAllDestAddr8723BSdio( + IN PADAPTER Adapter, + IN BOOLEAN bAllowAllDA, + IN BOOLEAN WriteIntoReg + ); + +VOID +AllowErrorPacket8723BSdio( + IN PADAPTER Adapter, + IN BOOLEAN bAllowErrPkt, + IN BOOLEAN WriteIntoReg + ); + +VOID +QueryRxDescStatus8723BSdio( + IN PADAPTER Adapter, + IN PVOID pDescIn, + IN OUT PRT_RFD pRfd + ); + +u4Byte +GetRxPacketShiftBytes8723BSdio( + IN PRT_RFD pRfd + ); + +BOOLEAN +HalQueryRxDMARequest8723BSdio( + IN PADAPTER Adapter, + OUT pu2Byte pRxReqLength + ); + +BOOLEAN +GetNmodeSupportBySecCfg8723BSdio( + IN PADAPTER Adapter + ); + +VOID +GPIOCheckPBC8723BSdio( + IN PADAPTER pAdapter + ); + +VOID +GpioDetectTimerStart8723BSdio( + IN PADAPTER Adapter +); + +VOID +SetRTSRateWorkItemCallback_8723BS( + IN PVOID pContext + ); + +VOID +HalSdioGetCmdAddr8723BSdio( + IN PADAPTER pAdapter, + IN u1Byte DeviceID, + IN u4Byte Addr, + OUT pu4Byte pCmdAddr + ); + +VOID +HalRxAggr8723BSdio( + IN PADAPTER Adapter, + IN BOOLEAN Value + ); + +BOOLEAN +HalQueryTxBufferStatus8723BSdio( + IN PADAPTER Adapter + ); + +BOOLEAN +HalQueryTxBufferAvailable8723BSdio( + IN PADAPTER Adapter, + IN PSDIO_OUT_CONTEXT pContext + ); + +BOOLEAN +HalSdioRxHandleInterrupt8723BSdio( + IN PADAPTER pAdapter + ); + +VOID +HalDropRxFIFO8723BSdio( + IN PADAPTER Adapter + ); + +VOID +HalDownloadRSVDPage8723BS( + IN PADAPTER Adapter + ); + +VOID +ResetHalRATRTable8723BSdio( + PADAPTER Adapter + ); + +VOID +HandleH2CJoinBssRptWorkItemCallback_8723BS( + IN PVOID pContext +); + +BOOLEAN +CheckCPWMInterrupt8723BS( + IN PADAPTER Adapter + ); + +BOOLEAN +HalSdioIoRegCmd52Available8723BS( + IN PADAPTER Adapter, + IN u4Byte offset + ); + +RT_STATUS +HalSetRsvdPageBndy8723BS( + IN PADAPTER Adapter, + IN u1Byte RQPNType + ); + diff --git a/network/wlan/WDI/HAL/rtl8723B/rtl8723bs/Hal8723BSdioLed.h b/network/wlan/WDI/HAL/rtl8723B/rtl8723bs/Hal8723BSdioLed.h new file mode 100644 index 00000000..210efaae --- /dev/null +++ b/network/wlan/WDI/HAL/rtl8723B/rtl8723bs/Hal8723BSdioLed.h @@ -0,0 +1,41 @@ +#ifndef __INC_HAL8723BSDIOLED_H +#define __INC_HAL8723BSDIOLED_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8192CUsbLed.h + +Abstract: + LED related data structure and interface to manipulate LED. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2006-12-27 Rcnjko Create. + +--*/ + +//================================================================================ +// Interface to manipulate LED objects. +//================================================================================ + +VOID +SwLedOn_8723B( + IN PADAPTER Adapter, + IN PLED_SDIO pLed +); + +VOID +SwLedOff_8723B( + IN PADAPTER Adapter, + IN PLED_SDIO pLed +); + +VOID +SwLedInit_8723BS( + IN PADAPTER Adapter +); + +#endif + diff --git a/network/wlan/WDI/HAL/sources.list.WlanS b/network/wlan/WDI/HAL/sources.list.WlanS new file mode 100644 index 00000000..7a656f97 --- /dev/null +++ b/network/wlan/WDI/HAL/sources.list.WlanS @@ -0,0 +1,178 @@ +// +// Command: +(OS, ...) -(OS, ...) [FILE] +// //: Comment at the beginning +// OS: * Ebd6 Ebd7 WinXP Vista Win7 Win8 WinBlue +// +: Add for OS +// -: Remove for OS +// + ++(*) [..\HalEEPROM.c] ++(*) [..\HalCommon.c] ++(*) [..\HalCam.c] ++(*) [..\HalSdio.c] ++(*) [..\HalFw.c] ++(*) [..\HalSIC.c] ++(*) [..\HalPwrSeqCmd.c] ++(*) [..\HalPhy.c] ++(*) [..\HalDM.c] ++(*) [..\HalPowerSave.c] ++(*) [..\HalTxFeedback.c] ++(*) [..\HalMacID.c] ++(*) [..\HalWoWLAN.c] ++(*) [..\HalH2cIOCmd.c] ++(*) [..\HalComLed.c] ++(*) [..\HalSDIOLed.c] ++(*) [..\HalComTxDesc.c] ++(*) [..\HalComRxDesc.c] ++(*) [..\HalComPhyCfg.c] ++(*) [..\HalComTxPwrCfg.c] ++(*) [..\HalComTxPwrLmtCfg.c] ++(*) [..\HalADCSampling.c] ++(*) [..\HalEfuse.c] ++(*) [Hal8723BEfuse.c] ++(*) [Hal8723BDesc.c] ++(*) [Hal8723BSdioTxDesc.c] ++(*) [Hal8723BSdioRxDesc.c] ++(*) [Hal8723BSdioLed.c] + ++(*) [Hal8723BPhyCfg.c] ++(*) [Hal8723BCom.c] + ++(*) [Hal8723BFirmware.c] ++(*) [Hal8723BRf6052.c] ++(*) [Hal8723BSdioGen.c] ++(*) [Hal8723BSdioIsr.c] ++(*) [Hal8723BPwrSeq.c] + ++(*) [HalPhyRf_WIN.c] ++(*) [phydm_interface.c] ++(*) [phydm_debug.c] ++(*) [phydm_HWConfig.c] +//+(*) [phydm_RTL8188E.c] +//+(*) [phydm_RTL8192E.c] +//+(*) [phydm_RTL8814A.c] ++(*) [phydm_RTL8723B.c] +//+(*) [phydm_RTL8822B.c] +//+(*) [phydm_RTL8188F.c] +//+(*) [phydm_rtl8723d.c] ++(*) [phydm.c] ++(*) [phydm_DIG.c] ++(*) [phydm_PathDiv.c] ++(*) [phydm_EdcaTurboCheck.c] ++(*) [phydm_DynamicBBPowerSaving.c] ++(*) [phydm_PowerTracking_WIN.c] ++(*) [phydm_DynamicTxPower.c] ++(*) [phydm_RaInfo.c] ++(*) [phydm_AntDiv.c] ++(*) [phydm_AntDect.c] ++(*) [phydm_CfoTracking.c] ++(*) [phydm_ACS.c] ++(*) [phydm_RXHP.c] ++(*) [PhyDM_Adaptivity.c] +//+(*) [PhyDM_IQK_8821A_WIN.c] +//+(*) [PhyDM_IQK_8814A.c] +//+(*) [PhyDM_IQK_8822b.c] +//+(*) [phydm_Beamforming.c] +//+(*) [HalTxbfJaguar.c] +//+(*) [HalTxbf8192E.c] +//+(*) [HalTxbf8814A.c] +//+(*) [HalTxbf8821B.c] +//+(*) [haltxbf8822b.c] +//+(*) [HalTxbfinterface.c] +//+(*) [HalComTxbf.c] + +//+(*) [HalPhyRf_8188e_WIN.c] +//+(*) [HalPhyRf_8192e_WIN.c] +//+(*) [HalPhyRf_8814a_WIN.c] +//+(*) [HalPhyRf_8812A_WIN.c] +//+(*) [HalPhyRf_8821A_WIN.c] ++(*) [HalPhyRf_8723B_WIN.c] +//+(*) [HalPhyRf_8703B.c] +//+(*) [halphyrf_8822b.c] +//+(*) [HalPhyRf_8188F.c] +//+(*) [HalPhyRf_8723D.c] + + +//+(*) [HalPhyRf_8821B.c] + +//+(*) [Hal8188ERateAdaptive.c] +//+(*) [HalHWImg8188E_MAC.c] +//+(*) [HalHWImg8188E_RF.c] +//+(*) [HalHWImg8188E_BB.c] +//+(*) [HalHWImg8188E_T_FW.c] +//+(*) [HalHWImg8188E_S_FW.c] +//+(*) [phydm_RegConfig8188E.c] +//+(*) [HalHWImg8812A_MAC.c] +//+(*) [HalHWImg8812A_RF.c] +//+(*) [HalHWImg8812A_BB.c] +//+(*) [HalHWImg8812A_FW.c] +//+(*) [phydm_RegConfig8812A.c] +//+(*) [phydm_RTL8812A.c] +//+(*) [HalHWImg8821A_MAC.c] +//+(*) [HalHWImg8821A_BB.c] +//+(*) [HalHWImg8821A_RF.c] +//+(*) [HalHWImg8821A_FW.c] +//+(*) [phydm_RTL8821A.c] +//+(*) [phydm_RegConfig8821A.c] +//+(*) [HalHWImg8192E_FW.c] +//+(*) [HalHWImg8192E_MAC.c] +//+(*) [HalHWImg8192E_RF.c] +//+(*) [HalHWImg8192E_BB.c] +//+(*) [phydm_RegConfig8192E.c] +//+(*) [HalHWImg8723D_FW.c] +//+(*) [HalHWImg8723D_MAC.c] +//+(*) [HalHWImg8723D_RF.c] +//+(*) [HalHWImg8723D_BB.c] +//+(*) [phydm_RegConfig8723D.c] + +//+(*) [HalHWImg8821B_FW.c] +//+(*) [HalHWImg8821B_MAC.c] +//+(*) [HalHWImg8821B_RF.c] +//+(*) [HalHWImg8821B_BB.c] +//+(*) [HalHWImg8821B_TestChip_MAC.c] +//+(*) [HalHWImg8821B_TestChip_RF.c] +//+(*) [HalHWImg8821B_TestChip_BB.c] +//+(*) [HalHWImg8821B_TestChip_FW.c] +//+(*) [phydm_RegConfig8821B.c] +//+(*) [halmac_api_8822b_pcie.c] +//+(*) [halmac_api_8822b_sdio.c] +//+(*) [halmac_api_8822b_usb.c] +//+(*) [halmac_8822b_pwr_seq.c] +//+(*) [halmac_api_8822b.c] +//+(*) [halmac_88xx_pwr_seq.c] +//+(*) [halmac_api_88xx_pcie.c] +//+(*) [halmac_api_88xx_sdio.c] +//+(*) [halmac_api_88xx_usb.c] +//+(*) [halmac_func_88xx.c] +//+(*) [halmac_api_88xx.c] +//+(*) [halmac_api.c] +//+(*) [..\HalMacApiWrapper.c] +//+(*) [HalHWImg8814A_FW.c] +//+(*) [HalHWImg8814A_MAC.c] +//+(*) [HalHWImg8814A_RF.c] +//+(*) [HalHWImg8814A_BB.c] +//+(*) [phydm_RegConfig8814A.c] ++(*) [HalHWImg8723B_MAC.c] ++(*) [HalHWImg8723B_RF.c] ++(*) [HalHWImg8723B_BB.c] ++(*) [HalHWImg8723B_FW.c] ++(*) [phydm_RegConfig8723B.c] +//+(*) [HalHWImg8703B_FW.c] +//+(*) [HalHWImg8703B_BB.c] +//+(*) [HalHWImg8703B_MAC.c] +//+(*) [HalHWImg8703B_RF.c] +//+(*) [phydm_RegConfig8703B.c] +// +//+(*) [HalHWImg8188F_FW.c] +//+(*) [HalHWImg8188F_MAC.c] +//+(*) [HalHWImg8188F_RF.c] +//+(*) [HalHWImg8188F_BB.c] +//+(*) [phydm_RegConfig8188F.c] +// +// +//+(*) [halhwimg8822b_mac.c] +//+(*) [halhwimg8822b_rf.c] +//+(*) [halhwimg8822b_bb.c] +//+(*) [phydm_regconfig8822b.c] +//+(*) [phydm_hal_api8822b.c] + diff --git a/network/wlan/WDI/HAL/sources.tpl.WlanS.props b/network/wlan/WDI/HAL/sources.tpl.WlanS.props new file mode 100644 index 00000000..12645c53 --- /dev/null +++ b/network/wlan/WDI/HAL/sources.tpl.WlanS.props @@ -0,0 +1,24 @@ +<?xml version="1.0" encoding="utf-8"?> +<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003"> + <PropertyGroup> + <TARGETNAME>hal</TARGETNAME> + <TARGETPATH>$(TMP_TARGET_DIR)</TARGETPATH> + <TARGETTYPE>DRIVER_LIBRARY</TARGETTYPE> + <PRECOMPILED_INCLUDE>Mp_Precomp.h</PRECOMPILED_INCLUDE> + <PRECOMPILED_PCH>precomp.pch</PRECOMPILED_PCH> + <PRECOMPILED_OBJ>precomp.obj</PRECOMPILED_OBJ> + <INCLUDES> + .; + ..; + $(SRC_ROOT)\Header; + $(SRC_ROOT)\Common; + $(HAL_INC_DIRS); + </INCLUDES> + </PropertyGroup> + <Import Project="$(SRC_ROOT)\$(PLATFORM_INC).props" /> + <PropertyGroup> + <SOURCES> + <!--TAG_REALTEK_SOURCE_FILES--> + </SOURCES> + </PropertyGroup> +</Project>
\ No newline at end of file diff --git a/network/wlan/WDI/HAL/sources.tpl.WlanS.win b/network/wlan/WDI/HAL/sources.tpl.WlanS.win new file mode 100644 index 00000000..aa8370f2 --- /dev/null +++ b/network/wlan/WDI/HAL/sources.tpl.WlanS.win @@ -0,0 +1,28 @@ +TARGETNAME=hal +TARGETPATH=. +TARGETTYPE=LIBRARY + +# 2011/11/17 MH Disable temporarily for compatiable with other SW teams. +PRECOMPILED_INCLUDE= Mp_Precomp.h +PRECOMPILED_PCH=precomp.pch +PRECOMPILED_OBJ=precomp.obj + +INCLUDES=\ + .; \ + ..; \ + $(SRC_ROOT)\Header; \ + $(SRC_ROOT)\Common; \ + $(HAL_INC_DIRS); \ + $(OMNIPEEK_INC_DIRS); \ + +# +# OS and Bus dependent setting. +# +!include $(SRC_ROOT)\$(PLATFORM_INC) + + +# +# Because we will copy HAL source file to HALSOURCE. But we can not copy HAL +# root directory to HALSOURCE, otherwise, WDK6000 warning. +# +SOURCES = <!--TAG_REALTEK_SOURCE_FILES-->
\ No newline at end of file |