update(port/dwc2/usb_glue_infineon): add some check for m55

Signed-off-by: sakumisu <[email protected]>

2 files changed, 23 insertions, 4 deletions

diff --git a/port/dwc2/usb_glue_infineon.c b/port/dwc2/usb_glue_infineon.c
index c08ebc08..5e54f572 100644
--- a/port/dwc2/usb_glue_infineon.c
+++ b/port/dwc2/usb_glue_infineon.c
@@ -8,10 +8,25 @@
 #include "usb_dwc2_param.h"
 #include "rtthread.h"
 #include "cybsp.h"
+#include "cy_device.h"
+
+#if defined (COMPONENT_CM55)
+
+#if !defined(CONFIG_USB_DCACHE_ENABLE)
+#error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" for CM55"
+#endif
+
+#else
+#define CONFIG_USB_DWC2_DMA_ENABLE
+#endif
 
 const struct dwc2_user_params param_common = {
     .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
+#ifdef CONFIG_USB_DWC2_DMA_ENABLE
     .device_dma_enable = true,
+#else
+    .device_dma_enable = false,
+#endif
     .device_dma_desc_enable = false,
     .device_rx_fifo_size = 0x21F,
     .device_tx_fifo_size = {
@@ -69,6 +84,8 @@ void usb_dc_low_level_init(uint8_t busid)
     USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos);
     USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk);
 
+    rt_thread_mdelay(200); // Wait for PHY stable
+
     cy_stc_sysint_t usb_int_cfg = {
         .intrSrc = usbhs_interrupt_usbhsctrl_IRQn,
         .intrPriority = 3
@@ -106,6 +123,8 @@ void usb_hc_low_level_init(struct usbh_bus *bus)
     USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos);
     USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk);
 
+    rt_thread_mdelay(200); // Wait for PHY stable
+
     cy_stc_sysint_t usb_int_cfg = {
         .intrSrc = usbhs_interrupt_usbhsctrl_IRQn,
         .intrPriority = 3
diff --git a/port/dwc2/usb_hc_dwc2.c b/port/dwc2/usb_hc_dwc2.c
index bf0adae5..92a7f3e0 100644
--- a/port/dwc2/usb_hc_dwc2.c
+++ b/port/dwc2/usb_hc_dwc2.c
@@ -717,10 +717,10 @@ int usb_hc_init(struct usbh_bus *bus)
 
     USB_ASSERT_MSG((USB_OTG_GLB->GRXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size,
                    "host_rx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->GRXFSIZ & 0xffff));
-    USB_ASSERT_MSG((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size,
-                   "host_nperio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ & 0xffff));
-    USB_ASSERT_MSG((USB_OTG_GLB->HPTXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size,
-                   "host_perio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->HPTXFSIZ & 0xffff));
+    USB_ASSERT_MSG(((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16) & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size,
+                   "host_nperio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16) & 0xffff));
+    USB_ASSERT_MSG(((USB_OTG_GLB->HPTXFSIZ >> 16) & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size,
+                   "host_perio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)((USB_OTG_GLB->HPTXFSIZ >> 16) & 0xffff));
 
     /* B-peripheral session valid override enable */
     USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN;