summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorsakumisu <[email protected]>2023-12-30 14:44:52 +0800
committersakumisu <[email protected]>2023-12-30 14:44:52 +0800
commit1492b8cca9ab8c014bf4a5ef38e4f2ec871bb858 (patch)
tree0ba3d0d4044130699ca686c010e4c0ca9243b1f2
parent67a3bbe02ecaf7052b28090c01faf9ca5e2140df (diff)
remove ch32 host, nrf5x, rp2040 port
Diffstat
-rw-r--r--port/ch32/usb_hc_usbfs.c1333
-rw-r--r--port/ch32/usb_hc_usbhs.c1393
-rw-r--r--port/nrf5x/README.md9
-rw-r--r--port/nrf5x/nrf5x_regs.h605
-rw-r--r--port/nrf5x/usb_dc_nrf5x.c1308
-rw-r--r--port/rp2040/usb_dc_rp2040.c605
-rw-r--r--port/rp2040/usb_rp2040_reg.h4350
7 files changed, 0 insertions, 9603 deletions
diff --git a/port/ch32/usb_hc_usbfs.c b/port/ch32/usb_hc_usbfs.c
deleted file mode 100644
index 0f5395a8..00000000
--- a/port/ch32/usb_hc_usbfs.c
+++ /dev/null
@@ -1,1333 +0,0 @@
-#include "usbh_core.h"
-#include "usbh_hub.h"
-#include "usb_ch32_usbfs_reg.h"
-
-#if defined(CH581) || defined(CH582) || defined(CH583) || defined(CH571) || defined(CH572) || defined(CH573)
-#undef USBFS_BASE
-#undef USBFS_HOST
-
-#ifndef USBFS_BASE
-#pragma message "USB2 is used by default"
-#define USBFS_BASE ((uint32_t)0x40008400u)
-#endif
-
-#define USBFS_HOST ((USB_FS_TypeDef *)USBFS_BASE)
-
-#undef USBFS_UH_PRE_PID_EN
-#undef USBFS_UH_SOF_EN
-#define USBFS_UH_PRE_PID_EN 0x80 /*!< USB host PRE PID enable for low speed device via hub */
-#define USBFS_UH_SOF_EN 0x40 /*!< USB host automatic SOF enable */
-
-#undef USBFS_UH_R_AUTO_TOG
-#undef USBFS_UH_R_TOG
-#undef USBFS_UH_R_RES
-#define USBFS_UH_R_AUTO_TOG 0x10 /*!< enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle */
-#define USBFS_UH_R_TOG 0x80 /*!< expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 */
-#define USBFS_UH_R_RES 0x04 /*!< prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions */
-
-#undef USBFS_UH_T_AUTO_TOG
-#undef USBFS_UH_T_TOG
-#undef USBFS_UH_T_RES
-#define USBFS_UH_T_AUTO_TOG 0x10 /*!< enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle */
-#define USBFS_UH_T_TOG 0x40 /*!< prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 */
-#define USBFS_UH_T_RES 0x01 /*!< expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions */
-
-void USBH_IRQHandler(void) __attribute__((section(".highcode")));
-#elif defined(CH32F203) || defined(CH32F205) || defined(CH32F207) || defined(CH32F208)
-void USBH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
-#elif defined(CH32V203) || defined(CH32V303) || defined(CH32V305) || defined(CH32V307) || defined(CH32V208)
-void USBH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
-#else
-#error "Do not support"
-#endif
-
-#ifndef USBH_IRQHandler
-#pragma message "Please make sure your platform interrupt name"
-#define USBH_IRQHandler USB2_IRQHandler
-#endif
-
-#ifndef CONFIG_USBHOST_PIPE_NUM
-#define CONFIG_USBHOST_PIPE_NUM 8
-#endif
-
-typedef enum {
- USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */
- USB_EP0_STATE_IN_DATA, /**< IN DATA */
- USB_EP0_STATE_IN_STATUS, /**< IN status */
- USB_EP0_STATE_OUT_DATA, /**< OUT DATA */
- USB_EP0_STATE_OUT_STATUS, /**< OUT status */
-} ep0_state_t;
-
-struct chusb_pipe {
- uint8_t dev_addr;
- uint8_t ep_addr;
- uint8_t ep_type;
- uint8_t ep_interval;
- uint8_t speed;
- uint16_t ep_mps;
- bool inuse;
- uint32_t xfrd;
- volatile bool waiter;
-
- uint32_t xferlen;
- uint8_t *buffer;
- uint8_t data_pid;
-
- usb_osal_sem_t waitsem;
- struct usbh_hubport *hport;
- struct usbh_urb *urb;
-};
-
-struct chusb_hcd {
- volatile bool port_csc;
- volatile bool port_pec;
- volatile bool port_pe;
- volatile uint8_t current_token;
- volatile uint8_t ep0_state;
- volatile bool prv_get_zero;
- volatile bool prv_set_zero;
- volatile bool main_pipe_using;
- // uint32_t current_pipe_timeout;
- uint8_t dev_speed;
- struct chusb_pipe *current_pipe;
- struct chusb_pipe pipe_pool[CONFIG_USBHOST_PIPE_NUM][2]; /* Support Bidirectional ep */
-} g_chusb_hcd;
-
-static inline void SET_UH_RX_CTRL_BIT(uint8_t bit)
-{
- if ((USBFS_HOST->HOST_RX_CTRL & USBFS_UH_R_AUTO_TOG) != 0) {
- /**
- * USBFS_UH_R_TOG canot write
- */
- if ((bit & USBFS_UH_R_TOG) != 0) {
- /**
- * bit contains USBFS_UH_R_TOG
- */
- USBFS_HOST->HOST_RX_CTRL &= ~(USBFS_UH_R_AUTO_TOG);
- USBFS_HOST->HOST_RX_CTRL |= (USBFS_UH_R_AUTO_TOG | bit);
- } else {
- USBFS_HOST->HOST_RX_CTRL |= bit;
- }
- } else {
- USBFS_HOST->HOST_RX_CTRL |= bit;
- }
-}
-
-static inline void SET_UH_TX_CTRL_BIT(uint8_t bit)
-{
- if ((USBFS_HOST->HOST_TX_CTRL & USBFS_UH_T_AUTO_TOG) != 0) {
- /**
- * USBFS_UH_T_TOG canot write
- */
- if ((bit & USBFS_UH_T_TOG) != 0) {
- /**
- * bit contains USBFS_UH_T_TOG
- */
- USBFS_HOST->HOST_TX_CTRL &= ~(USBFS_UH_T_AUTO_TOG);
- USBFS_HOST->HOST_TX_CTRL |= (USBFS_UH_T_AUTO_TOG | bit);
- } else {
- USBFS_HOST->HOST_TX_CTRL |= bit;
- }
- } else {
- USBFS_HOST->HOST_TX_CTRL |= bit;
- }
-}
-
-static inline void CLEAR_UH_TX_CTRL_BIT(uint8_t bit)
-{
- if ((USBFS_HOST->HOST_TX_CTRL & USBFS_UH_T_AUTO_TOG) != 0) {
- /**
- * USBFS_UH_T_TOG canot write
- */
- if ((bit & USBFS_UH_T_TOG) != 0) {
- /**
- * bit contains USBFS_UH_T_TOG
- */
- USBFS_HOST->HOST_TX_CTRL &= ~(USBFS_UH_T_AUTO_TOG);
- USBFS_HOST->HOST_TX_CTRL &= ~(bit);
- USBFS_HOST->HOST_TX_CTRL |= USBFS_UH_T_AUTO_TOG;
- } else {
- USBFS_HOST->HOST_TX_CTRL &= ~(bit);
- }
- } else {
- USBFS_HOST->HOST_TX_CTRL &= ~(bit);
- }
-}
-
-static inline void CLEAR_UH_RX_CTRL_BIT(uint8_t bit)
-{
- if ((USBFS_HOST->HOST_RX_CTRL & USBFS_UH_R_AUTO_TOG) != 0) {
- /**
- * USBFS_UH_R_TOG can't write
- */
- if ((bit & USBFS_UH_R_TOG) != 0) {
- /**
- * bit contains USBFS_UH_R_TOG
- */
- USBFS_HOST->HOST_RX_CTRL &= ~(USBFS_UH_R_AUTO_TOG);
- USBFS_HOST->HOST_RX_CTRL &= ~(bit);
- USBFS_HOST->HOST_RX_CTRL |= USBFS_UH_R_AUTO_TOG;
- } else {
- USBFS_HOST->HOST_RX_CTRL &= ~(bit);
- }
- } else {
- USBFS_HOST->HOST_RX_CTRL &= ~(bit);
- }
-}
-
-static inline void SET_UH_RX_CTRL(uint8_t value)
-{
- USBFS_HOST->HOST_RX_CTRL = 0;
- USBFS_HOST->HOST_RX_CTRL = value;
- USB_LOG_DBG("USBFS_HOST->HOST_RX_CTRL:%02x\r\n", USBFS_HOST->HOST_RX_CTRL);
-}
-
-static inline void SET_UH_TX_CTRL(uint8_t value)
-{
- USBFS_HOST->HOST_TX_CTRL = 0;
- USBFS_HOST->HOST_TX_CTRL = value;
- USB_LOG_DBG("USBFS_HOST->HOST_TX_CTRL:%02x\r\n", USBFS_HOST->HOST_TX_CTRL);
-}
-
-static inline void INT_PRE_HANDLER(void)
-{
-#if defined(CH581) || defined(CH582) || defined(CH583) || defined(CH571) || defined(CH572) || defined(CH573)
-#else
- asm("csrrw sp,mscratch,sp");
- extern void rt_interrupt_enter(void);
- rt_interrupt_enter();
-#endif
-}
-
-static inline void INT_POST_HANDLER(void)
-{
-#if defined(CH581) || defined(CH582) || defined(CH583) || defined(CH571) || defined(CH572) || defined(CH573)
-#else
- extern void rt_interrupt_leave(void);
- rt_interrupt_leave();
- asm("csrrw sp,mscratch,sp");
-#endif
-}
-
-static int8_t chusb_host_pipe_transfer(struct chusb_pipe *pipe, uint8_t pid, uint8_t *data, uint32_t len)
-{
- /*!< Updata current transfer pid */
- g_chusb_hcd.current_token = pid;
- /*!< Updata curretn pipe */
- g_chusb_hcd.current_pipe = pipe;
- /*!< Updata curretn pipe timeout */
- // g_chusb_hcd.current_pipe_timeout = pipe->urb->timeout;
- /*!< Updata main pipe using flag */
- // g_chusb_hcd.main_pipe_using = true;
-
- if (data == NULL && len > 0) {
- return -1;
- }
-
- if (pid == USB_PID_SETUP) {
- /*!< Record the data len */
- g_chusb_hcd.current_pipe->xferlen = len;
-
- if ((uint32_t)data & 0x03) {
- USB_LOG_INFO("SETUP DMA address is not align \r\n");
- return -3;
- }
-
- USBFS_HOST->HOST_TX_DMA = (uint16_t)(uint32_t)data;
-
- /*!< Record the data buffer address */
- pipe->buffer = data;
-
- if (len > pipe->ep_mps) {
- len = pipe->ep_mps;
- }
-
- USBFS_HOST->HOST_TX_LEN = len;
- USBFS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
-
- } else if (pid == USB_PID_OUT) {
- /*!< Record the data len */
- g_chusb_hcd.current_pipe->xferlen = len;
-
- if (len == 0) {
- USBFS_HOST->HOST_TX_LEN = len;
- USBFS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
- return 0;
- }
-
- if ((uint32_t)data & 0x03) {
- USB_LOG_INFO("OUT DMA address is not align \r\n");
- return -3;
- }
-
- USBFS_HOST->HOST_TX_DMA = (uint16_t)(uint32_t)data;
-
- /*!< Record the data buffer address */
- pipe->buffer = data;
-
- if (len > pipe->ep_mps) {
- len = pipe->ep_mps;
- }
-
- USBFS_HOST->HOST_TX_LEN = len;
- USBFS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
-
- } else if (pid == USB_PID_IN) {
- /*!< Record the data len */
- g_chusb_hcd.current_pipe->xferlen = len;
-
- if (len == 0) {
- /*!< Want get 0 length data */
- } else {
- if ((uint32_t)data & 0x03) {
- USB_LOG_INFO("IN DMA address is not align \r\n");
- return -3;
- }
- USBFS_HOST->HOST_RX_DMA = (uint16_t)(uint32_t)data;
- pipe->buffer = data;
- }
-
- USBFS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
- }
-
- return 0;
-}
-
-static void chusb_control_pipe_init(struct chusb_pipe *pipe, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen)
-{
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_SETUP) {
- /**
- * Setup is distributed as DATA0
- */
- SET_UH_TX_CTRL(USBFS_UH_T_AUTO_TOG);
- pipe->data_pid = 0;
- chusb_host_pipe_transfer(pipe, USB_PID_SETUP, (uint8_t *)setup, 8);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_DATA) {
- if (pipe->data_pid != 1) {
- USB_LOG_ERR("IN_DATA PID Error\r\n");
- }
- SET_UH_RX_CTRL(USBFS_UH_R_AUTO_TOG | USBFS_UH_R_TOG);
- chusb_host_pipe_transfer(pipe, USB_PID_IN, buffer, buflen);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_DATA) {
- if (pipe->data_pid != 1) {
- USB_LOG_ERR("OUT_DATA PID Error\r\n");
- }
- chusb_host_pipe_transfer(pipe, USB_PID_OUT, buffer, buflen);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_STATUS) {
- /**
- * Status stage must be DATA1
- */
- // SET_UH_RX_CTRL_BIT(USBFS_UH_R_TOG);
- pipe->data_pid = 1;
- SET_UH_RX_CTRL(USBFS_UH_R_AUTO_TOG | USBFS_UH_R_TOG);
- chusb_host_pipe_transfer(pipe, USB_PID_IN, NULL, 0);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_STATUS) {
- /**
- * Status stage must be DATA1
- */
- // SET_UH_TX_CTRL_BIT(USBFS_UH_T_TOG);
- pipe->data_pid = 1;
- SET_UH_TX_CTRL(USBFS_UH_T_AUTO_TOG | USBFS_UH_T_TOG);
- chusb_host_pipe_transfer(pipe, USB_PID_OUT, NULL, 0);
- }
-}
-
-static void chusb_bulk_pipe_init(struct chusb_pipe *pipe, uint8_t *buffer, uint32_t buflen)
-{
- if (pipe->ep_addr & 0x80) {
- /*!< IN */
- g_chusb_hcd.current_token = USB_PID_IN;
- if (pipe->data_pid == 1) {
- SET_UH_RX_CTRL(USBFS_UH_R_AUTO_TOG | USBFS_UH_R_TOG);
- } else {
- SET_UH_RX_CTRL(USBFS_UH_R_AUTO_TOG);
- }
- } else {
- /*!< OUT */
- g_chusb_hcd.current_token = USB_PID_OUT;
- if (pipe->data_pid == 1) {
- SET_UH_TX_CTRL(USBFS_UH_T_AUTO_TOG | USBFS_UH_T_TOG);
- } else {
- SET_UH_TX_CTRL(USBFS_UH_T_AUTO_TOG);
- }
- }
-
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
-}
-
-static void chusb_intr_pipe_init(struct chusb_pipe *pipe, uint8_t *buffer, uint32_t buflen)
-{
- if (pipe->ep_addr & 0x80) {
- /*!< IN */
- g_chusb_hcd.current_token = USB_PID_IN;
- if (pipe->data_pid == 1) {
- SET_UH_RX_CTRL(USBFS_UH_R_AUTO_TOG | USBFS_UH_R_TOG);
- } else {
- SET_UH_RX_CTRL(USBFS_UH_R_AUTO_TOG);
- }
- } else {
- /*!< OUT */
- g_chusb_hcd.current_token = USB_PID_OUT;
- if (pipe->data_pid == 1) {
- SET_UH_TX_CTRL(USBFS_UH_T_AUTO_TOG | USBFS_UH_T_TOG);
- } else {
- SET_UH_TX_CTRL(USBFS_UH_T_AUTO_TOG);
- }
- }
-
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
-}
-
-static void chusb_iso_pipe_init(struct chusb_pipe *pipe, uint8_t *buffer, uint32_t buflen)
-{
- if (pipe->ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
- USB_LOG_ERR("Endpoint type is not ISOCHRONOUS\r\n");
- return;
- }
-
- if (pipe->ep_addr & 0x80) {
- /*!< IN */
- g_chusb_hcd.current_token = USB_PID_IN;
- SET_UH_RX_CTRL(USBFS_UH_R_AUTO_TOG | USBFS_UH_R_RES);
- } else {
- /*!< OUT */
- g_chusb_hcd.current_token = USB_PID_OUT;
- SET_UH_TX_CTRL(USBFS_UH_T_AUTO_TOG | USBFS_UH_T_RES);
- }
-
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
-}
-
-static void chusbh_set_self_speed(uint8_t speed)
-{
- if (speed == USB_SPEED_HIGH) {
- } else if (speed == USB_SPEED_FULL) {
- USBFS_HOST->BASE_CTRL &= ~USBFS_UC_LOW_SPEED;
- USBFS_HOST->HOST_CTRL &= ~USBFS_UH_LOW_SPEED;
- USBFS_HOST->HOST_SETUP &= ~USBFS_UH_PRE_PID_EN;
- } else {
- USBFS_HOST->BASE_CTRL |= USBFS_UC_LOW_SPEED;
- USBFS_HOST->HOST_CTRL |= USBFS_UH_LOW_SPEED;
- USBFS_HOST->HOST_SETUP |= USBFS_UH_PRE_PID_EN;
- }
-}
-
-static int usbh_reset_port(const uint8_t port)
-{
- /*!< Disable detect interrupt */
- USBFS_HOST->INT_EN &= (~USBFS_UIE_DETECT);
- USBFS_HOST->HOST_CTRL &= ~USBFS_UH_SOF_EN;
-
- g_chusb_hcd.port_pe = 0;
- /*!< Set dev add 0 */
- USBFS_HOST->DEV_ADDR = (USBFS_HOST->DEV_ADDR & USBFS_UDA_GP_BIT) | (0x00 & USBFS_USB_ADDR_MASK);
- chusbh_set_self_speed(USB_SPEED_FULL);
- /*!< Close port */
- USBFS_HOST->HOST_CTRL &= ~USBFS_UH_PORT_EN;
- /*!< Start reset */
- USBFS_HOST->HOST_CTRL |= USBFS_UH_BUS_RESET;
- usb_osal_msleep(30);
- /*!< Stop reset */
- USBFS_HOST->HOST_CTRL &= ~USBFS_UH_BUS_RESET;
- usb_osal_msleep(20);
-
- if ((USBFS_HOST->HOST_CTRL & USBFS_UH_PORT_EN) == 0) {
- volatile uint8_t speed = (USBFS_HOST->MIS_ST & USBFS_UMS_DM_LEVEL) ? 0 : 1;
- if (speed == 0) {
- /*!< Low speed */
- USB_LOG_INFO("Dev USB_SPEED_LOW \r\n");
- USBFS_HOST->HOST_CTRL |= USBFS_UH_LOW_SPEED;
- g_chusb_hcd.dev_speed = USB_SPEED_LOW;
- chusbh_set_self_speed(USB_SPEED_LOW);
- } else {
- /*!< Full speed */
- USB_LOG_INFO("Dev USB_SPEED_FULL \r\n");
- USBFS_HOST->HOST_CTRL &= ~USBFS_UH_LOW_SPEED;
- g_chusb_hcd.dev_speed = USB_SPEED_FULL;
- }
- }
-
- /*!< Enable HUB Port */
- USBFS_HOST->HOST_CTRL |= USBFS_UH_PORT_EN;
- // USBFS_HOST->HOST_SETUP |= USBFS_UH_SOF_EN;
- USBFS_HOST->INT_EN |= USBFS_UIE_DETECT;
- g_chusb_hcd.port_pe = 1;
- return 0;
-}
-
-static uint8_t usbh_get_port_speed(const uint8_t port)
-{
- (void)port;
- USBFS_HOST->HOST_SETUP |= USBFS_UH_SOF_EN;
- return g_chusb_hcd.dev_speed;
-}
-
-__WEAK void usb_hc_low_level_init(void)
-{
-}
-
-int usb_hc_init(void)
-{
- memset(&g_chusb_hcd, 0, sizeof(struct chusb_hcd));
-
- for (uint8_t i = 0; i < CONFIG_USBHOST_PIPE_NUM; i++) {
- g_chusb_hcd.pipe_pool[i][0].waitsem = usb_osal_sem_create(0);
- g_chusb_hcd.pipe_pool[i][1].waitsem = usb_osal_sem_create(0);
- }
-
- usb_hc_low_level_init();
- USBFS_HOST->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
- static uint32_t wait_ct = 50000;
- while (wait_ct--) {
- }
- USBFS_HOST->BASE_CTRL = 0;
-
- USBFS_HOST->BASE_CTRL = USBFS_UC_HOST_MODE;
- USBFS_HOST->HOST_CTRL = 0;
-
- USBFS_HOST->DEV_ADDR = 0x00;
-
- USBFS_HOST->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN;
-
- USBFS_HOST->HOST_RX_CTRL = 0;
- USBFS_HOST->HOST_TX_CTRL = 0;
-
- USBFS_HOST->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
- // USBFS_HOST->HOST_SETUP = USBFS_UH_SOF_EN;
- USBFS_HOST->INT_FG = 0xFF;
-
- USBFS_HOST->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT;
- return 0;
-}
-
-int usbh_roothub_control(struct usb_setup_packet *setup, uint8_t *buf)
-{
- uint8_t nports;
- uint8_t port;
- uint32_t status;
-
- nports = CONFIG_USBHOST_MAX_RHPORTS;
- port = setup->wIndex;
- if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) {
- switch (setup->bRequest) {
- case HUB_REQUEST_CLEAR_FEATURE:
- switch (setup->wValue) {
- case HUB_FEATURE_HUB_C_LOCALPOWER:
- break;
- case HUB_FEATURE_HUB_C_OVERCURRENT:
- break;
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_SET_FEATURE:
- switch (setup->wValue) {
- case HUB_FEATURE_HUB_C_LOCALPOWER:
- break;
- case HUB_FEATURE_HUB_C_OVERCURRENT:
- break;
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_GET_DESCRIPTOR:
- break;
- case HUB_REQUEST_GET_STATUS:
- memset(buf, 0, 4);
- break;
- default:
- break;
- }
- } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) {
- switch (setup->bRequest) {
- case HUB_REQUEST_CLEAR_FEATURE:
- if (!port || port > nports) {
- return -EPIPE;
- }
-
- switch (setup->wValue) {
- case HUB_PORT_FEATURE_ENABLE:
- break;
- case HUB_PORT_FEATURE_SUSPEND:
- case HUB_PORT_FEATURE_C_SUSPEND:
- break;
- case HUB_PORT_FEATURE_POWER:
- break;
- case HUB_PORT_FEATURE_C_CONNECTION:
- g_chusb_hcd.port_csc = 0;
- break;
- case HUB_PORT_FEATURE_C_ENABLE:
- g_chusb_hcd.port_pec = 0;
- break;
- case HUB_PORT_FEATURE_C_OVER_CURREN:
- break;
- case HUB_PORT_FEATURE_C_RESET:
- break;
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_SET_FEATURE:
- if (!port || port > nports) {
- return -EPIPE;
- }
-
- switch (setup->wValue) {
- case HUB_PORT_FEATURE_SUSPEND:
- break;
- case HUB_PORT_FEATURE_POWER:
- break;
- case HUB_PORT_FEATURE_RESET:
- usbh_reset_port(port);
- break;
-
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_GET_STATUS:
- if (!port || port > nports) {
- return -EPIPE;
- }
-
- status = 0;
- if (g_chusb_hcd.port_csc) {
- status |= (1 << HUB_PORT_FEATURE_C_CONNECTION);
- }
- if (g_chusb_hcd.port_pec) {
- status |= (1 << HUB_PORT_FEATURE_C_ENABLE);
- }
-
- if (g_chusb_hcd.port_pe) {
- status |= (1 << HUB_PORT_FEATURE_CONNECTION);
- status |= (1 << HUB_PORT_FEATURE_ENABLE);
- if (usbh_get_port_speed(port) == USB_SPEED_LOW) {
- status |= (1 << HUB_PORT_FEATURE_LOWSPEED);
- } else if (usbh_get_port_speed(port) == USB_SPEED_HIGH) {
- status |= (1 << HUB_PORT_FEATURE_HIGHSPEED);
- }
- }
-
- memcpy(buf, &status, 4);
- break;
- default:
- break;
- }
- }
- return 0;
-}
-
-int usbh_ep_pipe_reconfigure(usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t mult)
-{
- struct chusb_pipe *ppipe = (struct chusb_pipe *)pipe;
-
- ppipe->dev_addr = dev_addr;
- ppipe->ep_mps = ep_mps;
-
- USBFS_HOST->DEV_ADDR = (USBFS_DEV_ADDR_OFFSET & USBFS_UDA_GP_BIT) | (dev_addr & USBFS_USB_ADDR_MASK);
- return 0;
-}
-
-int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg)
-{
- struct chusb_pipe *ppipe;
- uint8_t ep_idx;
- usb_osal_sem_t waitsem;
-
- ep_idx = ep_cfg->ep_addr & 0x7f;
-
- if (ep_idx > CONFIG_USBHOST_PIPE_NUM) {
- return -ENOMEM;
- }
-
- if (ep_cfg->ep_addr & 0x80) {
- ppipe = &g_chusb_hcd.pipe_pool[ep_idx][1];
- } else {
- ppipe = &g_chusb_hcd.pipe_pool[ep_idx][0];
- }
-
- /* store variables */
- waitsem = ppipe->waitsem;
-
- memset(ppipe, 0, sizeof(struct chusb_pipe));
-
- ppipe->ep_addr = ep_cfg->ep_addr;
- ppipe->ep_type = ep_cfg->ep_type;
- ppipe->ep_mps = ep_cfg->ep_mps;
- ppipe->ep_interval = ep_cfg->ep_interval;
- ppipe->speed = ep_cfg->hport->speed;
- ppipe->dev_addr = ep_cfg->hport->dev_addr;
- ppipe->hport = ep_cfg->hport;
-
- if (ep_cfg->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- } else {
- if (ppipe->speed == USB_SPEED_HIGH) {
- } else if (ppipe->speed == USB_SPEED_FULL) {
- } else if (ppipe->speed == USB_SPEED_LOW) {
- }
- }
- /* restore variable */
- ppipe->inuse = true;
- ppipe->waitsem = waitsem;
-
- *pipe = (usbh_pipe_t)ppipe;
- return 0;
-}
-
-int usbh_pipe_free(usbh_pipe_t pipe)
-{
- return 0;
-}
-
-int usbh_submit_urb(struct usbh_urb *urb)
-{
- struct chusb_pipe *pipe;
- size_t flags;
- int ret = 0;
-
- if (!urb) {
- USB_LOG_INFO("urb is null \r\n");
- return -EINVAL;
- }
-
- pipe = urb->pipe;
-
- if (!pipe) {
- USB_LOG_INFO("pipe is null \r\n");
- return -EINVAL;
- }
-
- if (!pipe->hport->connected) {
- USB_LOG_INFO("!pipe->hport->connected \r\n");
- return -ENODEV;
- }
-
- if (pipe->urb) {
- USB_LOG_INFO("pipe->urb is not null\r\n");
- return -EBUSY;
- }
-
-#if 0
- if (g_chusb_hcd.main_pipe_using == true) {
- USB_LOG_INFO("usbh_submit_urb//main pipe is using\r\n");
- return -EBUSY;
- }
-#endif
-
- flags = usb_osal_enter_critical_section();
-
- pipe->waiter = false;
- pipe->xfrd = 0;
- pipe->urb = urb;
- urb->errorcode = -EBUSY;
- urb->actual_length = 0;
-
- if (urb->timeout > 0) {
- pipe->waiter = true;
- }
- usb_osal_leave_critical_section(flags);
-
- switch (pipe->ep_type) {
- case USB_ENDPOINT_TYPE_CONTROL:
- g_chusb_hcd.ep0_state = USB_EP0_STATE_SETUP;
- chusb_control_pipe_init(pipe, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- case USB_ENDPOINT_TYPE_BULK:
- chusb_bulk_pipe_init(pipe, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- case USB_ENDPOINT_TYPE_INTERRUPT:
- chusb_intr_pipe_init(pipe, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- case USB_ENDPOINT_TYPE_ISOCHRONOUS:
- chusb_iso_pipe_init(pipe, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- default:
- break;
- }
- if (urb->timeout > 0) {
- /* wait until timeout or sem give */
- ret = usb_osal_sem_take(pipe->waitsem, urb->timeout);
- if (ret < 0) {
- goto errout_timeout;
- }
-
- // g_chusb_hcd.current_pipe_timeout = 0;
-
- ret = urb->errorcode;
- }
- return ret;
-errout_timeout:
- pipe->waiter = false;
- g_chusb_hcd.current_token = 0;
- usbh_kill_urb(urb);
- return ret;
-}
-
-int usbh_kill_urb(struct usbh_urb *urb)
-{
- return 0;
-}
-
-static inline void chusb_pipe_waitup(struct chusb_pipe *pipe, bool callback)
-{
- struct usbh_urb *urb;
-
- urb = pipe->urb;
- pipe->urb = NULL;
- // g_chusb_hcd.main_pipe_using = false;
-
- if (pipe->waiter) {
- pipe->waiter = false;
- usb_osal_sem_give(pipe->waitsem);
- }
-
- if (callback == true) {
- if (urb->complete) {
- if (urb->errorcode < 0) {
- urb->complete(urb->arg, urb->errorcode);
- } else {
- urb->complete(urb->arg, urb->actual_length);
- }
- }
- }
-}
-
-static int8_t chusb_outpipe_irq_handler(uint8_t res_state)
-{
- uint16_t current_tx_length = USBFS_HOST->HOST_TX_LEN;
- struct usbh_urb *urb;
- urb = (g_chusb_hcd.current_pipe->urb);
-
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_CONTROL) {
- if ((g_chusb_hcd.current_pipe->ep_addr & 0x80) != 0) {
- /* Error */
- USB_LOG_ERR("ep_addr is not out add \r\n");
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -1;
- }
- }
-
- switch (res_state) {
- case USB_PID_STALL:
- urb->errorcode = -EPERM;
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- USB_LOG_ERR("USB_PID_SETUP STALL \r\n");
- } else {
- USB_LOG_ERR("USB_PID_OUT STALL \r\n");
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_CONTROL) {
- /**
- * Reset data pid
- */
- g_chusb_hcd.current_pipe->data_pid = 0;
- }
- }
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -2;
- case USB_PID_NAK:
- urb->errorcode = -EAGAIN;
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- /**
- * Device must ack for setup package
- */
- USB_LOG_ERR("Setup NAK \r\n");
- g_chusb_hcd.current_token = 0;
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -3;
- } else {
- if (g_chusb_hcd.current_pipe->waiter == true) {
- USB_LOG_DBG("Control endpoint out nak and retry\r\n");
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- }
- } else {
- if (g_chusb_hcd.prv_set_zero == true) {
- /**
- * It is unlikely to run here,
- * because the device can probably receive 0 length byte packets
- */
- urb->errorcode = 0;
- g_chusb_hcd.prv_set_zero = false;
- g_chusb_hcd.current_token = 0;
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- if (g_chusb_hcd.current_pipe->waiter == true) {
- USB_LOG_DBG("Normal endpoint out nak and retry\r\n");
- urb->errorcode = -EAGAIN;
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- g_chusb_hcd.current_token = 0;
- if (g_chusb_hcd.current_pipe->xfrd > 0) {
- /**
- * The device received data but did not receive it completely
- */
- urb->errorcode = 0;
- USB_LOG_WRN("The data is not sent completely, but the timeout is 0\r\n");
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- /**
- * The device may not be ready, make sure your device can receive data
- */
- USB_LOG_WRN("Your device seems unable to receive data\r\n");
- urb->errorcode = -EBUSY;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, false);
- }
- }
- }
- }
- break;
- case USB_PID_ACK:
- /**
- * The last out or setup package was sent
- */
- urb->errorcode = 0;
-
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- /*!< Ctrol endpoint */
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- /*!< Setup package send successfully */
- urb->actual_length += 8;
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_SETUP) {
- if (urb->setup->wLength) {
- if (urb->setup->bmRequestType & 0x80) {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_IN_DATA;
- } else {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_OUT_DATA;
- }
- } else {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_IN_STATUS;
- }
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- }
- } else if (g_chusb_hcd.current_token == USB_PID_OUT) {
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_DATA) {
- USB_LOG_DBG("ep0 tx_len:%d\r\n", current_tx_length);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- g_chusb_hcd.current_pipe->xfrd += current_tx_length;
- g_chusb_hcd.current_pipe->buffer += current_tx_length;
- g_chusb_hcd.current_pipe->xferlen -= current_tx_length;
- if (g_chusb_hcd.current_pipe->xferlen == 0) {
- if (current_tx_length == g_chusb_hcd.current_pipe->ep_mps) {
- /**
- * Need send 0 length data
- */
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT, NULL, 0);
- } else {
- /*!< Out package send successfully */
- g_chusb_hcd.ep0_state = USB_EP0_STATE_IN_STATUS;
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- }
- } else {
- /*!< Start send next out package */
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_STATUS) {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_SETUP;
- urb->actual_length += g_chusb_hcd.current_pipe->xfrd;
- USB_LOG_DBG("S-> I-> O-status stage: In:%d\r\n", urb->actual_length - 8);
- if (g_chusb_hcd.current_pipe->data_pid != 1) {
- USB_LOG_ERR("S-> I-> O-status stage DATA PID Error\r\n");
- } else {
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- }
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- }
- } else {
- if (g_chusb_hcd.current_token == USB_PID_OUT) {
- USB_LOG_DBG("ep%d tx_len:%d\r\n", (g_chusb_hcd.current_pipe->ep_addr & 0x0f), current_tx_length);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- g_chusb_hcd.current_pipe->xfrd += current_tx_length;
- g_chusb_hcd.current_pipe->buffer += current_tx_length;
- g_chusb_hcd.current_pipe->xferlen -= current_tx_length;
- if (g_chusb_hcd.current_pipe->xferlen == 0) {
- if (current_tx_length == g_chusb_hcd.current_pipe->ep_mps) {
- /**
- * Need send 0 length data
- */
- if (g_chusb_hcd.prv_set_zero == true) {
- USB_LOG_ERR("g_chusb_hcd.prv_set_zero is always true\r\n");
- }
- g_chusb_hcd.prv_set_zero = true;
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT, NULL, 0);
- } else {
- /*!< Out package send successfully */
- g_chusb_hcd.current_token = 0;
- if (g_chusb_hcd.prv_set_zero == true) {
- g_chusb_hcd.prv_set_zero = false;
- }
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- } else {
- /*!< Start send next out package */
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- } else {
- USB_LOG_ERR("Error token is not match \r\n");
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -4;
- }
- }
- break;
- case 0:
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- if ((g_chusb_hcd.ep0_state == USB_EP0_STATE_SETUP) && (g_chusb_hcd.current_pipe->waiter == true)) {
- USB_LOG_WRN("Setup Timeout and retry\r\n");
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- } else {
- USB_LOG_ERR("Setup Timeout\r\n");
- urb->errorcode = -EIO;
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -5;
- }
- } else {
- USB_LOG_ERR("Out Timeout \r\n");
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_CONTROL) {
- /**
- * Reset data pid
- */
- g_chusb_hcd.current_pipe->data_pid = 0;
- }
- }
- urb->errorcode = -EIO;
- } else {
- /**
- * No response from isochronous endpoint out
- */
- urb->errorcode = 0;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- default:
- break;
- }
-
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return 0;
-}
-
-static int8_t chusb_inpipe_irq_handler(uint8_t res_state)
-{
- uint16_t rx_len = 0;
- struct usbh_urb *urb;
- urb = (g_chusb_hcd.current_pipe->urb);
-
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_CONTROL) {
- if ((g_chusb_hcd.current_pipe->ep_addr & 0x80) == 0) {
- /* Error */
- USB_LOG_ERR("ep_addr is not in add\r\n");
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -1;
- }
- }
-
- switch (res_state) {
- case USB_PID_STALL:
- USB_LOG_ERR("USB_PID_IN USB_PID_STALL\r\n");
- g_chusb_hcd.current_token = 0;
- urb->errorcode = -EPERM;
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -2;
- case USB_PID_NAK:
- g_chusb_hcd.current_token = 0;
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- if (g_chusb_hcd.current_pipe->waiter == true) {
- urb->errorcode = -EAGAIN;
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- urb->errorcode = 0;
- }
- } else {
- urb->errorcode = 0;
- if (g_chusb_hcd.prv_get_zero == true) {
- g_chusb_hcd.prv_get_zero = false;
- g_chusb_hcd.current_token = 0;
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- USB_LOG_DBG("Normal endpoint get zero length package\r\n");
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- USB_LOG_DBG("Normal endpoint in nak\r\n");
- if (g_chusb_hcd.current_pipe->xferlen > 0) {
- /**
- * The data has not been transmitted completely
- */
- if (g_chusb_hcd.current_pipe->xfrd > 0) {
- /**
- * Data was transmitted last time, but this time NAK
- */
- if (g_chusb_hcd.current_pipe->waiter == true) {
- /**
- * Retry in
- */
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- /**
- * Some data has been transferred
- */
- USB_LOG_WRN("The device has not finished sending all data, but the timeout is 0\r\n");
- g_chusb_hcd.current_token = 0;
- /**
- * Update the actual send length
- */
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- urb->errorcode = 0;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- } else {
- /**
- * The device did not send any data.
- */
- if (g_chusb_hcd.current_pipe->waiter == true) {
- /**
- * Try again
- */
- USB_LOG_DBG("The device does not transmit data, try again\r\n");
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- /**
- * g_chusb_hcd.current_pipe->waiter = false
- * We do not need to call a callback
- */
- USB_LOG_DBG("Do not need try again\r\n");
- urb->errorcode = -EBUSY;
- g_chusb_hcd.current_token = 0;
- urb->actual_length = 0;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, false);
- }
- }
- } else {
- urb->errorcode = -EIO;
- USB_LOG_ERR("xferlen == 0//should get zero package\r\n");
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -1;
- }
- }
- }
- break;
- case USB_PID_ACK:
- urb->errorcode = 0;
- break;
- case USB_PID_DATA0:
- case USB_PID_DATA1:
- if ((USBFS_HOST->INT_ST) & USBFS_UIS_TOG_OK) {
- /*!< Data is OK */
- rx_len = USBFS_HOST->RX_LEN;
-
- urb->errorcode = 0;
-
- g_chusb_hcd.current_pipe->xfrd += rx_len;
-
- if (g_chusb_hcd.current_pipe->xferlen < rx_len) {
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- USB_LOG_ERR("Please provide the correct data length parameter\r\n");
- if (g_chusb_hcd.prv_get_zero == true) {
- g_chusb_hcd.prv_get_zero = false;
- }
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -6;
- }
-
- g_chusb_hcd.current_pipe->xferlen -= rx_len;
-
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- /*!< Ctrol endpoint */
- /**
- * Status stage
- *
- * Setup ---> out data ---> in status stage
- */
- if ((g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_STATUS) && (rx_len == 0)) {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_SETUP;
- urb->actual_length += rx_len;
- USB_LOG_DBG("S-> O-> In-status stage: Out:%d\r\n", urb->actual_length - 8);
-
- if (g_chusb_hcd.current_pipe->data_pid != 1) {
- USB_LOG_ERR("S-> O-> In-status stage DATA PID Error//PID:%d\r\n", g_chusb_hcd.current_pipe->data_pid);
- } else {
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- }
-
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return 0;
- }
-
- /**
- * Setup ---> in data ---> need generate next out status stage
- */
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_DATA) {
- USB_LOG_DBG("ep0 rx_len:%d\r\n", rx_len);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- if ((g_chusb_hcd.current_pipe->xfrd) > (urb->setup->wLength)) {
- /**
- * Error
- */
- USB_LOG_ERR("xfrd > setup->wLength\r\n");
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -3;
- }
-
- if (rx_len == 0 || (rx_len & (g_chusb_hcd.current_pipe->ep_mps - 1))) {
- /**
- * Receive a short package, in data has transfer completed
- */
- g_chusb_hcd.current_token = 0;
- g_chusb_hcd.ep0_state = USB_EP0_STATE_OUT_STATUS;
- /**
- * generate next out status stage
- */
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- } else {
- /**
- * Retry in
- */
- g_chusb_hcd.current_pipe->buffer += rx_len;
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- }
- } else {
- USB_LOG_DBG("ep%d rx_len:%d\r\n", (g_chusb_hcd.current_pipe->ep_addr & 0x0f), rx_len);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- if (rx_len == 0 || (rx_len & (g_chusb_hcd.current_pipe->ep_mps - 1)) || ((g_chusb_hcd.current_pipe->xfrd == g_chusb_hcd.current_pipe->urb->transfer_buffer_length))) {
- /**
- * Receive a short package, in data has transfer completed
- */
- g_chusb_hcd.current_token = 0;
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
-
- if (g_chusb_hcd.prv_get_zero == true) {
- g_chusb_hcd.prv_get_zero = false;
- }
-
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- /**
- * Initiate In again
- */
- g_chusb_hcd.current_pipe->buffer += rx_len;
-
- if (g_chusb_hcd.current_pipe->xferlen == 0) {
- if (g_chusb_hcd.prv_get_zero == true) {
- USB_LOG_ERR("g_chusb_hcd.prv_get_zero is always true\r\n");
- g_chusb_hcd.prv_get_zero = false;
- }
- g_chusb_hcd.prv_get_zero = true;
- }
-
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- }
- } else {
- /*!< Discard data out of synchronization */
- USB_LOG_ERR("EP%dData out of sync %d\r\n",
- (g_chusb_hcd.current_pipe->ep_addr & 0x0f), g_chusb_hcd.current_pipe->data_pid);
- urb->errorcode = -EIO;
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return -3;
- }
- break;
- default:
- break;
- }
-
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- return 0;
-}
-
-void USBH_IRQHandler(void)
-{
- INT_PRE_HANDLER();
- volatile uint8_t intflag = 0;
- volatile uint8_t res = 0;
- intflag = USBFS_HOST->INT_FG;
-
- if (intflag & USBFS_UIF_TRANSFER) {
- /*!< Check the equipment response status */
- res = (USBFS_HOST->INT_ST) & USBFS_UIS_ENDP_MASK;
- /*!< Stop this transmission after successful transmission */
- USBFS_HOST->HOST_EP_PID = 0x00;
- switch (g_chusb_hcd.current_token) {
- case USB_PID_SETUP:
- case USB_PID_OUT:
- if (chusb_outpipe_irq_handler(res) < 0) {
- goto pipe_wait;
- }
- break;
- case USB_PID_IN:
- if (chusb_inpipe_irq_handler(res) < 0) {
- goto pipe_wait;
- }
- break;
- default:
- USBFS_HOST->INT_FG = USBFS_UIF_TRANSFER;
- break;
- }
- } else if (intflag & USBFS_UIF_DETECT) {
- if (USBFS_HOST->MIS_ST & USBFS_UMS_DEV_ATTACH) {
- USB_LOG_INFO("Dev connect \r\n");
- g_chusb_hcd.port_csc = 1;
- g_chusb_hcd.port_pec = 1;
- g_chusb_hcd.port_pe = 1;
- usbh_roothub_thread_wakeup(1);
- } else {
- USB_LOG_INFO("Dev remove \r\n");
- /**
- * Device remove
- * Disable port and stop send sof
- */
- USBFS_HOST->HOST_SETUP &= ~USBFS_UH_SOF_EN;
- USBFS_HOST->HOST_CTRL &= ~USBFS_UH_PORT_EN;
-#if 0
- if (g_chusb_hcd.main_pipe_using) {
- g_chusb_hcd.main_pipe_using = false;
- }
-#endif
- g_chusb_hcd.port_csc = 1;
- g_chusb_hcd.port_pec = 1;
- g_chusb_hcd.port_pe = 0;
- for (uint8_t index = 0; index < CONFIG_USBHOST_PIPE_NUM; index++) {
- for (uint8_t j = 0; j < 2; j++) {
- struct chusb_pipe *pipe = &g_chusb_hcd.pipe_pool[index][j];
- struct usbh_urb *urb = pipe->urb;
- if (pipe->waiter) {
- pipe->waiter = false;
- urb->errorcode = -ESHUTDOWN;
- usb_osal_sem_give(pipe->waitsem);
- }
- }
- }
- usbh_roothub_thread_wakeup(1);
- }
- USBFS_HOST->INT_FG = USBFS_UIF_DETECT;
- } else {
- USB_LOG_INFO("Unkonwn \r\n");
- USBFS_HOST->INT_FG = intflag;
- }
- INT_POST_HANDLER();
- return;
-pipe_wait:
- /**
- * enerally, only errors can arrive here.
- * After testing, most cases arrive here because of the problem of the DATA PID,
- * but the transmission will be completed correctly next time.
- */
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- INT_POST_HANDLER();
-}
diff --git a/port/ch32/usb_hc_usbhs.c b/port/ch32/usb_hc_usbhs.c
deleted file mode 100644
index 07d031ef..00000000
--- a/port/ch32/usb_hc_usbhs.c
+++ /dev/null
@@ -1,1393 +0,0 @@
-#include "usbh_core.h"
-#include "usbh_hub.h"
-#include "usb_ch32_usbhs_reg.h"
-
-#ifndef USBH_IRQHandler
-#define USBH_IRQHandler USB2_IRQHandler
-#endif
-
-#ifndef CONFIG_USBHOST_PIPE_NUM
-#define CONFIG_USBHOST_PIPE_NUM 8
-#endif
-
-#ifndef USBHS_MAX_PACKET_SIZE
-#define USBHS_MAX_PACKET_SIZE 1024
-#endif
-
-#define HIGH_SP_HIGH_BAND_Pos 11
-#define HIGH_SP_HIGH_BAND_Mask (0x03 << HIGH_SP_HIGH_BAND_Pos)
-#define HIGH_SP_HIGH_BAND_1 (0x00 << HIGH_SP_HIGH_BAND_Pos)
-#define HIGH_SP_HIGH_BAND_2 (0x01 << HIGH_SP_HIGH_BAND_Pos)
-#define HIGH_SP_HIGH_BAND_3 (0x02 << HIGH_SP_HIGH_BAND_Pos)
-
-typedef enum {
- USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */
- USB_EP0_STATE_IN_DATA, /**< IN DATA */
- USB_EP0_STATE_IN_STATUS, /**< IN status */
- USB_EP0_STATE_OUT_DATA, /**< OUT DATA */
- USB_EP0_STATE_OUT_STATUS, /**< OUT status */
-} ep0_state_t;
-
-struct chusb_pipe {
- uint8_t dev_addr;
- uint8_t ep_addr;
- uint8_t ep_type;
- uint8_t ep_interval;
- uint8_t speed;
- uint16_t ep_mps;
- bool inuse;
- uint32_t xfrd;
- volatile bool waiter;
-
- uint32_t xferlen;
- uint8_t *buffer;
- uint8_t data_pid;
- uint8_t trans_num;
-
- usb_osal_sem_t waitsem;
- struct usbh_hubport *hport;
- struct usbh_urb *urb;
-};
-
-struct chusb_hcd {
- volatile bool port_csc;
- volatile bool port_pec;
- volatile bool port_pe;
- volatile uint8_t current_token;
- volatile uint8_t ep0_state;
- volatile bool prv_get_zero;
- volatile bool prv_set_zero;
- volatile bool main_pipe_using;
- // uint32_t current_pipe_timeout;
- uint8_t dev_speed;
- struct chusb_pipe *current_pipe;
- struct chusb_pipe pipe_pool[CONFIG_USBHOST_PIPE_NUM][2]; /* Support Bidirectional ep */
-} g_chusb_hcd;
-
-static inline void SET_UH_RX_CTRL_BIT(uint8_t bit)
-{
- if ((USBHS_HOST->HOST_RX_CTRL & USBHS_UH_R_TOG_AUTO) != 0) {
- /**
- * USBHS_UH_R_TOG canot write
- */
- if ((bit & (USBHS_UH_R_TOG_1 | USBHS_UH_R_TOG_2 | USBHS_UH_R_TOG_3)) != 0) {
- /**
- * bit contains USBHS_UH_R_TOG
- */
- USBHS_HOST->HOST_RX_CTRL &= ~(USBHS_UH_R_TOG_AUTO);
- USBHS_HOST->HOST_RX_CTRL |= (USBHS_UH_R_TOG_AUTO | bit);
- } else {
- USBHS_HOST->HOST_RX_CTRL |= bit;
- }
- } else {
- USBHS_HOST->HOST_RX_CTRL |= bit;
- }
-}
-
-static inline void SET_UH_TX_CTRL_BIT(uint8_t bit)
-{
- if ((USBHS_HOST->HOST_TX_CTRL & USBHS_UH_T_TOG_AUTO) != 0) {
- /**
- * USBFS_UH_T_TOG canot write
- */
- if ((bit & (USBHS_UH_T_TOG_1 | USBHS_UH_T_TOG_2 | USBHS_UH_T_TOG_3)) != 0) {
- /**
- * bit contains USBFS_UH_T_TOG
- */
- USBHS_HOST->HOST_TX_CTRL &= ~(USBHS_UH_T_TOG_AUTO);
- USBHS_HOST->HOST_TX_CTRL |= (USBHS_UH_T_TOG_AUTO | bit);
- } else {
- USBHS_HOST->HOST_TX_CTRL |= bit;
- }
- } else {
- USBHS_HOST->HOST_TX_CTRL |= bit;
- }
-}
-
-static inline void CLEAR_UH_TX_CTRL_BIT(uint8_t bit)
-{
- if ((USBHS_HOST->HOST_TX_CTRL & USBHS_UH_T_TOG_AUTO) != 0) {
- /**
- * USBFS_UH_T_TOG canot write
- */
- if ((bit & (USBHS_UH_T_TOG_1 | USBHS_UH_T_TOG_2 | USBHS_UH_T_TOG_3)) != 0) {
- /**
- * bit contains USBFS_UH_T_TOG
- */
- USBHS_HOST->HOST_TX_CTRL &= ~(USBHS_UH_T_TOG_AUTO);
- USBHS_HOST->HOST_TX_CTRL &= ~(bit);
- USBHS_HOST->HOST_TX_CTRL |= USBHS_UH_T_TOG_AUTO;
- } else {
- USBHS_HOST->HOST_TX_CTRL &= ~(bit);
- }
- } else {
- USBHS_HOST->HOST_TX_CTRL &= ~(bit);
- }
-}
-
-static inline void CLEAR_UH_RX_CTRL_BIT(uint8_t bit)
-{
- if ((USBHS_HOST->HOST_RX_CTRL & USBHS_UH_R_TOG_AUTO) != 0) {
- /**
- * USBFS_UH_R_TOG canot write
- */
- if ((bit & (USBHS_UH_R_TOG_1 | USBHS_UH_R_TOG_2 | USBHS_UH_R_TOG_3)) != 0) {
- /**
- * bit contains USBFS_UH_R_TOG
- */
- USBHS_HOST->HOST_RX_CTRL &= ~(USBHS_UH_R_TOG_AUTO);
- USBHS_HOST->HOST_RX_CTRL &= ~(bit);
- USBHS_HOST->HOST_RX_CTRL |= USBHS_UH_R_TOG_AUTO;
- } else {
- USBHS_HOST->HOST_RX_CTRL &= ~(bit);
- }
- } else {
- USBHS_HOST->HOST_RX_CTRL &= ~(bit);
- }
-}
-
-static inline void SET_UH_RX_CTRL(uint8_t value)
-{
- USBHS_HOST->HOST_RX_CTRL = 0;
- USBHS_HOST->HOST_RX_CTRL = value;
- USB_LOG_DBG("USBHS_HOST->HOST_RX_CTRL:%02x\r\n", USBHS_HOST->HOST_RX_CTRL);
-}
-
-static inline void SET_UH_TX_CTRL(uint8_t value)
-{
- USBHS_HOST->HOST_TX_CTRL = 0;
- USBHS_HOST->HOST_TX_CTRL = value;
- USB_LOG_DBG("USBHS_HOST->HOST_TX_CTRL:%02x\r\n", USBHS_HOST->HOST_TX_CTRL);
-}
-
-static inline void INT_PRE_HANDLER(void)
-{
-#if defined(CH581) || defined(CH582) || defined(CH583) || defined(CH571) || defined(CH572) || defined(CH573)
-#else
- asm("csrrw sp,mscratch,sp");
- extern void rt_interrupt_enter(void);
- rt_interrupt_enter();
-#endif
-}
-
-static inline void INT_POST_HANDLER(void)
-{
-#if defined(CH581) || defined(CH582) || defined(CH583) || defined(CH571) || defined(CH572) || defined(CH573)
-#else
- extern void rt_interrupt_leave(void);
- rt_interrupt_leave();
- asm("csrrw sp,mscratch,sp");
-#endif
-}
-
-static int8_t chusb_host_pipe_transfer(struct chusb_pipe *pipe, uint8_t pid, uint8_t *data, uint32_t len)
-{
- /*!< Updata current transfer pid */
- g_chusb_hcd.current_token = pid;
- /*!< Updata curretn pipe */
- g_chusb_hcd.current_pipe = pipe;
- /*!< Updata curretn pipe timeout */
- // g_chusb_hcd.current_pipe_timeout = pipe->urb->timeout;
- /*!< Updata main pipe using flag */
- // g_chusb_hcd.main_pipe_using = true;
-
- if (data == NULL && len > 0) {
- USB_LOG_ERR("Please give correct data and len parameters\r\n");
- return -1;
- }
-
- if (pid == USB_PID_SETUP) {
- /*!< Record the data len */
- g_chusb_hcd.current_pipe->xferlen = len;
-
- if ((uint32_t)data & 0x03) {
- USB_LOG_INFO("SETUP DMA address is not align \r\n");
- return -3;
- }
-
- USBHS_HOST->HOST_TX_DMA = (uint32_t)data;
-
- /*!< Record the data buffer address */
- pipe->buffer = data;
-
- if (len > pipe->ep_mps) {
- len = pipe->ep_mps;
- }
-
- USBHS_HOST->HOST_TX_LEN = len;
- USBHS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
-
- } else if (pid == USB_PID_OUT) {
- /*!< Record the data len */
- g_chusb_hcd.current_pipe->xferlen = len;
-
- if (len == 0) {
- USBHS_HOST->HOST_TX_LEN = len;
- USBHS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
- return 0;
- }
-
- if ((uint32_t)data & 0x03) {
- USB_LOG_WRN("OUT DMA address is not align \r\n");
- return -3;
- }
-
- USBHS_HOST->HOST_TX_DMA = (uint32_t)data;
-
- /*!< Record the data buffer address */
- pipe->buffer = data;
-
- if (len > pipe->ep_mps) {
- len = pipe->ep_mps;
- }
-
- USBHS_HOST->HOST_TX_LEN = len;
- USBHS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
-
- } else if (pid == USB_PID_IN) {
- /*!< Record the data len */
- g_chusb_hcd.current_pipe->xferlen = len;
-
- if (len == 0) {
- /*!< Want get 0 length data */
- } else {
- if ((uint32_t)data & 0x03) {
- USB_LOG_INFO("IN DMA address is not align \r\n");
- return -3;
- }
- USBHS_HOST->HOST_RX_DMA = (uint32_t)data;
- pipe->buffer = data;
- }
-
- USBHS_HOST->HOST_EP_PID = pid << 4 | (pipe->ep_addr & 0x0f);
- }
- return 0;
-}
-
-static void chusb_control_pipe_init(struct chusb_pipe *pipe, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen)
-{
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_SETUP) {
- /**
- * Setup is distributed as DATA0
- */
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO);
- pipe->data_pid = 0;
- chusb_host_pipe_transfer(pipe, USB_PID_SETUP, (uint8_t *)setup, 8);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_DATA) {
- if (pipe->data_pid != 1) {
- USB_LOG_ERR("IN_DATA PID Error\r\n");
- }
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO | USBHS_UH_R_TOG_1);
- chusb_host_pipe_transfer(pipe, USB_PID_IN, buffer, buflen);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_DATA) {
- if (pipe->data_pid != 1) {
- USB_LOG_ERR("OUT_DATA PID Error\r\n");
- }
- chusb_host_pipe_transfer(pipe, USB_PID_OUT, buffer, buflen);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_STATUS) {
- /**
- * Status stage must be DATA1
- */
- // SET_UH_RX_CTRL_BIT(USBFS_UH_R_TOG);
- pipe->data_pid = 1;
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO | USBHS_UH_R_TOG_1);
- chusb_host_pipe_transfer(pipe, USB_PID_IN, NULL, 0);
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_STATUS) {
- /**
- * Status stage must be DATA1
- */
- // SET_UH_TX_CTRL_BIT(USBFS_UH_T_TOG);
- pipe->data_pid = 1;
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO | USBHS_UH_T_TOG_1);
- chusb_host_pipe_transfer(pipe, USB_PID_OUT, NULL, 0);
- }
-}
-
-static void chusb_bulk_pipe_init(struct chusb_pipe *pipe, uint8_t *buffer, uint32_t buflen)
-{
- if (pipe->ep_type != USB_ENDPOINT_TYPE_BULK) {
- USB_LOG_ERR("Endpoint type is not BULK\r\n");
- return;
- }
-
- if (pipe->ep_addr & 0x80) {
- /*!< IN */
- g_chusb_hcd.current_token = USB_PID_IN;
- if (pipe->data_pid == 1) {
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO | USBHS_UH_R_TOG_1);
- } else {
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO);
- }
- } else {
- /*!< OUT */
- g_chusb_hcd.current_token = USB_PID_OUT;
- if (pipe->data_pid == 1) {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO | USBHS_UH_T_TOG_1);
- } else {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO);
- }
- }
-
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
-}
-
-static void chusb_intr_pipe_init(struct chusb_pipe *pipe, uint8_t *buffer, uint32_t buflen)
-{
- if (pipe->ep_type != USB_ENDPOINT_TYPE_INTERRUPT) {
- USB_LOG_ERR("Endpoint type is not INTERRUPT\r\n");
- return;
- }
-
- if (pipe->ep_addr & 0x80) {
- /*!< IN */
- g_chusb_hcd.current_token = USB_PID_IN;
-
- if (pipe->trans_num > 1) {
- USB_LOG_WRN("Not supported temporarily\r\n");
- if (pipe->trans_num == 2) {
- } else if (pipe->trans_num == 3) {
- }
- } else {
- if (pipe->data_pid == 1) {
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO | USBHS_UH_R_TOG_1);
- } else {
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO);
- }
- }
- } else {
- /*!< OUT */
- g_chusb_hcd.current_token = USB_PID_OUT;
- if (pipe->trans_num > 1) {
- USB_LOG_WRN("Not supported temporarily\r\n");
- if (pipe->trans_num == 2) {
- } else if (pipe->trans_num == 3) {
- }
- } else {
- if (pipe->data_pid == 1) {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO | USBHS_UH_T_TOG_1);
- } else {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO);
- }
- }
- }
-
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
-}
-
-static void chusb_iso_pipe_init(struct chusb_pipe *pipe, uint8_t *buffer, uint32_t buflen)
-{
- if (pipe->ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
- USB_LOG_ERR("Endpoint type is not ISOCHRONOUS\r\n");
- return;
- }
-
- if (pipe->ep_addr & 0x80) {
- /*!< IN */
- g_chusb_hcd.current_token = USB_PID_IN;
- if (pipe->trans_num > 1) {
- /**
- * High speed and high bandwidth isochronous endpoint
- */
- USB_LOG_WRN("Not supported temporarily\r\n");
-#if 0
- if (pipe->trans_num == 2) {
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO | USBHS_UH_R_TOG_1 | USBHS_UH_R_RES_NO);
- } else if (pipe->trans_num == 3) {
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO | USBHS_UH_R_TOG_2 | USBHS_UH_R_RES_NO);
- }
-#endif
- } else {
- SET_UH_RX_CTRL(USBHS_UH_R_TOG_AUTO | USBHS_UH_R_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
- return;
- }
- } else {
- /*!< OUT */
- g_chusb_hcd.current_token = USB_PID_OUT;
- if (pipe->trans_num > 1) {
- /**
- * High speed and high bandwidth isochronous endpoint
- */
- USB_LOG_WRN("Not supported temporarily\r\n");
-#if 0
- if (pipe->trans_num == 2) {
- if (buflen < pipe->ep_mps) {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO | USBHS_UH_T_RES_NO);
- } else {
- uint32_t send_len = buflen;
- while (send_len > pipe->ep_mps) {
- /**
- * First send a MDATA
- */
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_3 | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, send_len);
- send_len -= pipe->ep_mps;
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_1 | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, (buffer + pipe->ep_mps), send_len);
- if (send_len > pipe->ep_mps) {
- send_len -= pipe->ep_mps;
- }
- }
- }
- return;
- } else if (pipe->trans_num == 3) {
- if (buflen < pipe->ep_mps) {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO | USBHS_UH_T_RES_NO);
- } else if (buflen < (2 * pipe->ep_mps)) {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_3 | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_1 | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, (buffer + pipe->ep_mps), (buflen - pipe->ep_mps));
- return;
- } else {
- uint32_t send_len = buflen;
- while (send_len > pipe->ep_mps) {
- /**
- * First send a MDATA
- */
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_3 | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, send_len);
- send_len -= pipe->ep_mps;
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_3 | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, (buffer + pipe->ep_mps), send_len);
- send_len -= pipe->ep_mps;
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_2 | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, (buffer + pipe->ep_mps), send_len);
- if (send_len > pipe->ep_mps) {
- send_len -= pipe->ep_mps;
- }
- }
- }
- }
-#endif
- } else {
- SET_UH_TX_CTRL(USBHS_UH_T_TOG_AUTO | USBHS_UH_T_RES_NO);
- chusb_host_pipe_transfer(pipe, g_chusb_hcd.current_token, buffer, buflen);
- return;
- }
- }
-}
-
-static void chusbh_set_self_speed(uint8_t speed)
-{
- if (speed == USB_SPEED_HIGH) {
- USBHS_HOST->CONTROL = (USBHS_HOST->CONTROL & ~USBHS_SPEED_MASK) | USBHS_HIGH_SPEED;
- } else if (speed == USB_SPEED_FULL) {
- USBHS_HOST->CONTROL = (USBHS_HOST->CONTROL & ~USBHS_SPEED_MASK) | USBHS_FULL_SPEED;
- } else {
- USBHS_HOST->CONTROL = (USBHS_HOST->CONTROL & ~USBHS_SPEED_MASK) | USBHS_LOW_SPEED;
- }
-}
-
-static int usbh_reset_port(const uint8_t port)
-{
- USB_LOG_INFO("Reset port \r\n");
- /*!< Clear flags that may not have been cleared */
- // g_chusb_hcd.main_pipe_using = false;
-
- g_chusb_hcd.port_pe = 0;
- /*!< Set dev add 0 */
- USBHS_HOST->DEV_AD = (0x00 & 0x7F);
- chusbh_set_self_speed(USB_SPEED_HIGH);
-
- /*!< Start reset */
- USBHS_HOST->HOST_CTRL |= USBHS_SEND_BUS_RESET;
- usb_osal_msleep(11);
- /*!< Stop reset */
- USBHS_HOST->HOST_CTRL &= ~USBHS_SEND_BUS_RESET;
- usb_osal_msleep(2);
- g_chusb_hcd.port_pe = 1;
-
- if (USBHS_HOST->MIS_ST & USBHS_ATTACH) {
- volatile uint8_t speed = USBHS_HOST->SPEED_TYPE & USBSPEED_MASK;
- if (speed == 0x02) {
- USB_LOG_INFO("Dev USB_SPEED_LOW \r\n");
- g_chusb_hcd.dev_speed = USB_SPEED_LOW;
- chusbh_set_self_speed(USB_SPEED_LOW);
- } else if (speed == 0x00) {
- USB_LOG_INFO("Dev USB_SPEED_FULL \r\n");
- g_chusb_hcd.dev_speed = USB_SPEED_FULL;
- chusbh_set_self_speed(USB_SPEED_FULL);
- } else if (speed == 0x01) {
- USB_LOG_INFO("Dev USB_SPEED_HIGH \r\n");
- g_chusb_hcd.dev_speed = USB_SPEED_HIGH;
- chusbh_set_self_speed(USB_SPEED_HIGH);
- }
- }
-
- USBHS_HOST->INT_EN |= USBHS_DETECT_EN;
- return 0;
-}
-
-static uint8_t usbh_get_port_speed(const uint8_t port)
-{
- (void)port;
- return g_chusb_hcd.dev_speed;
-}
-
-__WEAK void usb_hc_low_level_init(void)
-{
-}
-
-int usb_hc_init(void)
-{
- memset(&g_chusb_hcd, 0, sizeof(struct chusb_hcd));
-
- for (uint8_t i = 0; i < CONFIG_USBHOST_PIPE_NUM; i++) {
- g_chusb_hcd.pipe_pool[i][0].waitsem = usb_osal_sem_create(0);
- g_chusb_hcd.pipe_pool[i][1].waitsem = usb_osal_sem_create(0);
- }
-
- usb_hc_low_level_init();
-
- /* Reset USB module */
- USBHS_HOST->CONTROL = USBHS_ALL_CLR | USBHS_FORCE_RST;
- static volatile uint32_t wait_ct = 50000;
- while (wait_ct--) {
- }
- USBHS_HOST->CONTROL = 0;
-
- /* Initialize USB host configuration */
- USBHS_HOST->CONTROL = USBHS_HOST_MODE | USBHS_HIGH_SPEED | USBHS_INT_BUSY_EN | USBHS_DMA_EN;
- USBHS_HOST->HOST_EP_CONFIG = USBHS_HOST_TX_EN | USBHS_HOST_RX_EN;
- USBHS_HOST->HOST_CTRL = USBHS_PHY_SUSPENDM;
- USBHS_HOST->HOST_RX_MAX_LEN = USBHS_MAX_PACKET_SIZE;
-
- USBHS_HOST->HOST_RX_CTRL = 0;
- USBHS_HOST->HOST_TX_CTRL = 0;
- USBHS_HOST->INT_FG = 0xFF;
- USBHS_HOST->INT_EN = USBHS_TRANSFER_EN | USBHS_DETECT_EN;
- return 0;
-}
-
-int usbh_roothub_control(struct usb_setup_packet *setup, uint8_t *buf)
-{
- uint8_t nports;
- uint8_t port;
- uint32_t status;
-
- nports = CONFIG_USBHOST_MAX_RHPORTS;
- port = setup->wIndex;
- if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) {
- switch (setup->bRequest) {
- case HUB_REQUEST_CLEAR_FEATURE:
- switch (setup->wValue) {
- case HUB_FEATURE_HUB_C_LOCALPOWER:
- break;
- case HUB_FEATURE_HUB_C_OVERCURRENT:
- break;
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_SET_FEATURE:
- switch (setup->wValue) {
- case HUB_FEATURE_HUB_C_LOCALPOWER:
- break;
- case HUB_FEATURE_HUB_C_OVERCURRENT:
- break;
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_GET_DESCRIPTOR:
- break;
- case HUB_REQUEST_GET_STATUS:
- memset(buf, 0, 4);
- break;
- default:
- break;
- }
- } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) {
- switch (setup->bRequest) {
- case HUB_REQUEST_CLEAR_FEATURE:
- if (!port || port > nports) {
- return -EPIPE;
- }
-
- switch (setup->wValue) {
- case HUB_PORT_FEATURE_ENABLE:
- break;
- case HUB_PORT_FEATURE_SUSPEND:
- case HUB_PORT_FEATURE_C_SUSPEND:
- break;
- case HUB_PORT_FEATURE_POWER:
- break;
- case HUB_PORT_FEATURE_C_CONNECTION:
- g_chusb_hcd.port_csc = 0;
- break;
- case HUB_PORT_FEATURE_C_ENABLE:
- g_chusb_hcd.port_pec = 0;
- break;
- case HUB_PORT_FEATURE_C_OVER_CURREN:
- break;
- case HUB_PORT_FEATURE_C_RESET:
- break;
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_SET_FEATURE:
- if (!port || port > nports) {
- return -EPIPE;
- }
-
- switch (setup->wValue) {
- case HUB_PORT_FEATURE_SUSPEND:
- break;
- case HUB_PORT_FEATURE_POWER:
- break;
- case HUB_PORT_FEATURE_RESET:
- usbh_reset_port(port);
- break;
-
- default:
- return -EPIPE;
- }
- break;
- case HUB_REQUEST_GET_STATUS:
- if (!port || port > nports) {
- return -EPIPE;
- }
-
- status = 0;
- if (g_chusb_hcd.port_csc) {
- status |= (1 << HUB_PORT_FEATURE_C_CONNECTION);
- }
- if (g_chusb_hcd.port_pec) {
- status |= (1 << HUB_PORT_FEATURE_C_ENABLE);
- }
-
- if (g_chusb_hcd.port_pe) {
- status |= (1 << HUB_PORT_FEATURE_CONNECTION);
- status |= (1 << HUB_PORT_FEATURE_ENABLE);
- if (usbh_get_port_speed(port) == USB_SPEED_LOW) {
- status |= (1 << HUB_PORT_FEATURE_LOWSPEED);
- } else if (usbh_get_port_speed(port) == USB_SPEED_HIGH) {
- status |= (1 << HUB_PORT_FEATURE_HIGHSPEED);
- }
- }
-
- memcpy(buf, &status, 4);
- break;
- default:
- break;
- }
- }
- return 0;
-}
-
-int usbh_ep_pipe_reconfigure(usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t speed)
-{
- struct chusb_pipe *ppipe = (struct chusb_pipe *)pipe;
-
- ppipe->dev_addr = dev_addr;
- ppipe->ep_mps = ep_mps;
-
- USBHS_HOST->DEV_AD = dev_addr & 0x7f;
- return 0;
-}
-
-int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg)
-{
- struct chusb_pipe *ppipe;
- uint8_t ep_idx;
- usb_osal_sem_t waitsem;
-
- ep_idx = ep_cfg->ep_addr & 0x7f;
-
- if (ep_idx > CONFIG_USBHOST_PIPE_NUM) {
- return -ENOMEM;
- }
-
- if (ep_cfg->ep_addr & 0x80) {
- ppipe = &g_chusb_hcd.pipe_pool[ep_idx][1];
- } else {
- ppipe = &g_chusb_hcd.pipe_pool[ep_idx][0];
- }
-
- /* store variables */
- waitsem = ppipe->waitsem;
-
- memset(ppipe, 0, sizeof(struct chusb_pipe));
-
- ppipe->ep_addr = ep_cfg->ep_addr;
- ppipe->ep_type = ep_cfg->ep_type;
- ppipe->ep_mps = ep_cfg->ep_mps;
- ppipe->ep_interval = ep_cfg->ep_interval;
- ppipe->speed = ep_cfg->hport->speed;
- ppipe->dev_addr = ep_cfg->hport->dev_addr;
- ppipe->hport = ep_cfg->hport;
-
- if (ep_cfg->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- } else {
- if (ppipe->speed == USB_SPEED_HIGH) {
- if ((ep_cfg->ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) ||
- (ep_cfg->ep_type == USB_ENDPOINT_TYPE_INTERRUPT)) {
- if ((ppipe->ep_mps & HIGH_SP_HIGH_BAND_Mask) != 0) {
- /**
- * High speed and high bandwidth isochronous endpoint
- */
- if ((ppipe->ep_mps & HIGH_SP_HIGH_BAND_Mask) == HIGH_SP_HIGH_BAND_2) {
- ppipe->trans_num = 2;
- } else if ((ppipe->ep_mps & HIGH_SP_HIGH_BAND_Mask) == HIGH_SP_HIGH_BAND_3) {
- ppipe->trans_num = 3;
- }
- } else {
- ppipe->trans_num = 1;
- }
- }
- } else if (ppipe->speed == USB_SPEED_FULL) {
- } else if (ppipe->speed == USB_SPEED_LOW) {
- }
- }
- /* restore variable */
- ppipe->inuse = true;
- ppipe->waitsem = waitsem;
-
- *pipe = (usbh_pipe_t)ppipe;
- return 0;
-}
-
-int usbh_pipe_free(usbh_pipe_t pipe)
-{
- return 0;
-}
-
-static inline void chusb_pipe_waitup(struct chusb_pipe *pipe, bool callback)
-{
- struct usbh_urb *urb;
-
- urb = pipe->urb;
- pipe->urb = NULL;
- // g_chusb_hcd.main_pipe_using = false;
-
- if (pipe->waiter) {
- pipe->waiter = false;
- usb_osal_sem_give(pipe->waitsem);
- }
-
- if (callback == true) {
- if (urb->complete) {
- if (urb->errorcode < 0) {
- urb->complete(urb->arg, urb->errorcode);
- } else {
- urb->complete(urb->arg, urb->actual_length);
- }
- }
- }
-}
-
-int usbh_submit_urb(struct usbh_urb *urb)
-{
- struct chusb_pipe *pipe;
- size_t flags;
- int ret = 0;
-
- if (!urb) {
- USB_LOG_INFO("urb is null \r\n");
- return -EINVAL;
- }
-
- pipe = urb->pipe;
-
- if (!pipe) {
- USB_LOG_INFO("pipe is null \r\n");
- return -EINVAL;
- }
-
- if (!pipe->hport->connected) {
- USB_LOG_INFO("!pipe->hport->connected \r\n");
- return -ENODEV;
- }
-
- if (pipe->urb) {
- USB_LOG_INFO("pipe->urb is not null\r\n");
- return -EBUSY;
- }
-
-#if 0
- if (g_chusb_hcd.main_pipe_using == true) {
- USB_LOG_INFO("usbh_submit_urb//main pipe is using\r\n");
- return -EBUSY;
- }
-#endif
-
- flags = usb_osal_enter_critical_section();
-
- pipe->waiter = false;
- pipe->xfrd = 0;
- pipe->urb = urb;
- urb->errorcode = -EBUSY;
- urb->actual_length = 0;
-
- if (urb->timeout > 0) {
- pipe->waiter = true;
- }
- usb_osal_leave_critical_section(flags);
-
- switch (pipe->ep_type) {
- case USB_ENDPOINT_TYPE_CONTROL:
- g_chusb_hcd.ep0_state = USB_EP0_STATE_SETUP;
- chusb_control_pipe_init(pipe, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- case USB_ENDPOINT_TYPE_BULK:
- chusb_bulk_pipe_init(pipe, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- case USB_ENDPOINT_TYPE_INTERRUPT:
- chusb_intr_pipe_init(pipe, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- case USB_ENDPOINT_TYPE_ISOCHRONOUS:
- chusb_iso_pipe_init(pipe, urb->transfer_buffer, urb->transfer_buffer_length);
- break;
- default:
- break;
- }
- if (urb->timeout > 0) {
- /* wait until timeout or sem give */
- ret = usb_osal_sem_take(pipe->waitsem, urb->timeout);
- if (ret < 0) {
- goto errout_timeout;
- }
-
- ret = urb->errorcode;
- }
- return ret;
-errout_timeout:
- pipe->waiter = false;
- g_chusb_hcd.current_token = 0;
- // g_chusb_hcd.main_pipe_using = false;
- chusb_pipe_waitup(pipe, false);
- usbh_kill_urb(urb);
- return ret;
-}
-
-int usbh_kill_urb(struct usbh_urb *urb)
-{
- return 0;
-}
-
-static int8_t chusb_outpipe_irq_handler(uint8_t res_state)
-{
- uint16_t current_tx_length = USBHS_HOST->HOST_TX_LEN;
- struct usbh_urb *urb;
- urb = (g_chusb_hcd.current_pipe->urb);
-
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_CONTROL) {
- if ((g_chusb_hcd.current_pipe->ep_addr & 0x80) != 0) {
- /* Error */
- USB_LOG_ERR("ep_addr is not out add \r\n");
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -1;
- }
- }
-
- switch (res_state) {
- case USB_PID_STALL:
- urb->errorcode = -EPERM;
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- USB_LOG_ERR("USB_PID_SETUP STALL \r\n");
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -2;
- } else {
- if (g_chusb_hcd.current_pipe->waiter == true) {
- USB_LOG_WRN("USB_PID_OUT STALL \r\n");
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- USB_LOG_ERR("USB_PID_OUT STALL \r\n");
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -2;
- }
- }
- case USB_PID_NAK:
- urb->errorcode = -EAGAIN;
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- /**
- * Device must ack for setup package
- */
- USB_LOG_ERR("Setup NAK \r\n");
- g_chusb_hcd.current_token = 0;
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -3;
- } else {
- if (g_chusb_hcd.current_pipe->waiter == true) {
- USB_LOG_DBG("Control endpoint out nak and retry, length:%d\r\n",g_chusb_hcd.current_pipe->xferlen);
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- }
- } else {
- urb->errorcode = 0;
- if (g_chusb_hcd.prv_set_zero == true) {
- /**
- * It is unlikely to run here,
- * because the device can probably receive 0 length byte packets
- */
- g_chusb_hcd.prv_set_zero = false;
- g_chusb_hcd.current_token = 0;
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- if (g_chusb_hcd.current_pipe->waiter == true) {
- USB_LOG_DBG("Normal endpoint out nak and retry\r\n");
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- g_chusb_hcd.current_token = 0;
- if (g_chusb_hcd.current_pipe->xfrd > 0) {
- /**
- * The device received data but did not receive it completely
- */
- urb->errorcode = 0;
- USB_LOG_WRN("The data is not sent completely, but the timeout is 0\r\n");
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- /**
- * The device may not be ready, make sure your device can receive data
- */
- USB_LOG_WRN("The device may not be ready, make sure your device can receive data\r\n");
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, false);
- }
- }
- }
- }
- break;
- case USB_PID_ACK:
- case USB_PID_NYET:
- /**
- * The last out or setup package was sent
- */
- urb->errorcode = 0;
-
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- /*!< Ctrol endpoint */
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- /*!< Setup package send successfully */
- urb->actual_length += 8;
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_SETUP) {
- if (urb->setup->wLength) {
- if (urb->setup->bmRequestType & 0x80) {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_IN_DATA;
- } else {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_OUT_DATA;
- }
- } else {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_IN_STATUS;
- }
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- }
- } else if (g_chusb_hcd.current_token == USB_PID_OUT) {
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_DATA) {
- USB_LOG_DBG("ep0 tx_len:%d\r\n", current_tx_length);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- g_chusb_hcd.current_pipe->xfrd += current_tx_length;
- g_chusb_hcd.current_pipe->buffer += current_tx_length;
- g_chusb_hcd.current_pipe->xferlen -= current_tx_length;
- if (g_chusb_hcd.current_pipe->xferlen == 0) {
- if (current_tx_length == g_chusb_hcd.current_pipe->ep_mps) {
- /**
- * Need send 0 length data
- */
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT, NULL, 0);
- } else {
- /*!< Out package send successfully */
- g_chusb_hcd.ep0_state = USB_EP0_STATE_IN_STATUS;
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- }
- } else {
- /*!< Start send next out package */
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- } else if (g_chusb_hcd.ep0_state == USB_EP0_STATE_OUT_STATUS) {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_SETUP;
- urb->actual_length += g_chusb_hcd.current_pipe->xfrd;
- USB_LOG_DBG("S-> I-> O-status stage: In:%d\r\n", urb->actual_length - 8);
- if (g_chusb_hcd.current_pipe->data_pid != 1) {
- USB_LOG_ERR("S-> I-> O-status stage DATA PID Error\r\n");
- } else {
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- }
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- }
- } else {
- if (g_chusb_hcd.current_token == USB_PID_OUT) {
- USB_LOG_DBG("ep%d tx_len:%d\r\n", (g_chusb_hcd.current_pipe->ep_addr & 0x0f), current_tx_length);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- g_chusb_hcd.current_pipe->xfrd += current_tx_length;
- g_chusb_hcd.current_pipe->buffer += current_tx_length;
- g_chusb_hcd.current_pipe->xferlen -= current_tx_length;
- if (g_chusb_hcd.current_pipe->xferlen == 0) {
- if (current_tx_length == g_chusb_hcd.current_pipe->ep_mps) {
- /**
- * Need send 0 length data
- */
- if (g_chusb_hcd.prv_set_zero == true) {
- USB_LOG_ERR("g_chusb_hcd.prv_set_zero is always true\r\n");
- }
- g_chusb_hcd.prv_set_zero = true;
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT, NULL, 0);
- } else {
- /*!< Out package send successfully */
- g_chusb_hcd.current_token = 0;
- if (g_chusb_hcd.prv_set_zero == true) {
- g_chusb_hcd.prv_set_zero = false;
- }
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- } else {
- /*!< Start send next out package */
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_OUT,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- } else {
- USB_LOG_ERR("Error token is not match \r\n");
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -4;
- }
- }
- break;
- case 0:
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
- if (g_chusb_hcd.current_token == USB_PID_SETUP) {
- if ((g_chusb_hcd.ep0_state == USB_EP0_STATE_SETUP) && (g_chusb_hcd.current_pipe->waiter == true)) {
- USB_LOG_WRN("Setup Timeout and retry\r\n");
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- } else {
- USB_LOG_ERR("Setup Timeout\r\n");
- urb->errorcode = -EIO;
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -5;
- }
- } else {
- USB_LOG_ERR("Out Timeout \r\n");
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_CONTROL) {
- /**
- * Reset data pid
- */
- g_chusb_hcd.current_pipe->data_pid = 0;
- }
- }
- urb->errorcode = -EIO;
- } else {
- /**
- * No response from isochronous endpoint out
- */
- urb->errorcode = 0;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- default:
- break;
- }
-
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return 0;
-}
-
-static int8_t chusb_inpipe_irq_handler(uint8_t res_state)
-{
- uint16_t rx_len = 0;
- struct usbh_urb *urb;
- urb = (g_chusb_hcd.current_pipe->urb);
-
- if (g_chusb_hcd.current_pipe->ep_type != USB_ENDPOINT_TYPE_CONTROL) {
- if ((g_chusb_hcd.current_pipe->ep_addr & 0x80) == 0) {
- /* Error */
- USB_LOG_ERR("ep_addr is not in add\r\n");
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -1;
- }
- }
-
- switch (res_state) {
- case USB_PID_STALL:
- USB_LOG_ERR("USB_PID_IN USB_PID_STALL\r\n");
- g_chusb_hcd.current_token = 0;
- urb->errorcode = -EPERM;
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -2;
- case USB_PID_NAK:
- urb->errorcode = -EAGAIN;
- g_chusb_hcd.current_token = 0;
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- if (g_chusb_hcd.current_pipe->waiter == true) {
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- } else {
- urb->errorcode = 0;
- if (g_chusb_hcd.prv_get_zero == true) {
- g_chusb_hcd.prv_get_zero = false;
- g_chusb_hcd.current_token = 0;
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- USB_LOG_DBG("Normal endpoint get zero length package\r\n");
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- USB_LOG_DBG("Normal endpoint in nak\r\n");
- if (g_chusb_hcd.current_pipe->xferlen > 0) {
- /**
- * The data has not been transmitted completely
- */
- if (g_chusb_hcd.current_pipe->xfrd > 0) {
- /**
- * Data was transmitted last time, but this time NAK
- */
- if (g_chusb_hcd.current_pipe->waiter == true) {
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- /**
- * Some data has been transferred
- */
- USB_LOG_WRN("The device has not finished sending all data, but the timeout is 0\r\n");
- g_chusb_hcd.current_token = 0;
- /**
- * Update the actual send length
- */
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
- urb->errorcode = 0;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- }
- } else {
- /**
- * The device did not send any data.
- */
- if (g_chusb_hcd.current_pipe->waiter == true) {
- /**
- * Try again
- */
- USB_LOG_DBG("The device does not transmit data, try again\r\n");
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- } else {
- /**
- * g_chusb_hcd.current_pipe->waiter = false
- * We do not need to call a callback
- */
- USB_LOG_DBG("Do not need try again\r\n");
- urb->errorcode = -EBUSY;
- g_chusb_hcd.current_token = 0;
- urb->actual_length = 0;
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, false);
- }
- }
- } else {
- USB_LOG_ERR("xferlen == 0//should get zero package\r\n");
- }
- }
- }
- break;
- case USB_PID_ACK:
- urb->errorcode = 0;
- break;
- case USB_PID_DATA0:
- case USB_PID_DATA1:
- case USB_PID_DATA2:
- case USB_PID_MDATA:
- if ((USBHS_HOST->INT_ST) & USBHS_DEV_UIS_TOG_OK) {
- /*!< Data is OK */
- rx_len = USBHS_HOST->RX_LEN;
-
- urb->errorcode = 0;
-
- g_chusb_hcd.current_pipe->xfrd += rx_len;
-
- if (g_chusb_hcd.current_pipe->xferlen < rx_len) {
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- USB_LOG_ERR("Please provide the correct data length parameter xferlen:%d rxlen:%d\r\n",g_chusb_hcd.current_pipe->xferlen, rx_len);
- if (g_chusb_hcd.prv_get_zero == true) {
- g_chusb_hcd.prv_get_zero = false;
- }
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -6;
- }
-
- g_chusb_hcd.current_pipe->xferlen -= rx_len;
-
- if (g_chusb_hcd.current_pipe->ep_type == USB_ENDPOINT_TYPE_CONTROL) {
- /*!< Ctrol endpoint */
- /**
- * Status stage
- *
- * Setup ---> out data ---> in status stage
- */
- if ((g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_STATUS) && (rx_len == 0)) {
- g_chusb_hcd.ep0_state = USB_EP0_STATE_SETUP;
- urb->actual_length += rx_len;
- USB_LOG_DBG("S-> O-> In-status stage: Out:%d\r\n", urb->actual_length - 8);
-
- if (g_chusb_hcd.current_pipe->data_pid != 1) {
- USB_LOG_ERR("S-> O-> In-status stage DATA PID Error//PID:%d\r\n", g_chusb_hcd.current_pipe->data_pid);
- } else {
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- }
-
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return 0;
- }
-
- /**
- * Setup ---> in data ---> need generate next out status stage
- */
- if (g_chusb_hcd.ep0_state == USB_EP0_STATE_IN_DATA) {
- USB_LOG_DBG("ep0 rx_len:%d\r\n", rx_len);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- if ((g_chusb_hcd.current_pipe->xfrd) > (urb->setup->wLength)) {
- /**
- * Error
- */
- USB_LOG_ERR("xfrd > setup->wLength\r\n");
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -3;
- }
-
- if (rx_len == 0 || (rx_len & (g_chusb_hcd.current_pipe->ep_mps - 1))) {
- /**
- * Receive a short package, in data has transfer completed
- */
- g_chusb_hcd.current_token = 0;
- g_chusb_hcd.ep0_state = USB_EP0_STATE_OUT_STATUS;
- /**
- * generate next out status stage
- */
- chusb_control_pipe_init(g_chusb_hcd.current_pipe, urb->setup,
- urb->transfer_buffer, urb->transfer_buffer_length);
- } else {
- /**
- * Retry in
- */
- g_chusb_hcd.current_pipe->buffer += rx_len;
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- }
- } else {
- USB_LOG_DBG("ep%d rx_len:%d\r\n", (g_chusb_hcd.current_pipe->ep_addr & 0x0f), rx_len);
- g_chusb_hcd.current_pipe->data_pid ^= 1;
- if (rx_len == 0 || (rx_len & (g_chusb_hcd.current_pipe->ep_mps - 1)) || (g_chusb_hcd.current_pipe->xfrd == g_chusb_hcd.current_pipe->urb->transfer_buffer_length)) {
- /**
- * Receive a short package, in data has transfer completed
- */
- g_chusb_hcd.current_token = 0;
- urb->actual_length = g_chusb_hcd.current_pipe->xfrd;
-
- if (g_chusb_hcd.prv_get_zero == true) {
- g_chusb_hcd.prv_get_zero = false;
- }
-
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, true);
- } else {
- /**
- * Initiate In again
- */
- g_chusb_hcd.current_pipe->buffer += rx_len;
-
- if (g_chusb_hcd.current_pipe->xferlen == 0) {
- if (g_chusb_hcd.prv_get_zero == true) {
- USB_LOG_ERR("g_chusb_hcd.prv_get_zero is always true\r\n");
- g_chusb_hcd.prv_get_zero = false;
- }
- g_chusb_hcd.prv_get_zero = true;
- }
-
- chusb_host_pipe_transfer(g_chusb_hcd.current_pipe, USB_PID_IN,
- g_chusb_hcd.current_pipe->buffer, g_chusb_hcd.current_pipe->xferlen);
- }
- }
- } else {
- /*!< Discard data out of synchronization */
- USB_LOG_ERR("EP%dData out of sync %d\r\n",
- (g_chusb_hcd.current_pipe->ep_addr & 0x0f), g_chusb_hcd.current_pipe->data_pid);
- urb->errorcode = -EIO;
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return -3;
- }
- break;
- default:
- break;
- }
-
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- return 0;
-}
-
-__attribute__((interrupt("WCH-Interrupt-fast"))) void USBH_IRQHandler(void)
-{
- INT_PRE_HANDLER();
- volatile uint8_t intflag = 0;
- volatile uint8_t res = 0;
- intflag = USBHS_HOST->INT_FG;
-
- if (intflag & USBHS_TRANSFER_FLAG) {
- /*!< Check the equipment response status */
- res = (USBHS_HOST->INT_ST) & MASK_UIS_H_RES;
- USBHS_HOST->HOST_EP_PID = 0x00;
- switch (g_chusb_hcd.current_token) {
- case USB_PID_SETUP:
- case USB_PID_OUT:
- if (chusb_outpipe_irq_handler(res) < 0) {
- goto pipe_wait;
- }
- break;
- case USB_PID_IN:
- if (chusb_inpipe_irq_handler(res) < 0) {
- goto pipe_wait;
- }
- break;
- default:
- USBHS_HOST->INT_FG = USBHS_TRANSFER_FLAG;
- break;
- }
- } else if (intflag & USBHS_DETECT_FLAG) {
- if (USBHS_HOST->MIS_ST & USBHS_ATTACH) {
- USB_LOG_INFO("Dev connect \r\n");
- g_chusb_hcd.port_csc = 1;
- g_chusb_hcd.port_pec = 1;
- g_chusb_hcd.port_pe = 1;
- USBHS_HOST->HOST_CTRL |= USBHS_SEND_SOF_EN;
- usbh_roothub_thread_wakeup(1);
- } else {
- USB_LOG_INFO("Dev remove \r\n");
- USBHS_HOST->HOST_EP_PID = 0x00;
-#if 0
- if (g_chusb_hcd.main_pipe_using) {
- g_chusb_hcd.main_pipe_using = false;
- }
-#endif
- g_chusb_hcd.port_csc = 1;
- g_chusb_hcd.port_pec = 1;
- g_chusb_hcd.port_pe = 0;
- for (uint8_t index = 0; index < CONFIG_USBHOST_PIPE_NUM; index++) {
- for (uint8_t j = 0; j < 2; j++) {
- struct chusb_pipe *pipe = &g_chusb_hcd.pipe_pool[index][j];
- struct usbh_urb *urb = pipe->urb;
- if (pipe->waiter) {
- pipe->waiter = false;
- urb->errorcode = -ESHUTDOWN;
- usb_osal_sem_give(pipe->waitsem);
- }
- }
- }
- usbh_roothub_thread_wakeup(1);
- }
- USBHS_HOST->INT_FG = USBHS_DETECT_FLAG;
- } else {
- USB_LOG_INFO("Unkonwn \r\n");
- USBHS_HOST->INT_FG = intflag;
- }
- INT_POST_HANDLER();
- return;
-pipe_wait:
- chusb_pipe_waitup(g_chusb_hcd.current_pipe, false);
- INT_POST_HANDLER();
-}
diff --git a/port/nrf5x/README.md b/port/nrf5x/README.md
deleted file mode 100644
index 5f976a02..00000000
--- a/port/nrf5x/README.md
+++ /dev/null
@@ -1,9 +0,0 @@
-# Note
-
-## Support Chip List
-
-- NRF5x
-
-## Before Use
-
-- Your should implement `usb_dc_low_level_pre_init`,`usb_dc_low_level_post_init`,`usb_dc_low_level_deinit`. \ No newline at end of file
diff --git a/port/nrf5x/nrf5x_regs.h b/port/nrf5x/nrf5x_regs.h
deleted file mode 100644
index 5f8d32f7..00000000
--- a/port/nrf5x/nrf5x_regs.h
+++ /dev/null
@@ -1,605 +0,0 @@
-#pragma once
-
-
-
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/**
- * @brief USBD_HALTED [HALTED] (Unspecified)
- */
-typedef struct {
- __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status.
- Can be used as is as response to a GetStatus()
- request to endpoint. */
- __IM uint32_t RESERVED;
- __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status.
- Can be used as is as response to a GetStatus()
- request to endpoint. */
-} USBD_HALTED_Type; /*!< Size = 68 (0x44) */
-
-
-/**
- * @brief USBD_SIZE [SIZE] (Unspecified)
- */
-typedef struct {
- __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received
- last in the data stage of this OUT endpoint */
- __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT
- data endpoint */
-} USBD_SIZE_Type; /*!< Size = 36 (0x24) */
-
-
-/**
- * @brief USBD_EPIN [EPIN] (Unspecified)
- */
-typedef struct {
- __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */
- __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes
- to transfer */
- __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred
- in the last transaction */
- __IM uint32_t RESERVED[2];
-} USBD_EPIN_Type; /*!< Size = 20 (0x14) */
-
-
-/**
- * @brief USBD_ISOIN [ISOIN] (Unspecified)
- */
-typedef struct {
- __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
- __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */
- __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
-} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */
-
-
-/**
- * @brief USBD_EPOUT [EPOUT] (Unspecified)
- */
-typedef struct {
- __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */
- __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes
- to transfer */
- __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred
- in the last transaction */
- __IM uint32_t RESERVED[2];
-} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */
-
-
-/**
- * @brief USBD_ISOOUT [ISOOUT] (Unspecified)
- */
-typedef struct {
- __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
- __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */
- __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
-} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */
-
-typedef struct { /*!< (@ 0x40027000) USBD Structure */
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR
- and EPIN[n].MAXCNT registers values, and
- enables endpoint IN n to respond to traffic
- from host */
- __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers
- values, and enables sending data on ISO
- endpoint */
- __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR
- and EPOUT[n].MAXCNT registers values, and
- enables endpoint n to respond to traffic
- from host */
- __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers
- values, and enables receiving of data on
- ISO endpoint */
- __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */
- __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */
- __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint
- 0 */
- __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined
- in the DPDMVALUE register */
- __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state
- (USB engine takes control) */
- __IM uint32_t RESERVED1[40];
- __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected
- on USB lines */
- __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT,
- or EPOUT[n].PTR and EPOUT[n].MAXCNT registers
- have been captured on all endpoints reported
- in the EPSTATUS register */
- __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer
- has been consumed. The RAM buffer can be
- accessed safely by software. */
- __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place
- on the control endpoint */
- __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The
- RAM buffer can be accessed safely by software. */
- __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer
- has been consumed. The RAM buffer can be
- accessed safely by software. */
- __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The
- RAM buffer can be accessed safely by software. */
- __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition
- has been detected on USB lines */
- __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific
- events has occurred. Check EVENTCAUSE register
- to find the cause. */
- __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged)
- on the control endpoint */
- __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint,
- indicated by the EPDATASTATUS register */
- __IM uint32_t RESERVED2[39];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
- __IM uint32_t RESERVED3[63];
- __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
- __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
- __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED4[61];
- __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */
- __IM uint32_t RESERVED5[7];
- __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */
- __IM uint32_t RESERVED6;
- __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA
- registers have been captured */
- __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an
- acknowledged data transfer has occurred
- (EPDATA event) */
- __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */
- __IM uint32_t RESERVED7[3];
- __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */
- __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */
- __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */
- __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */
- __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */
- __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */
- __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */
- __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */
- __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */
- __IM uint32_t RESERVED8[15];
- __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */
- __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */
- __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by
- the DPDMDRIVE task. The DPDMNODRIVE task
- reverts the control of the lines to MAC
- IP (no forcing). */
- __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */
- __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */
- __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */
- __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */
- __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */
- __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame
- counter */
- __IM uint32_t RESERVED9[2];
- __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during
- USB suspend */
- __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint
- to an IN token when no data is ready to
- be sent */
- __IM uint32_t RESERVED10[51];
- __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */
- __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */
- __IM uint32_t RESERVED11[21];
- __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */
- __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */
-} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */
-
-
-/* Register: USBD_EPINEN */
-/* Description: Endpoint IN enable */
-
-/* Bit 8 : Enable ISO IN endpoint */
-#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
-#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
-#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */
-#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */
-
-/* Bit 7 : Enable IN endpoint 7 */
-#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
-#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
-#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable IN endpoint 7 */
-#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable IN endpoint 7 */
-
-/* Bit 6 : Enable IN endpoint 6 */
-#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
-#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
-#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
-#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
-
-/* Bit 5 : Enable IN endpoint 5 */
-#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
-#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
-#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
-#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
-
-/* Bit 4 : Enable IN endpoint 4 */
-#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
-#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
-#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
-#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
-
-/* Bit 3 : Enable IN endpoint 3 */
-#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
-#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
-#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
-#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
-
-/* Bit 2 : Enable IN endpoint 2 */
-#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
-#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
-#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
-#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
-
-/* Bit 1 : Enable IN endpoint 1 */
-#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
-#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
-#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
-#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
-
-/* Bit 0 : Enable IN endpoint 0 */
-#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
-#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
-#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
-#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
-
-/* Register: USBD_EPOUTEN */
-/* Description: Endpoint OUT enable */
-
-/* Bit 8 : Enable ISO OUT endpoint 8 */
-#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
-#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
-#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */
-#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */
-
-/* Bit 7 : Enable OUT endpoint 7 */
-#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
-#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
-#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
-
-/* Bit 6 : Enable OUT endpoint 6 */
-#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
-#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
-#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
-
-/* Bit 5 : Enable OUT endpoint 5 */
-#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
-#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
-#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
-
-/* Bit 4 : Enable OUT endpoint 4 */
-#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
-#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
-#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
-
-/* Bit 3 : Enable OUT endpoint 3 */
-#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
-#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
-#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
-
-/* Bit 2 : Enable OUT endpoint 2 */
-#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
-#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
-#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
-
-/* Bit 1 : Enable OUT endpoint 1 */
-#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
-#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
-#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
-
-/* Bit 0 : Enable OUT endpoint 0 */
-#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
-#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
-#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
-#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
-
-/* Register: USBD_INTEN */
-/* Description: Enable or disable interrupt */
-
-/* Bit 24 : Enable or disable interrupt for event EPDATA */
-#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
-#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
-#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
-
-/* Bit 23 : Enable or disable interrupt for event EP0SETUP */
-#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
-#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
-#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
-
-/* Bit 22 : Enable or disable interrupt for event USBEVENT */
-#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
-#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
-#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
-
-/* Bit 21 : Enable or disable interrupt for event SOF */
-#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
-#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
-#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
-
-/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
-#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
-#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
-#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
-
-/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
-#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
-#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
-#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
-
-/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
-#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
-#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
-#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
-
-/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
-#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
-#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
-#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
-
-/* Bit 11 : Enable or disable interrupt for event ENDISOIN */
-#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
-#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
-#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
-
-/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
-#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
-#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
-#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
-
-/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
-#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
-#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
-#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
-
-/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
-#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
-#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
-#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
-
-/* Bit 1 : Enable or disable interrupt for event STARTED */
-#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
-#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
-#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
-
-/* Bit 0 : Enable or disable interrupt for event USBRESET */
-#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
-#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
-#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
-#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
-
-/* Register: USBD_INTENSET */
-/* Description: Enable interrupt */
-
-/* Bit 21 : Write '1' to enable interrupt for event SOF */
-#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
-#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
-#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
-#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
-#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
-
-/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
-#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
-#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
-#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
-#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
-#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
-
-/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
-#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
-#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
-#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
-#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
-#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
-
-/* Register: USBD_INTENCLR */
-/* Description: Disable interrupt */
-
-/* Bit 21 : Write '1' to disable interrupt for event SOF */
-#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
-#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
-#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
-#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
-#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
-
-/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
-#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
-#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
-#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
-#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
-#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
-
-/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
-#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
-#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
-#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
-#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
-#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
-
-/* Register: USBD_ISOSPLIT */
-/* Description: Controls the split of ISO buffers */
-
-/* Bits 15..0 : Controls the split of ISO buffers */
-#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
-#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
-#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */
-#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
-
-/* Register: USBD_EPSTALL */
-/* Description: STALL endpoints */
-
-/* Bit 8 : Stall selected endpoint */
-#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
-#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
-#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
-#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
-
-/* Register: USBD_DPDMVALUE */
-/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
-
-/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
-#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
-#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
-#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
-#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
-#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
-
-/* Register: USBD_DTOGGLE */
-/* Description: Data toggle control and status */
-
-/* Bits 9..8 : Data toggle value */
-#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
-#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
-#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
-#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
-#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
-
-/* Register: USBD_EVENTCAUSE */
-/* Description: Details on what caused the USBEVENT event */
-
-/* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
-#define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
-#define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
-#define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */
-#define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */
-
-/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
-#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
-#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
-#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
-#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
-
-/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
-#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
-#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
-#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
-#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
-
-/* Register: USBD_SIZE_ISOOUT */
-/* Description: Number of bytes received last on this ISO OUT data endpoint */
-
-/* Bit 16 : Zero-length data packet received */
-#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
-#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
-#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
-#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
-
-/* Register: USBD_EVENTCAUSE */
-/* Description: Details on what caused the USBEVENT event */
-
-/* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
-#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
-#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
-#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
-#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
-
-/* Register: USBD_ISOINCONFIG */
-/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
-
-/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
-#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
-#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
-#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
-#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
-
-
-
-
-/**
- * @brief Clock control (CLOCK)
- */
-
-typedef struct { /*!< (@ 0x40000000) CLOCK Structure */
- __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */
- __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */
- __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */
- __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */
- __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */
- __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */
- __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */
- __IM uint32_t RESERVED[57];
- __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */
- __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */
- __IM uint32_t RESERVED1;
- __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */
- __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */
- __IM uint32_t RESERVED2[5];
- __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready
- to process new tasks */
- __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready
- to process new tasks */
- __IM uint32_t RESERVED3[117];
- __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
- __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED4[63];
- __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
- triggered */
- __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */
- __IM uint32_t RESERVED5;
- __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
- triggered */
- __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */
- __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART
- task was triggered */
- __IM uint32_t RESERVED6[62];
- __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */
- __IM uint32_t RESERVED7[3];
- __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering
- the TASKS_HFCLKSTART task. */
- __IM uint32_t RESERVED8[3];
- __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */
- __IM uint32_t RESERVED9[8];
- __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */
- __IM uint32_t RESERVED10[21];
- __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */
-} NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */
-
-
-#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
-#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
-
-
-/* Bit 0 : Source of HFCLK */
-#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
-#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
-
-
-
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RESERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
diff --git a/port/nrf5x/usb_dc_nrf5x.c b/port/nrf5x/usb_dc_nrf5x.c
deleted file mode 100644
index 9007e194..00000000
--- a/port/nrf5x/usb_dc_nrf5x.c
+++ /dev/null
@@ -1,1308 +0,0 @@
-#include <stddef.h>
-#include "usb_dc.h"
-#include "usbd_core.h"
-#include "nrf5x_regs.h"
-
-#define __ISB() \
- do \
- { \
- __schedule_barrier(); \
- __isb(0xF); \
- __schedule_barrier(); \
- } while (0U)
-
-#define __DSB() \
- do \
- { \
- __schedule_barrier(); \
- __dsb(0xF); \
- __schedule_barrier(); \
- } while (0U)
-
-#ifndef USBD_IRQHandler
-#define USBD_IRQHandler USBD_IRQHandler /*!< Use actual usb irq name instead */
-#endif
-
-#ifndef USBD_CONFIG_ISO_IN_ZLP
-#define USBD_CONFIG_ISO_IN_ZLP 0
-#endif
-
-/*!< The default platform is NRF52840 */
-#define NRF52_SERIES
-#define NRF52840_XXAA
-
-/*!< Ep nums */
-#define EP_NUMS 9
-/*!< Ep mps */
-#define EP_MPS 64
-/*!< Nrf5x special */
-#define EP_ISO_NUM 8
-
-/*!< USBD peripheral address base */
-#define NRF_USBD_BASE 0x40027000UL
-/*!< Clock peripheral address base */
-#define NRF_CLOCK_BASE 0x40000000UL
-/*!< NVIC peripheral address base */
-#define NVIC_BASE (0xE000E000UL + 0x0100UL)
-
-#define NRF_USBD ((NRF_USBD_Type *)NRF_USBD_BASE)
-#define NRF_CLOCK ((NRF_CLOCK_Type *)NRF_CLOCK_BASE)
-#define NVIC ((NVIC_Type *)NVIC_BASE)
-
-#define USBD_IRQn 39
-
-#ifndef EP_ISO_MPS
-#define EP_ISO_MPS 64
-#endif
-
-#define CHECK_ADD_IS_RAM(address) ((((uint32_t)address) & 0xE0000000u) == 0x20000000u) ? 1 : 0
-
-/**
- * @brief Endpoint information structure
- */
-typedef struct _usbd_ep_info
-{
- uint16_t mps; /*!< Maximum packet length of endpoint */
- uint8_t eptype; /*!< Endpoint Type */
- uint8_t ep_stalled; /* Endpoint stall flag */
- uint8_t ep_enable; /* Endpoint enable */
- uint8_t *xfer_buf;
- uint32_t xfer_len;
- uint32_t actual_xfer_len;
- uint8_t ep_buffer[EP_MPS];
- /*!< Other endpoint parameters that may be used */
- volatile uint8_t is_using_dma;
- volatile uint8_t add_flag;
-} usbd_ep_info;
-
-/*!< nrf52840 usb */
-struct _nrf52840_core_prvi
-{
- uint8_t address; /*!< address */
- usbd_ep_info ep_in[EP_NUMS]; /*!< ep in */
- usbd_ep_info ep_out[EP_NUMS]; /*!< ep out */
- struct usb_setup_packet setup; /*!< Setup package that may be used in interrupt processing (outside the protocol stack) */
- volatile uint8_t dma_running;
- int8_t in_count;
- volatile uint8_t iso_turn;
- volatile uint8_t iso_tx_is_ready;
- /**
- * For nrf5x, easydma will not move the setup packet into RAM.
- * We use a flag bit to judge whether the host sends setup,
- * and then notify usbd_ep_read to and from the register to read the setup package
- */
- volatile uint8_t is_setup_packet;
-} usb_dc_cfg;
-
-__WEAK void usb_dc_low_level_pre_init(void)
-{
-}
-
-__WEAK void usb_dc_low_level_post_init(void)
-{
-}
-
-__WEAK void usb_dc_low_level_deinit(void)
-{
-}
-
-/**
- * @brief Get setup package
- * @pre None
- * @param[in] setup Pointer to the address where the setup package is stored
- * @retval None
- */
-static inline void get_setup_packet(struct usb_setup_packet *setup)
-{
- setup->bmRequestType = (uint8_t)(NRF_USBD->BMREQUESTTYPE);
- setup->bRequest = (uint8_t)(NRF_USBD->BREQUEST);
- setup->wIndex = (uint16_t)(NRF_USBD->WINDEXL | ((NRF_USBD->WINDEXH) << 8));
- setup->wLength = (uint16_t)(NRF_USBD->WLENGTHL | ((NRF_USBD->WLENGTHH) << 8));
- setup->wValue = (uint16_t)(NRF_USBD->WVALUEL | ((NRF_USBD->WVALUEH) << 8));
-}
-
-/**
- * @brief Set tx easydma
- * @pre None
- * @param[in] ep End point address
- * @param[in] ptr Data ram ptr
- * @param[in] maxcnt Max length
- * @retval None
- */
-static void nrf_usbd_ep_easydma_set_tx(uint8_t ep, uint32_t ptr, uint32_t maxcnt)
-{
- uint8_t epid = USB_EP_GET_IDX(ep);
- if (epid == EP_ISO_NUM)
- {
- NRF_USBD->ISOIN.PTR = ptr;
- NRF_USBD->ISOIN.MAXCNT = maxcnt;
- return;
- }
- NRF_USBD->EPIN[epid].PTR = ptr;
- NRF_USBD->EPIN[epid].MAXCNT = maxcnt;
-}
-
-/**
- * @brief Set rx easydma
- * @pre None
- * @param[in] ep End point address
- * @param[in] ptr Data ram ptr
- * @param[in] maxcnt Max length
- * @retval None
- */
-static void nrf_usbd_ep_easydma_set_rx(uint8_t ep, uint32_t ptr, uint32_t maxcnt)
-{
- uint8_t epid = USB_EP_GET_IDX(ep);
- if (epid == EP_ISO_NUM)
- {
- NRF_USBD->ISOOUT.PTR = ptr;
- NRF_USBD->ISOOUT.MAXCNT = maxcnt;
- return;
- }
- NRF_USBD->EPOUT[epid].PTR = ptr;
- NRF_USBD->EPOUT[epid].MAXCNT = maxcnt;
-}
-
-/**
- * @brief Set address
- * @pre None
- * @param[in] address 8-bit valid address
- * @retval >=0 success otherwise failure
- */
-int usbd_set_address(const uint8_t address)
-{
- if (address == 0)
- {
- /*!< init 0 address */
- }
- else
- {
- /*!< For non-0 addresses, write the address to the register in the state phase of setting the address */
- }
-
- NRF_USBD->EVENTCAUSE |= NRF_USBD->EVENTCAUSE;
- NRF_USBD->EVENTS_USBEVENT = 0;
-
- NRF_USBD->INTENSET = USBD_INTEN_USBEVENT_Msk;
- /*!< nothing to do, handled by hardware; but don't STALL */
- usb_dc_cfg.address = address;
- return 0;
-}
-
-uint8_t usbd_get_port_speed(const uint8_t port)
-{
- return USB_SPEED_FULL;
-}
-
-/**
- * @brief Open endpoint
- * @pre None
- * @param[in] ep_cfg : Endpoint configuration structure pointer
- * @retval >=0 success otherwise failure
- */
-int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
-{
- /*!< ep id */
- uint8_t epid = USB_EP_GET_IDX(ep->bEndpointAddress);
- /*!< ep max packet length */
- uint8_t mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
- if (USB_EP_DIR_IS_IN(ep->bEndpointAddress))
- {
- /*!< In */
- usb_dc_cfg.ep_in[epid].mps = mps;
- usb_dc_cfg.ep_in[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
- usb_dc_cfg.ep_in[epid].ep_enable = true;
- /*!< Open ep */
- if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS)
- {
- /*!< Enable endpoint interrupt */
- NRF_USBD->INTENSET = (1 << (USBD_INTEN_ENDEPIN0_Pos + epid));
- /*!< Enable the in endpoint host to respond when sending in token */
- NRF_USBD->EPINEN |= (1 << (epid));
- __ISB();
- __DSB();
- }
- else
- {
- NRF_USBD->EVENTS_ENDISOIN = 0;
- /*!< SPLIT ISO buffer when ISO OUT endpoint is already opened. */
- if (usb_dc_cfg.ep_out[EP_ISO_NUM].mps)
- NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
-
- /*!< Clear SOF event in case interrupt was not enabled yet. */
- if ((NRF_USBD->INTEN & USBD_INTEN_SOF_Msk) == 0)
- NRF_USBD->EVENTS_SOF = 0;
-
- /*!< Enable SOF and ISOIN interrupts, and ISOIN endpoint. */
- NRF_USBD->INTENSET = USBD_INTENSET_ENDISOIN_Msk | USBD_INTENSET_SOF_Msk;
- NRF_USBD->EPINEN |= USBD_EPINEN_ISOIN_Msk;
- }
- }
- else if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress))
- {
- /*!< Out */
- usb_dc_cfg.ep_out[epid].mps = mps;
- usb_dc_cfg.ep_out[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
- usb_dc_cfg.ep_out[epid].ep_enable = true;
- /*!< Open ep */
- if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS)
- {
- NRF_USBD->INTENSET = (1 << (USBD_INTEN_ENDEPOUT0_Pos + epid));
- NRF_USBD->EPOUTEN |= (1 << (epid));
- __ISB();
- __DSB();
- /*!< Write any value to SIZE register will allow nRF to ACK/accept data */
- NRF_USBD->SIZE.EPOUT[epid] = 0;
- }
- else
- {
- /*!< SPLIT ISO buffer when ISO IN endpoint is already opened. */
- if (usb_dc_cfg.ep_in[EP_ISO_NUM].mps)
- NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
-
- /*!< Clear old events */
- NRF_USBD->EVENTS_ENDISOOUT = 0;
-
- /*!< Clear SOF event in case interrupt was not enabled yet. */
- if ((NRF_USBD->INTEN & USBD_INTEN_SOF_Msk) == 0)
- NRF_USBD->EVENTS_SOF = 0;
-
- /*!< Enable SOF and ISOOUT interrupts, and ISOOUT endpoint. */
- NRF_USBD->INTENSET = USBD_INTENSET_ENDISOOUT_Msk | USBD_INTENSET_SOF_Msk;
- NRF_USBD->EPOUTEN |= USBD_EPOUTEN_ISOOUT_Msk;
- }
- }
-
- /*!< Clear stall and reset DataToggle */
- NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | (ep->bEndpointAddress);
- NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | (ep->bEndpointAddress);
-
- __ISB();
- __DSB();
-
- return 0;
-}
-
-/**
- * @brief Close endpoint
- * @pre None
- * @param[in] ep ： Endpoint address
- * @retval >=0 success otherwise failure
- */
-int usbd_ep_close(const uint8_t ep)
-{
- /*!< ep id */
- uint8_t epid = USB_EP_GET_IDX(ep);
- if (epid != EP_ISO_NUM)
- {
-
- if (USB_EP_DIR_IS_OUT(ep))
- {
- usb_dc_cfg.ep_out[epid].ep_enable = false;
- NRF_USBD->INTENCLR = (1 << (USBD_INTEN_ENDEPOUT0_Pos + epid));
- NRF_USBD->EPOUTEN &= ~(1 << (epid));
- }
- else
- {
- usb_dc_cfg.ep_in[epid].ep_enable = false;
- NRF_USBD->INTENCLR = (1 << (USBD_INTEN_ENDEPIN0_Pos + epid));
- NRF_USBD->EPINEN &= ~(1 << (epid));
- }
- }
- else
- {
- /*!< ISO EP */
- if (USB_EP_DIR_IS_OUT(ep))
- {
- usb_dc_cfg.ep_out[epid].ep_enable = false;
- usb_dc_cfg.ep_out[EP_ISO_NUM].mps = 0;
- NRF_USBD->INTENCLR = USBD_INTENCLR_ENDISOOUT_Msk;
- NRF_USBD->EPOUTEN &= ~USBD_EPOUTEN_ISOOUT_Msk;
- NRF_USBD->EVENTS_ENDISOOUT = 0;
- }
- else
- {
- usb_dc_cfg.ep_in[epid].ep_enable = false;
- usb_dc_cfg.ep_in[EP_ISO_NUM].mps = 0;
- NRF_USBD->INTENCLR = USBD_INTENCLR_ENDISOIN_Msk;
- NRF_USBD->EPINEN &= ~USBD_EPINEN_ISOIN_Msk;
- }
- /*!< One of the ISO endpoints closed, no need to split buffers any more. */
- NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_OneDir;
- /*!< When both ISO endpoint are close there is no need for SOF any more. */
- if (usb_dc_cfg.ep_in[EP_ISO_NUM].mps + usb_dc_cfg.ep_out[EP_ISO_NUM].mps == 0)
- {
- NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
- }
- }
- __ISB();
- __DSB();
-
- return 0;
-}
-
-/**
- * @brief Setup in ep transfer setting and start transfer.
- *
- * This function is asynchronous.
- * This function is similar to uart with tx dma.
- *
- * This function is called to write data to the specified endpoint. The
- * supplied usbd_endpoint_callback function will be called when data is transmitted
- * out.
- *
- * @param[in] ep Endpoint address corresponding to the one
- * listed in the device configuration table
- * @param[in] data Pointer to data to write
- * @param[in] data_len Length of the data requested to write. This may
- * be zero for a zero length status packet.
- * @return 0 on success, negative errno code on fail.
- */
-int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
-{
- uint8_t ep_idx = USB_EP_GET_IDX(ep);
-
- if (!data && data_len)
- {
- return -1;
- }
- if (!usb_dc_cfg.ep_in[ep_idx].ep_enable)
- {
- return -2;
- }
- if ((uint32_t)data & 0x03)
- {
- return -3;
- }
-
- usb_dc_cfg.ep_in[ep_idx].xfer_buf = (uint8_t *)data;
- usb_dc_cfg.ep_in[ep_idx].xfer_len = data_len;
- usb_dc_cfg.ep_in[ep_idx].actual_xfer_len = 0;
-
- if (data_len == 0)
- {
- /*!< write 0 len data */
- nrf_usbd_ep_easydma_set_tx(ep_idx, NULL, 0);
- NRF_USBD->TASKS_STARTEPIN[ep_idx] = 1;
- }
- else
- {
- /*!< Not zlp */
- data_len = MIN(data_len, usb_dc_cfg.ep_in[ep_idx].mps);
- if (!CHECK_ADD_IS_RAM(data))
- {
- /*!< Data is not in ram */
- /*!< Memcpy data to ram */
- memcpy(usb_dc_cfg.ep_in[ep_idx].ep_buffer, data, data_len);
- nrf_usbd_ep_easydma_set_tx(ep_idx, (uint32_t)usb_dc_cfg.ep_in[ep_idx].ep_buffer, data_len);
- }
- else
- {
- nrf_usbd_ep_easydma_set_tx(ep_idx, (uint32_t)data, data_len);
- }
- /**
- * Note that starting DMA transmission is to transmit data to USB peripherals,
- * and then wait for the host to get it
- */
- /*!< Start dma transfer */
- if (ep_idx != EP_ISO_NUM)
- {
- NRF_USBD->TASKS_STARTEPIN[ep_idx] = 1;
- }
- else
- {
- // NRF_USBD->TASKS_STARTISOIN = 1;
- usb_dc_cfg.iso_tx_is_ready = 1;
- }
- }
- return 0;
-}
-
-/**
- * @brief Setup out ep transfer setting and start transfer.
- *
- * This function is asynchronous.
- * This function is similar to uart with rx dma.
- *
- * This function is called to read data to the specified endpoint. The
- * supplied usbd_endpoint_callback function will be called when data is received
- * in.
- *
- * @param[in] ep Endpoint address corresponding to the one
- * listed in the device configuration table
- * @param[in] data Pointer to data to read
- * @param[in] data_len Max length of the data requested to read.
- *
- * @return 0 on success, negative errno code on fail.
- */
-int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
-{
- uint8_t ep_idx = USB_EP_GET_IDX(ep);
-
- if (!data && data_len)
- {
- return -1;
- }
- if (!usb_dc_cfg.ep_out[ep_idx].ep_enable)
- {
- return -2;
- }
- if ((uint32_t)data & 0x03)
- {
- return -3;
- }
-
- usb_dc_cfg.ep_out[ep_idx].xfer_buf = (uint8_t *)data;
- usb_dc_cfg.ep_out[ep_idx].xfer_len = data_len;
- usb_dc_cfg.ep_out[ep_idx].actual_xfer_len = 0;
-
- if (data_len == 0)
- {
- return 0;
- }
- else
- {
- data_len = MIN(data_len, usb_dc_cfg.ep_out[ep_idx].mps);
- if (!CHECK_ADD_IS_RAM(data))
- {
- /*!< Data address is not in ram */
- // TODO:
- }
- else
- {
- if (ep_idx == 0)
- {
- NRF_USBD->TASKS_EP0RCVOUT = 1;
- }
- nrf_usbd_ep_easydma_set_rx(ep_idx, (uint32_t)data, data_len);
- }
- }
- return 0;
-}
-
-/**
- * @brief Endpoint setting pause
- * @pre None
- * @param[in] ep ： Endpoint address
- * @retval >=0 success otherwise failure
- */
-int usbd_ep_set_stall(const uint8_t ep)
-{
- /*!< ep id */
- uint8_t epid = USB_EP_GET_IDX(ep);
- if (epid == 0)
- {
- NRF_USBD->TASKS_EP0STALL = 1;
- }
- else if (epid != EP_ISO_NUM)
- {
- NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | (ep);
- }
- __ISB();
- __DSB();
- return 0;
-}
-
-/**
- * @brief Endpoint clear pause
- * @pre None
- * @param[in] ep ： Endpoint address
- * @retval >=0 success otherwise failure
- */
-int usbd_ep_clear_stall(const uint8_t ep)
-{
- /*!< ep id */
- uint8_t epid = USB_EP_GET_IDX(ep);
-
- if (epid != 0 && epid != EP_ISO_NUM)
- {
- /**
- * reset data toggle to DATA0
- * First write this register with VALUE=Nop to select the endpoint, then either read it to get the status from
- * VALUE, or write it again with VALUE=Data0 or Data1
- */
- NRF_USBD->DTOGGLE = ep;
- NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep;
-
- /*!< Clear stall */
- NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep;
-
- /*!< Write any value to SIZE register will allow nRF to ACK/accept data */
- if (USB_EP_DIR_IS_OUT(ep))
- NRF_USBD->SIZE.EPOUT[epid] = 0;
-
- __ISB();
- __DSB();
- }
-
- return 0;
-}
-
-/**
- * @brief Check endpoint status
- * @pre None
- * @param[in] ep ： Endpoint address
- * @param[out] stalled ： Outgoing endpoint status
- * @retval >=0 success otherwise failure
- */
-int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
-{
- return 0;
-}
-
-/**
- * @brief USB initialization
- * @pre None
- * @param[in] None
- * @retval >=0 success otherwise failure
- */
-int usb_dc_init(void)
-{
- /*!< dc init */
- usb_dc_low_level_pre_init();
-
- memset(&usb_dc_cfg, 0, sizeof(usb_dc_cfg));
- /*!< Clear USB Event Interrupt */
- NRF_USBD->EVENTS_USBEVENT = 0;
- NRF_USBD->EVENTCAUSE |= NRF_USBD->EVENTCAUSE;
-
- /*!< Reset interrupt */
- NRF_USBD->INTENCLR = NRF_USBD->INTEN;
- NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
- USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk | USBD_INTEN_STARTED_Msk;
-
- usb_dc_low_level_post_init();
- return 0;
-}
-
-/**
- * @brief USB interrupt processing function
- * @pre None
- * @param[in] None
- * @retval None
- */
-void USBD_IRQHandler(void)
-{
- uint32_t const inten = NRF_USBD->INTEN;
- uint32_t int_status = 0;
- volatile uint32_t usb_event = 0;
- volatile uint32_t *regevt = &NRF_USBD->EVENTS_USBRESET;
-
- /*!< Traverse USB events */
- for (uint8_t i = 0; i < USBD_INTEN_EPDATA_Pos + 1; i++)
- {
- if ((inten & (1 << i)) && regevt[i])
- {
- int_status |= (1 << (i));
- /*!< event clear */
- regevt[i] = 0;
- __ISB();
- __DSB();
- }
- }
-
- /*!< bit 24 */
- if (int_status & USBD_INTEN_EPDATA_Msk)
- {
- /*!< out ep */
- for (uint8_t ep_out_ct = 1; ep_out_ct <= 7; ep_out_ct++)
- {
- if ((NRF_USBD->EPDATASTATUS) & (1 << (16 + ep_out_ct)))
- {
- NRF_USBD->EPDATASTATUS |= (1 << (16 + ep_out_ct));
- /*!< The data arrives at the usb fifo, starts the dma transmission, and transfers it to the user ram */
- NRF_USBD->TASKS_STARTEPOUT[ep_out_ct] = 1;
- }
- }
- /*!< in ep */
- for (uint8_t ep_in_ct = 1; ep_in_ct <= 7; ep_in_ct++)
- {
- if ((NRF_USBD->EPDATASTATUS) & (1 << (0 + ep_in_ct)))
- {
- /*!< in ep tranfer to host successfully */
- NRF_USBD->EPDATASTATUS |= (1 << (0 + ep_in_ct));
- if (usb_dc_cfg.ep_in[ep_in_ct].xfer_len > usb_dc_cfg.ep_in[ep_in_ct].mps)
- {
- /*!< Need start in again */
- usb_dc_cfg.ep_in[ep_in_ct].xfer_buf += usb_dc_cfg.ep_in[ep_in_ct].mps;
- usb_dc_cfg.ep_in[ep_in_ct].xfer_len -= usb_dc_cfg.ep_in[ep_in_ct].mps;
- usb_dc_cfg.ep_in[ep_in_ct].actual_xfer_len += usb_dc_cfg.ep_in[ep_in_ct].mps;
- if (usb_dc_cfg.ep_in[ep_in_ct].xfer_len > usb_dc_cfg.ep_in[ep_in_ct].mps)
- {
- nrf_usbd_ep_easydma_set_tx(ep_in_ct, (uint32_t)usb_dc_cfg.ep_in[ep_in_ct].xfer_buf, usb_dc_cfg.ep_in[ep_in_ct].mps);
- }
- else
- {
- nrf_usbd_ep_easydma_set_tx(ep_in_ct, (uint32_t)usb_dc_cfg.ep_in[ep_in_ct].xfer_buf, usb_dc_cfg.ep_in[ep_in_ct].xfer_len);
- }
- NRF_USBD->TASKS_STARTEPIN[ep_in_ct] = 1;
- }
- else
- {
- usb_dc_cfg.ep_in[ep_in_ct].actual_xfer_len += usb_dc_cfg.ep_in[ep_in_ct].xfer_len;
- usb_dc_cfg.ep_in[ep_in_ct].xfer_len = 0;
- usbd_event_ep_in_complete_handler(ep_in_ct | 0x80, usb_dc_cfg.ep_in[ep_in_ct].actual_xfer_len);
- }
- }
- }
- }
-
- /*!< bit 23 */
- if (int_status & USBD_INTEN_EP0SETUP_Msk)
- {
- /* Setup */
- /*!< Storing this setup package will help the following procedures */
- get_setup_packet(&(usb_dc_cfg.setup));
- /*!< Nrf52840 will set the address automatically by hardware,
- so the protocol stack of the address setting command sent by the host does not need to be processed */
-
- if (usb_dc_cfg.setup.wLength == 0)
- {
- NRF_USBD->TASKS_EP0STATUS = 1;
- }
-
- if (usb_dc_cfg.setup.bRequest != USB_REQUEST_SET_ADDRESS)
- {
- usbd_event_ep0_setup_complete_handler((uint8_t *)&(usb_dc_cfg.setup));
- }
- }
-
- /*!< bit 22 */
- if (int_status & USBD_INTEN_USBEVENT_Msk)
- {
- usb_event = NRF_USBD->EVENTCAUSE;
- NRF_USBD->EVENTCAUSE = usb_event;
- if (usb_event & USBD_EVENTCAUSE_SUSPEND_Msk)
- {
- NRF_USBD->LOWPOWER = 1;
- /*!< */
- }
- if (usb_event & USBD_EVENTCAUSE_RESUME_Msk)
- {
- /*!< */
- }
- if (usb_event & USBD_EVENTCAUSE_USBWUALLOWED_Msk)
- {
- NRF_USBD->DPDMVALUE = USBD_DPDMVALUE_STATE_Resume;
- NRF_USBD->TASKS_DPDMDRIVE = 1;
- /**
- * There is no Resume interrupt for remote wakeup, enable SOF for to report bus ready state
- * Clear SOF event in case interrupt was not enabled yet.
- */
- if ((NRF_USBD->INTEN & USBD_INTEN_SOF_Msk) == 0)
- NRF_USBD->EVENTS_SOF = 0;
- NRF_USBD->INTENSET = USBD_INTENSET_SOF_Msk;
- }
- }
-
- /*!< bit 21 */
- if (int_status & USBD_INTEN_SOF_Msk)
- {
- bool iso_enabled = false;
- /*!< ISOOUT: Transfer data gathered in previous frame from buffer to RAM */
- if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
- {
- iso_enabled = true;
- /*!< If ZERO bit is set, ignore ISOOUT length */
- if ((NRF_USBD->SIZE.ISOOUT) & USBD_SIZE_ISOOUT_ZERO_Msk)
- {
- }
- else
- {
- /*!< Trigger DMA move data from Endpoint -> SRAM */
- NRF_USBD->TASKS_STARTISOOUT = 1;
- /*!< EP_ISO_NUM out using dma */
- usb_dc_cfg.ep_out[EP_ISO_NUM].is_using_dma = 1;
- }
- }
-
- /*!< ISOIN: Notify client that data was transferred */
- if (NRF_USBD->EPINEN & USBD_EPINEN_ISOIN_Msk)
- {
- iso_enabled = true;
- if (usb_dc_cfg.iso_tx_is_ready == 1)
- {
- usb_dc_cfg.iso_tx_is_ready = 0;
- NRF_USBD->TASKS_STARTISOIN = 1;
- }
- }
-
- if (!iso_enabled)
- {
- /**
- * ISO endpoint is not used, SOF is only enabled one-time for remote wakeup
- * so we disable it now
- */
- NRF_USBD->INTENCLR = USBD_INTENSET_SOF_Msk;
- }
- }
-
- /*!< bit 20 */
- if (int_status & USBD_INTEN_ENDISOOUT_Msk)
- {
- if (usb_dc_cfg.ep_out[EP_ISO_NUM].is_using_dma == 1)
- {
- usb_dc_cfg.ep_out[EP_ISO_NUM].is_using_dma = 0;
- uint32_t read_count = NRF_USBD->SIZE.ISOOUT;
- usb_dc_cfg.ep_out[EP_ISO_NUM].xfer_buf += read_count;
- usb_dc_cfg.ep_out[EP_ISO_NUM].actual_xfer_len += read_count;
- usb_dc_cfg.ep_out[EP_ISO_NUM].xfer_len -= read_count;
-
- if ((read_count < usb_dc_cfg.ep_out[EP_ISO_NUM].mps) || (usb_dc_cfg.ep_out[EP_ISO_NUM].xfer_len == 0))
- {
- usbd_event_ep_out_complete_handler(((EP_ISO_NUM)&0x7f), usb_dc_cfg.ep_out[EP_ISO_NUM].actual_xfer_len);
- }
- else
- {
- if (usb_dc_cfg.ep_out[EP_ISO_NUM].xfer_len > usb_dc_cfg.ep_out[EP_ISO_NUM].mps)
- {
- nrf_usbd_ep_easydma_set_rx(((EP_ISO_NUM)&0x7f), (uint32_t)usb_dc_cfg.ep_out[EP_ISO_NUM].xfer_buf, usb_dc_cfg.ep_out[EP_ISO_NUM].mps);
- }
- else
- {
- nrf_usbd_ep_easydma_set_rx(((EP_ISO_NUM)&0x7f), (uint32_t)usb_dc_cfg.ep_out[EP_ISO_NUM].xfer_buf, usb_dc_cfg.ep_out[EP_ISO_NUM].xfer_len);
- }
- }
- }
- }
-
- /**
- * Traverse ordinary out endpoint events, starting from endpoint 1 to endpoint 7,
- * and end 0 for special processing
- */
- for (uint8_t offset = 0; offset < 7; offset++)
- {
- if (int_status & (USBD_INTEN_ENDEPOUT1_Msk << offset))
- {
- /*!< Out 'offset' transfer complete */
- uint32_t read_count = NRF_USBD->SIZE.EPOUT[offset + 1];
- usb_dc_cfg.ep_out[offset + 1].xfer_buf += read_count;
- usb_dc_cfg.ep_out[offset + 1].actual_xfer_len += read_count;
- usb_dc_cfg.ep_out[offset + 1].xfer_len -= read_count;
-
- if ((read_count < usb_dc_cfg.ep_out[offset + 1].mps) || (usb_dc_cfg.ep_out[offset + 1].xfer_len == 0))
- {
- usbd_event_ep_out_complete_handler(((offset + 1) & 0x7f), usb_dc_cfg.ep_out[offset + 1].actual_xfer_len);
- }
- else
- {
- if (usb_dc_cfg.ep_out[offset + 1].xfer_len > usb_dc_cfg.ep_out[offset + 1].mps)
- {
- nrf_usbd_ep_easydma_set_rx(((offset + 1) & 0x7f), (uint32_t)usb_dc_cfg.ep_out[offset + 1].xfer_buf, usb_dc_cfg.ep_out[offset + 1].mps);
- }
- else
- {
- nrf_usbd_ep_easydma_set_rx(((offset + 1) & 0x7f), (uint32_t)usb_dc_cfg.ep_out[offset + 1].xfer_buf, usb_dc_cfg.ep_out[offset + 1].xfer_len);
- }
- }
- }
- }
-
- /*!< bit 12 */
- if (int_status & USBD_INTEN_ENDEPOUT0_Msk)
- {
- uint32_t read_count = NRF_USBD->SIZE.EPOUT[0];
- usb_dc_cfg.ep_out[0].actual_xfer_len += read_count;
- usb_dc_cfg.ep_out[0].xfer_len -= read_count;
-
- if (usb_dc_cfg.ep_out[0].xfer_len == 0)
- {
- /*!< Enable the state phase of endpoint 0 */
- NRF_USBD->TASKS_EP0STATUS = 1;
- }
-
- usbd_event_ep_out_complete_handler(0x00, usb_dc_cfg.ep_out[0].actual_xfer_len);
- }
-
- /*!< bit 11 */
- if (int_status & USBD_INTEN_ENDISOIN_Msk)
- {
- }
-
- /*!< bit 10 */
- if (int_status & USBD_INTEN_EP0DATADONE_Msk)
- {
- switch (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT)
- {
- case 1:
- /*!< IN */
- if (usb_dc_cfg.ep_in[0].xfer_len > usb_dc_cfg.ep_in[0].mps)
- {
- usb_dc_cfg.ep_in[0].xfer_len -= usb_dc_cfg.ep_in[0].mps;
- usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].mps;
- usbd_event_ep_in_complete_handler(0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len);
- }
- else
- {
- usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].xfer_len;
- usb_dc_cfg.ep_in[0].xfer_len = 0;
- /*!< Enable the state phase of endpoint 0 */
- usbd_event_ep_in_complete_handler(0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len);
- NRF_USBD->TASKS_EP0STATUS = 1;
- }
- break;
- case 0:
- if (usb_dc_cfg.setup.bRequest != USB_REQUEST_SET_ADDRESS)
- {
- /*!< The data arrives at the usb fifo, starts the dma transmission, and transfers it to the user ram */
- NRF_USBD->TASKS_STARTEPOUT[0] = 1;
- }
- break;
- }
- }
-
- /**
- * Traversing ordinary in endpoint events, starting from endpoint 1 to endpoint 7,
- * endpoint 0 special processing
- */
- for (uint8_t offset = 0; offset < 7; offset++)
- {
- if (int_status & (USBD_INTEN_ENDEPIN1_Msk << offset))
- {
- /*!< DMA move data completed */
- }
- }
-
- /*!< bit 1 */
- if (int_status & USBD_INTEN_STARTED_Msk)
- {
- /*!< Easy dma start transfer data */
- }
-
- /*!< bit 2 */
- if (int_status & USBD_INTEN_ENDEPIN0_Msk)
- {
- /*!< EP0 IN DMA move data completed */
- }
-
- /*!< bit 0 */
- if (int_status & USBD_INTEN_USBRESET_Msk)
- {
- NRF_USBD->EPOUTEN = 1UL;
- NRF_USBD->EPINEN = 1UL;
-
- for (int i = 0; i < 8; i++)
- {
- NRF_USBD->TASKS_STARTEPIN[i] = 0;
- NRF_USBD->TASKS_STARTEPOUT[i] = 0;
- }
-
- NRF_USBD->TASKS_STARTISOIN = 0;
- NRF_USBD->TASKS_STARTISOOUT = 0;
-
- /*!< Clear USB Event Interrupt */
- NRF_USBD->EVENTS_USBEVENT = 0;
- NRF_USBD->EVENTCAUSE |= NRF_USBD->EVENTCAUSE;
-
- /*!< Reset interrupt */
- NRF_USBD->INTENCLR = NRF_USBD->INTEN;
- NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
- USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk | USBD_INTEN_STARTED_Msk;
-
- usbd_event_reset_handler();
- }
-}
-
-/**
- * Errata: USB cannot be enabled.
- */
-static bool chyu_nrf52_errata_187(void)
-{
-#ifndef NRF52_SERIES
- return false;
-#else
-#if defined(NRF52820_XXAA) || defined(DEVELOP_IN_NRF52820) || defined(NRF52833_XXAA) || defined(DEVELOP_IN_NRF52833) || defined(NRF52840_XXAA) || defined(DEVELOP_IN_NRF52840)
- uint32_t var1 = *(uint32_t *)0x10000130ul;
- uint32_t var2 = *(uint32_t *)0x10000134ul;
-#endif
-#if defined(NRF52840_XXAA) || defined(DEVELOP_IN_NRF52840)
- if (var1 == 0x08)
- {
- switch (var2)
- {
- case 0x00ul:
- return false;
- case 0x01ul:
- return true;
- case 0x02ul:
- return true;
- case 0x03ul:
- return true;
- default:
- return true;
- }
- }
-#endif
-#if defined(NRF52833_XXAA) || defined(DEVELOP_IN_NRF52833)
- if (var1 == 0x0D)
- {
- switch (var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- default:
- return true;
- }
- }
-#endif
-#if defined(NRF52820_XXAA) || defined(DEVELOP_IN_NRF52820)
- if (var1 == 0x10)
- {
- switch (var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return true;
- default:
- return true;
- }
- }
-#endif
- return false;
-#endif
-}
-
-/**
- * Errata: USBD might not reach its active state.
- */
-static bool chyu_nrf52_errata_171(void)
-{
-#ifndef NRF52_SERIES
- return false;
-#else
-#if defined(NRF52840_XXAA) || defined(DEVELOP_IN_NRF52840)
- uint32_t var1 = *(uint32_t *)0x10000130ul;
- uint32_t var2 = *(uint32_t *)0x10000134ul;
-#endif
-#if defined(NRF52840_XXAA) || defined(DEVELOP_IN_NRF52840)
- if (var1 == 0x08)
- {
- switch (var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return true;
- case 0x03ul:
- return true;
- default:
- return true;
- }
- }
-#endif
- return false;
-#endif
-}
-
-/**
- * Errata: ISO double buffering not functional.
- */
-static bool chyu_nrf52_errata_166(void)
-{
-#ifndef NRF52_SERIES
- return false;
-#else
-#if defined(NRF52840_XXAA) || defined(DEVELOP_IN_NRF52840)
- uint32_t var1 = *(uint32_t *)0x10000130ul;
- uint32_t var2 = *(uint32_t *)0x10000134ul;
-#endif
-#if defined(NRF52840_XXAA) || defined(DEVELOP_IN_NRF52840)
- if (var1 == 0x08)
- {
- switch (var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return true;
- case 0x03ul:
- return true;
- default:
- return true;
- }
- }
-#endif
- return false;
-#endif
-}
-
-#ifdef SOFTDEVICE_PRESENT
-
-#include "nrf_mbr.h"
-#include "nrf_sdm.h"
-#include "nrf_soc.h"
-
-#ifndef SD_MAGIC_NUMBER
-#define SD_MAGIC_NUMBER 0x51B1E5DB
-#endif
-
-static inline bool is_sd_existed(void)
-{
- return *((uint32_t *)(SOFTDEVICE_INFO_STRUCT_ADDRESS + 4)) == SD_MAGIC_NUMBER;
-}
-
-/**
- * check if SD is existed and enabled
- */
-static inline bool is_sd_enabled(void)
-{
- if (!is_sd_existed())
- return false;
-
- uint8_t sd_en = false;
- (void)sd_softdevice_is_enabled(&sd_en);
- return sd_en;
-}
-#endif
-
-static bool hfclk_running(void)
-{
-#ifdef SOFTDEVICE_PRESENT
- if (is_sd_enabled())
- {
- uint32_t is_running = 0;
- (void)sd_clock_hfclk_is_running(&is_running);
- return (is_running ? true : false);
- }
-#endif
-
-#if defined(CLOCK_HFCLKSTAT_SRC_Xtal) || defined(__NRFX_DOXYGEN__)
- return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) ==
- (CLOCK_HFCLKSTAT_STATE_Msk | (CLOCK_HFCLKSTAT_SRC_Xtal << CLOCK_HFCLKSTAT_SRC_Pos));
-#else
- return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) ==
- (CLOCK_HFCLKSTAT_STATE_Msk | (CLOCK_HFCLKSTAT_SRC_HFXO << CLOCK_HFCLKSTAT_SRC_Pos));
-#endif
-}
-
-enum
-{
- NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /*!< HFCLK oscillator started. */
-};
-
-enum
-{
- NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /*!< Start HFCLK clock source. */
- NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /*!< Stop HFCLK clock source. */
-};
-
-static void hfclk_enable(void)
-{
- /*!< already running, nothing to do */
- if (hfclk_running())
- return;
-
-#ifdef SOFTDEVICE_PRESENT
- if (is_sd_enabled())
- {
- (void)sd_clock_hfclk_request();
- return;
- }
-#endif
-
- *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + NRF_CLOCK_EVENT_HFCLKSTARTED)) = 0x0UL;
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + (uint32_t)NRF_CLOCK_EVENT_HFCLKSTARTED));
- (void)dummy;
- *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + NRF_CLOCK_TASK_HFCLKSTART)) = 0x1UL;
-}
-
-static void hfclk_disable(void)
-{
-#ifdef SOFTDEVICE_PRESENT
- if (is_sd_enabled())
- {
- (void)sd_clock_hfclk_release();
- return;
- }
-#endif
-
- *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + NRF_CLOCK_TASK_HFCLKSTOP)) = 0x1UL;
-}
-
-/**
- * Power & Clock Peripheral on nRF5x to manage USB
- * USB Bus power is managed by Power module, there are 3 VBUS power events:
- * Detected, Ready, Removed. Upon these power events, This function will
- * enable ( or disable ) usb & hfclk peripheral, set the usb pin pull up
- * accordingly to the controller Startup/Standby Sequence in USBD 51.4 specs.
- * Therefore this function must be called to handle USB power event by
- * - nrfx_power_usbevt_init() : if Softdevice is not used or enabled
- * - SoftDevice SOC event : if SD is used and enabled
- */
-void cherry_usb_hal_nrf_power_event(uint32_t event)
-{
- enum
- {
- USB_EVT_DETECTED = 0,
- USB_EVT_REMOVED = 1,
- USB_EVT_READY = 2
- };
-
- switch (event)
- {
- case USB_EVT_DETECTED:
- if (!NRF_USBD->ENABLE)
- {
- /*!< Prepare for receiving READY event: disable interrupt since we will blocking wait */
- NRF_USBD->INTENCLR = USBD_INTEN_USBEVENT_Msk;
- NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
- __ISB();
- __DSB();
-
-#ifdef NRF52_SERIES /*!< NRF53 does not need this errata */
- /*!< ERRATA 171, 187, 166 */
- if (chyu_nrf52_errata_187())
- {
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
- }
- }
-
- if (chyu_nrf52_errata_171())
- {
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
- }
- }
-#endif
-
- /*!< Enable the peripheral (will cause Ready event) */
- NRF_USBD->ENABLE = 1;
- __ISB();
- __DSB();
-
- /*!< Enable HFCLK */
- hfclk_enable();
- }
- break;
-
- case USB_EVT_READY:
- /**
- * Skip if pull-up is enabled and HCLK is already running.
- * Application probably call this more than necessary.
- */
- if (NRF_USBD->USBPULLUP && hfclk_running())
- break;
-
- /*!< Waiting for USBD peripheral enabled */
- while (!(USBD_EVENTCAUSE_READY_Msk & NRF_USBD->EVENTCAUSE))
- {
- }
-
- NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
- __ISB();
- __DSB();
-
-#ifdef NRF52_SERIES
- if (chyu_nrf52_errata_171())
- {
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
- }
- }
-
- if (chyu_nrf52_errata_187())
- {
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
- }
- }
-
- if (chyu_nrf52_errata_166())
- {
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7E3;
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = 0x40;
-
- __ISB();
- __DSB();
- }
-#endif
-
- /*!< ISO buffer Lower half for IN, upper half for OUT */
- NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
-
- /*!< Enable bus-reset interrupt */
- NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk;
-
- /*!< Enable interrupt, priorities should be set by application */
- /*!< clear pending irq */
- NVIC->ICPR[(((uint32_t)USBD_IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)USBD_IRQn) & 0x1FUL));
- /**
- * Don't enable USBD interrupt yet, if dcd_init() did not finish yet
- * Interrupt will be enabled by tud_init(), when USB stack is ready
- * to handle interrupts.
- */
- /*!< Wait for HFCLK */
- while (!hfclk_running())
- {
- }
-
- /*!< Enable pull up */
- NRF_USBD->USBPULLUP = 1;
- __ISB();
- __DSB();
- break;
-
- case USB_EVT_REMOVED:
- if (NRF_USBD->ENABLE)
- {
- /*!< Disable pull up */
- NRF_USBD->USBPULLUP = 0;
- __ISB();
- __DSB();
-
- /*!< Disable Interrupt */
- NVIC->ICER[(((uint32_t)USBD_IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)USBD_IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- /*!< disable all interrupt */
- NRF_USBD->INTENCLR = NRF_USBD->INTEN;
-
- NRF_USBD->ENABLE = 0;
- __ISB();
- __DSB();
- hfclk_disable();
- }
- break;
-
- default:
- break;
- }
-}
diff --git a/port/rp2040/usb_dc_rp2040.c b/port/rp2040/usb_dc_rp2040.c
deleted file mode 100644
index 3f011693..00000000
--- a/port/rp2040/usb_dc_rp2040.c
+++ /dev/null
@@ -1,605 +0,0 @@
-#include "usbd_core.h"
-#include "usb_rp2040_reg.h"
-
-#ifndef USBD_IRQHandler
-#define USBD_IRQHandler isr_irq5
-#endif
-
-#ifndef USB_NUM_BIDIR_ENDPOINTS
-#define USB_NUM_BIDIR_ENDPOINTS 16
-#endif
-
-#ifndef FORCE_VBUS_DETECT
-#define FORCE_VBUS_DETECT 1
-#endif
-
-/* Endpoint state */
-struct usb_dc_ep_state {
- uint16_t ep_mps; /* Endpoint max packet size */
- uint8_t ep_type; /* Endpoint type */
- uint8_t ep_stalled; /* Endpoint stall flag */
- uint8_t ep_enable; /* Endpoint enable */
- uint8_t ep_addr; /* Endpoint address */
- uint8_t *xfer_buf;
- uint32_t xfer_len;
- uint32_t actual_xfer_len;
- /**
- * For rp2040
- */
- volatile uint32_t *endpoint_control; /*!< Endpoint control register */
- volatile uint32_t *buffer_control; /*!< Buffer control register */
- uint8_t *dpram_data_buf; /*!< Buffer pointer in usb dpram */
- uint8_t next_pid; /*!< Toggle after each packet (unless replying to a SETUP) */
-};
-
-/* Driver state */
-struct rp2040_udc {
- volatile uint8_t dev_addr;
- struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
- struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
- struct usb_setup_packet setup; /*!< Setup package that may be used in interrupt processing (outside the protocol stack) */
-} g_rp2040_udc;
-
-static uint8_t *next_buffer_ptr;
-
-/**
- * @brief Take a buffer pointer located in the USB RAM and return as an offset of the RAM.
- *
- * @param buf
- * @return uint32_t
- */
-static inline uint32_t usb_buffer_offset(volatile uint8_t *buf)
-{
- return (uint32_t)buf ^ (uint32_t)usb_dpram;
-}
-
-/**
- * @brief Alloc the endpoint dpram and set up ep (if applicable. Not valid for EP0).
- *
- * @param ep
- */
-static int8_t rp2040_usb_config_ep(struct usb_dc_ep_state *ep)
-{
- if (!ep->endpoint_control) {
- USB_LOG_WRN("Not valid for EP0 \r\n");
- return 0;
- }
-
- /*!< size must be multiple of 64 */
- uint16_t size = ((ep->ep_mps + 64 - 1) / 64) * 64;
- /*!< Get current buffer ptr */
- ep->dpram_data_buf = next_buffer_ptr;
- /*!< Update the next buffer ptr */
- next_buffer_ptr += size;
- if (((uint32_t)next_buffer_ptr & 0b111111u) != 0) {
- USB_LOG_ERR("DPRAM Not 64 byte aligned \r\n");
- return -1;
- }
- uint32_t dpram_offset = usb_buffer_offset(ep->dpram_data_buf);
- if (dpram_offset > USB_DPRAM_MAX) {
- USB_LOG_ERR("DPRAM overflow \r\n");
- return -2;
- }
- USB_LOG_INFO("Alloced %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->dpram_data_buf);
- /*!< Enable ep and perbuffer trigger interrupt */
- volatile uint32_t reg = EP_CTRL_ENABLE_BITS | EP_CTRL_INTERRUPT_PER_BUFFER | ((ep->ep_type) << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
- *ep->endpoint_control = reg;
- return 0;
-}
-
-static void rp2040_usb_init(void)
-{
- /*!< Reset usb controller */
- reset_block(RESETS_RESET_USBCTRL_BITS);
- unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
-
- /*!< Clear any previous state just in case */
- memset(usb_hw, 0, sizeof(*usb_hw));
- memset(usb_dpram, 0, sizeof(*usb_dpram));
-
- /*!< Mux the controller to the onboard usb phy */
- usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
-}
-
-int usb_dc_init(void)
-{
- memset(&g_rp2040_udc, 0, sizeof(struct rp2040_udc));
- rp2040_usb_init();
-#if FORCE_VBUS_DETECT
- /*!< Force VBUS detect so the device thinks it is plugged into a host */
- usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
-#endif
-
- /**
- * Initializes the USB peripheral for device mode and enables it.
- * Don't need to enable the pull up here. Force VBUS
- */
- usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS;
-
- /**
- * Enable individual controller IRQS here. Processor interrupt enable will be used
- * for the global interrupt enable...
- * Note: Force VBUS detect cause disconnection not detectable
- */
- usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS;
- usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
- USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS |
- (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
-
- /**
- * Enable interrupt
- * Clear pending before enable
- * (if IRQ is actually asserted, it will immediately re-pend)
- */
- *((io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = 1 << 5;
- *((io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = 1 << 5;
-
- usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
- return 0;
-}
-
-/**
- * @brief Starts a transfer on a given endpoint.
- *
- * @param ep, the endpoint configuration.
- * @param buf, the data buffer to send. Only applicable if the endpoint is TX
- * @param len, the length of the data in buf (this example limits max len to one packet - 64 bytes)
- */
-static void usb_start_transfer(struct usb_dc_ep_state *ep, uint8_t *buf, uint16_t len)
-{
- /*!< Prepare buffer control register value */
- uint32_t val = len | USB_BUF_CTRL_AVAIL;
- if (len < ep->ep_mps) {
- val |= USB_BUF_CTRL_LAST;
- }
-
- if (USB_EP_DIR_IS_IN(ep->ep_addr)) {
- /*!< Need to copy the data from the user buffer to the usb memory */
- if (buf != NULL) {
- memcpy((void *)ep->dpram_data_buf, (void *)buf, len);
- }
- /*!< Mark as full */
- val |= USB_BUF_CTRL_FULL;
- } else {
- }
-
- /*!< Set pid and flip for next transfer */
- val |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
- ep->next_pid ^= 1u;
- /**
- * !Need delay some cycles
- * nop for some clk_sys cycles to ensure that at least one clk_usb cycle has passed. For example if clk_sys was running
- * at 125MHz and clk_usb was running at 48MHz then 125/48 rounded up would be 3 nop instructions
- */
- *ep->buffer_control = val & ~USB_BUF_CTRL_AVAIL;
- __asm volatile(
- "b 1f\n"
- "1: b 1f\n"
- "1: b 1f\n"
- "1: b 1f\n"
- "1: b 1f\n"
- "1: b 1f\n"
- "1: b 1f\n"
- "1:\n"
- :
- :
- : "memory");
- *ep->buffer_control = val;
-}
-
-int usb_dc_deinit(void)
-{
- return 0;
-}
-
-int usbd_set_address(const uint8_t addr)
-{
- if (addr != 0) {
- g_rp2040_udc.dev_addr = addr;
- }
- return 0;
-}
-
-uint8_t usbd_get_port_speed(const uint8_t port)
-{
- return USB_SPEED_FULL;
-}
-
-int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
-{
- uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
-
- if (ep_idx == 0) {
- /**
- * A device must support Endpoint 0 so that it can reply to SETUP packets and be enumerated. As a result, there is no
- * endpoint control register for EP0. Its buffers begin at 0x100. All other endpoints can have either single or dual buffers
- * and are mapped at the base address programmed. As EP0 has no endpoint control register, the interrupt enable
- * controls for EP0 come from SIE_CTRL.
- */
- g_rp2040_udc.out_ep[ep_idx].endpoint_control = NULL;
- g_rp2040_udc.out_ep[ep_idx].dpram_data_buf = (uint8_t *)&usb_dpram->ep0_buf_a[0];
- g_rp2040_udc.in_ep[ep_idx].endpoint_control = NULL;
- g_rp2040_udc.in_ep[ep_idx].dpram_data_buf = (uint8_t *)&usb_dpram->ep0_buf_a[0];
- }
-
- if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
- g_rp2040_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
- g_rp2040_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
- g_rp2040_udc.out_ep[ep_idx].ep_addr = ep->bEndpointAddress;
- g_rp2040_udc.out_ep[ep_idx].ep_enable = true;
- /*!< Get control reg */
- g_rp2040_udc.out_ep[ep_idx].buffer_control = &usb_dpram->ep_buf_ctrl[ep_idx].out;
- /*!< Clear control reg */
- *(g_rp2040_udc.out_ep[ep_idx].buffer_control) = 0;
-
- if (ep_idx != 0) {
- g_rp2040_udc.out_ep[ep_idx].endpoint_control = &usb_dpram->ep_ctrl[ep_idx - 1].out;
- /**
- * Allocate a buffer on DPRAM for the endpoint
- */
- return rp2040_usb_config_ep(&g_rp2040_udc.out_ep[ep_idx]);
- }
-
- } else {
- g_rp2040_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
- g_rp2040_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
- g_rp2040_udc.in_ep[ep_idx].ep_addr = ep->bEndpointAddress;
- g_rp2040_udc.in_ep[ep_idx].ep_enable = true;
- /*!< Get control reg */
- g_rp2040_udc.in_ep[ep_idx].buffer_control = &usb_dpram->ep_buf_ctrl[ep_idx].in;
- /*!< Clear control reg */
- *(g_rp2040_udc.in_ep[ep_idx].buffer_control) = 0;
-
- if (ep_idx != 0) {
- g_rp2040_udc.in_ep[ep_idx].endpoint_control = &usb_dpram->ep_ctrl[ep_idx - 1].in;
- /**
- * Allocate a buffer on DPRAM for the endpoint
- */
- return rp2040_usb_config_ep(&g_rp2040_udc.in_ep[ep_idx]);
- }
- }
- return 0;
-}
-
-int usbd_ep_close(const uint8_t ep)
-{
- /*!< Ep id */
- uint16_t size = 0;
-
- uint8_t epid = USB_EP_GET_IDX(ep);
- if (USB_EP_DIR_IS_IN(ep)) {
- /*!< In */
- size = ((g_rp2040_udc.in_ep[epid].ep_mps + 64 - 1) / 64) * 64;
- memset(g_rp2040_udc.in_ep[epid].dpram_data_buf, 0, size);
- next_buffer_ptr -= size;
- g_rp2040_udc.in_ep[epid].ep_enable = false;
- } else if (USB_EP_DIR_IS_OUT(ep)) {
- /*!< Out */
- size = ((g_rp2040_udc.out_ep[epid].ep_mps + 64 - 1) / 64) * 64;
- memset(g_rp2040_udc.out_ep[epid].dpram_data_buf, 0, size);
- next_buffer_ptr -= size;
- g_rp2040_udc.out_ep[epid].ep_enable = false;
- }
- return 0;
-}
-
-int usbd_ep_set_stall(const uint8_t ep)
-{
- if (USB_EP_GET_IDX(ep) == 0) {
- /**
- * A stall on EP0 has to be armed so it can be cleared on the next setup packet
- */
- usb_hw_set->ep_stall_arm = (USB_EP_DIR_IS_IN(ep)) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
- }
-
- if (USB_EP_DIR_IS_OUT(ep)) {
- *(g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].buffer_control) = USB_BUF_CTRL_STALL;
- } else {
- *(g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].buffer_control) = USB_BUF_CTRL_STALL;
- }
-
- return 0;
-}
-
-int usbd_ep_clear_stall(const uint8_t ep)
-{
- volatile uint32_t value = 0;
- if (USB_EP_GET_IDX(ep)) {
- if (USB_EP_DIR_IS_OUT(ep)) {
- g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].next_pid = 0;
- value = *(g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].buffer_control) & (~USB_BUF_CTRL_STALL);
- *(g_rp2040_udc.out_ep[USB_EP_GET_IDX(ep)].buffer_control) = value;
- } else {
- g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].next_pid = 0;
- value = *(g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].buffer_control) & (~USB_BUF_CTRL_STALL);
- *(g_rp2040_udc.in_ep[USB_EP_GET_IDX(ep)].buffer_control) = value;
- }
- }
- return 0;
-}
-
-int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
-{
- return 0;
-}
-
-int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
-{
- uint8_t ep_idx = USB_EP_GET_IDX(ep);
-
- if (!data && data_len) {
- return -1;
- }
- if (!g_rp2040_udc.in_ep[ep_idx].ep_enable) {
- return -2;
- }
-
- g_rp2040_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
- g_rp2040_udc.in_ep[ep_idx].xfer_len = data_len;
- g_rp2040_udc.in_ep[ep_idx].actual_xfer_len = 0;
-
- if (data_len == 0) {
- usb_start_transfer(&g_rp2040_udc.in_ep[ep_idx], NULL, 0);
- return 0;
- } else {
- /*!< Not zlp */
- data_len = MIN(data_len, g_rp2040_udc.in_ep[ep_idx].ep_mps);
- usb_start_transfer(&g_rp2040_udc.in_ep[ep_idx], g_rp2040_udc.in_ep[ep_idx].xfer_buf, data_len);
- }
-
- return 0;
-}
-
-int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
-{
- uint8_t ep_idx = USB_EP_GET_IDX(ep);
-
- if (!data && data_len) {
- return -1;
- }
- if (!g_rp2040_udc.out_ep[ep_idx].ep_enable) {
- return -2;
- }
- g_rp2040_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data;
- g_rp2040_udc.out_ep[ep_idx].xfer_len = data_len;
- g_rp2040_udc.out_ep[ep_idx].actual_xfer_len = 0;
-
- if (data_len == 0) {
- usb_start_transfer(&g_rp2040_udc.out_ep[ep_idx], NULL, 0);
- return 0;
- } else {
- /*!< Not zlp */
- data_len = MIN(data_len, g_rp2040_udc.out_ep[ep_idx].ep_mps);
- usb_start_transfer(&g_rp2040_udc.out_ep[ep_idx], g_rp2040_udc.out_ep[ep_idx].xfer_buf, data_len);
- }
- return 0;
-}
-
-/**
- * @brief Notify an endpoint that a transfer has completed.
- *
- * @param ep, the endpoint to notify.
- */
-static void usb_handle_ep_buff_done(struct usb_dc_ep_state *ep)
-{
- uint32_t buffer_control = *ep->buffer_control;
- /*!< Get the transfer length for this endpoint */
- uint16_t read_count = buffer_control & USB_BUF_CTRL_LEN_MASK;
- /*!< Call that endpoints buffer done handler */
- if (ep->ep_addr == 0x80) {
- /*!< EP0 In */
- /**
- * Determine the current setup direction
- */
- switch (g_rp2040_udc.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT) {
- case 1:
- /*!< Get */
- if (g_rp2040_udc.in_ep[0].xfer_len > g_rp2040_udc.in_ep[0].ep_mps) {
- g_rp2040_udc.in_ep[0].xfer_len -= g_rp2040_udc.in_ep[0].ep_mps;
- g_rp2040_udc.in_ep[0].actual_xfer_len += g_rp2040_udc.in_ep[0].ep_mps;
- usbd_event_ep_in_complete_handler(0 | 0x80, g_rp2040_udc.in_ep[0].actual_xfer_len);
- } else {
- g_rp2040_udc.in_ep[0].actual_xfer_len += g_rp2040_udc.in_ep[0].xfer_len;
- g_rp2040_udc.in_ep[0].xfer_len = 0;
- /**
- * EP0 In complete and host will send a out token to get 0 length packet
- * In the next usbd_event_ep_in_complete_handler, stack will start read 0 length packet
- * and host must send data1 packet.We resest the ep0 next_pid = 1 in setup interrupt head.
- */
- usbd_event_ep_in_complete_handler(0 | 0x80, g_rp2040_udc.in_ep[0].actual_xfer_len);
- }
- break;
- case 0:
- /*!< Set */
- if (g_rp2040_udc.dev_addr > 0) {
- usb_hw->dev_addr_ctrl = g_rp2040_udc.dev_addr;
- g_rp2040_udc.dev_addr = 0;
- } else {
- /*!< Normal status stage // Setup out...out in */
- /**
- * Perpar for next setup
- */
- }
- break;
- }
-
- } else if (ep->ep_addr == 0x00) {
- /*!< EP0 Out */
- memcpy(g_rp2040_udc.out_ep[0].xfer_buf, g_rp2040_udc.out_ep[0].dpram_data_buf, read_count);
- if (read_count == 0) {
- /*!< Normal status stage // Setup in...in out */
- /**
- * Perpar for next setup
- */
- }
-
- g_rp2040_udc.out_ep[0].actual_xfer_len += read_count;
- g_rp2040_udc.out_ep[0].xfer_len -= read_count;
-
- usbd_event_ep_out_complete_handler(0x00, g_rp2040_udc.out_ep[0].actual_xfer_len);
- } else {
- /*!< Others ep */
- uint16_t data_len = 0;
- if (USB_EP_DIR_IS_OUT(ep->ep_addr)) {
- /*!< flip the pid */
- memcpy(g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_buf, g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].dpram_data_buf, read_count);
- g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_buf += read_count;
- g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].actual_xfer_len += read_count;
- g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_len -= read_count;
-
- if (read_count < g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].ep_mps || g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_len == 0) {
- /*!< Out complete */
- usbd_event_ep_out_complete_handler(ep->ep_addr, g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].actual_xfer_len);
- } else {
- /*!< Need read again */
- data_len = MIN(g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].xfer_len, g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f].ep_mps);
- usb_start_transfer(&g_rp2040_udc.out_ep[(ep->ep_addr) & 0x0f], NULL, data_len);
- }
- } else {
- if (g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len > g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps) {
- /*!< Need tx again */
- g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len -= g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps;
- g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_buf += g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps;
- g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].actual_xfer_len += g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps;
- data_len = MIN(g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len, g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].ep_mps);
- usb_start_transfer(&g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f], g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_buf, data_len);
- } else {
- /*!< In complete */
- g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].actual_xfer_len += g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len;
- g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].xfer_len = 0;
- usbd_event_ep_in_complete_handler(ep->ep_addr, g_rp2040_udc.in_ep[(ep->ep_addr) & 0x0f].actual_xfer_len);
- }
- }
- }
-}
-
-/**
- * @brief Find the endpoint configuration for a specified endpoint number and
- * direction and notify it that a transfer has completed.
- *
- * @param ep_num
- * @param in
- */
-static void usb_handle_buff_done(uint8_t ep_num, bool in)
-{
- uint8_t ep_addr = ep_num | (in ? USB_EP_DIR_IN : 0);
- if (USB_EP_DIR_IS_OUT(ep_addr)) {
- usb_handle_ep_buff_done(&g_rp2040_udc.out_ep[ep_num]);
- } else {
- usb_handle_ep_buff_done(&g_rp2040_udc.in_ep[ep_num]);
- }
-}
-
-/**
- * @brief Handle a "buffer status" irq. This means that one or more
- * buffers have been sent / received. Notify each endpoint where this
- * is the case.
- */
-static void usb_handle_buff_status()
-{
- uint32_t buffers = usb_hw->buf_status;
- uint32_t remaining_buffers = buffers;
-
- uint32_t bit = 1u;
- for (uint8_t i = 0; remaining_buffers && i < USB_NUM_ENDPOINTS * 2; i++) {
- if (remaining_buffers & bit) {
- /*!< clear this in advance */
- usb_hw_clear->buf_status = bit;
- /*!< IN transfer for even i, OUT transfer for odd i */
- usb_handle_buff_done(i >> 1u, !(i & 1u));
- remaining_buffers &= ~bit;
- }
- bit <<= 1u;
- }
-}
-
-void USBD_IRQHandler(void)
-{
- uint32_t const status = usb_hw->ints;
- uint32_t handled = 0;
-
- if (status & USB_INTS_BUFF_STATUS_BITS) {
- handled |= USB_INTS_BUFF_STATUS_BITS;
- usb_handle_buff_status();
- }
-
- if (status & USB_INTS_SETUP_REQ_BITS) {
- handled |= USB_INTS_SETUP_REQ_BITS;
- memcpy((uint8_t *)&g_rp2040_udc.setup, (uint8_t const *)&usb_dpram->setup_packet, 8);
- /**
- * reset pid to both 1 (data and ack)
- */
- g_rp2040_udc.in_ep[0].next_pid = 1;
- g_rp2040_udc.out_ep[0].next_pid = 1;
- usbd_event_ep0_setup_complete_handler((uint8_t *)&g_rp2040_udc.setup);
- usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
- }
-
-#if FORCE_VBUS_DETECT == 0
- /**
- * Since we force VBUS detect On, device will always think it is connected and
- * couldn't distinguish between disconnect and suspend
- */
- if (status & USB_INTS_DEV_CONN_DIS_BITS) {
- handled |= USB_INTS_DEV_CONN_DIS_BITS;
- if (usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS) {
- /*!< Connected: nothing to do */
- } else {
- /*!< Disconnected */
- }
- usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS;
- }
-#endif
-
- /**
- * SE0 for 2.5 us or more (will last at least 10ms)
- */
- if (status & USB_INTS_BUS_RESET_BITS) {
- handled |= USB_INTS_BUS_RESET_BITS;
- usb_hw->dev_addr_ctrl = 0;
-
- for (uint8_t i = 0; i < USB_NUM_BIDIR_ENDPOINTS - 1; i++) {
- /*!< Start at ep1 */
- usb_dpram->ep_ctrl[i].in = 0;
- usb_dpram->ep_ctrl[i].out = 0;
- }
- /*!< reclaim buffer space */
- next_buffer_ptr = &usb_dpram->epx_data[0];
-
- usbd_event_reset_handler();
- usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
-
-#if CHERRYUSB_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
- /**
- * Only run enumeration walk-around if pull up is enabled
- */
- if (usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS)
- rp2040_usb_device_enumeration_fix();
-#endif
- }
-
- /**
- * Note from pico datasheet 4.1.2.6.4 (v1.2)
- * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when
- * the device is first connected but the bus is idle. The bus can be idle for a few ms before
- * the host begins sending start of frame packets. You will also see a suspend interrupt
- * when the device is disconnected if you do not have a VBUS detect circuit connected. This is
- * because without VBUS detection, it is impossible to tell the difference between
- * being disconnected and suspended.
- */
- if (status & USB_INTS_DEV_SUSPEND_BITS) {
- handled |= USB_INTS_DEV_SUSPEND_BITS;
- /*!< Suspend */
- usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS;
- }
-
- if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS) {
- handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS;
- /*!< Resume */
- usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
- }
-
- if (status ^ handled) {
- USB_LOG_INFO("Unhandled IRQ 0x%x\n", (uint32_t)(status ^ handled));
- }
-}
diff --git a/port/rp2040/usb_rp2040_reg.h b/port/rp2040/usb_rp2040_reg.h
deleted file mode 100644
index dea98659..00000000
--- a/port/rp2040/usb_rp2040_reg.h
+++ /dev/null
@@ -1,4350 +0,0 @@
-#pragma once
-#include <stdint.h>
-
-#if defined(__GNUC__) && (__GNUC__ <= 6 || (__GNUC__ == 7 && (__GNUC_MINOR__ < 3 || !defined(__cplusplus))))
-#ifndef __force_inline
-#define __force_inline inline __always_inline
-#endif
-#else
-#ifndef __force_inline
-#define __force_inline __always_inline
-#endif
-#endif
-
-// 0-15
-#define USB_NUM_ENDPOINTS 16
-// 1-15
-#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1)
-
-// ep_inout_ctrl bits
-#define EP_CTRL_ENABLE_BITS (1u << 31u)
-#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30)
-#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29)
-#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
-#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
-#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
-#define EP_CTRL_BUFFER_TYPE_LSB 26u
-#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
-
-// Endpoint buffer control bits
-#define USB_BUF_CTRL_FULL 0x00008000u
-#define USB_BUF_CTRL_LAST 0x00004000u
-#define USB_BUF_CTRL_DATA0_PID 0x00000000u
-#define USB_BUF_CTRL_DATA1_PID 0x00002000u
-#define USB_BUF_CTRL_SEL 0x00001000u
-#define USB_BUF_CTRL_STALL 0x00000800u
-#define USB_BUF_CTRL_AVAIL 0x00000400u
-#define USB_BUF_CTRL_LEN_MASK 0x000003FFu
-#define USB_BUF_CTRL_LEN_LSB 0
-
-#define USB_DPRAM_SIZE 4096u
-// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
-// Allow user to claim some of the USB RAM for themselves
-#ifndef USB_DPRAM_MAX
-#define USB_DPRAM_MAX USB_DPRAM_SIZE
-#endif
-
-#define _REG_(x)
-#ifndef _u
-#define _u(x) x##u
-#endif
-typedef volatile uint32_t io_rw_32;
-typedef volatile uint32_t io_wo_32;
-typedef const volatile uint32_t io_ro_32;
-
-// =============================================================================
-// Register : RESETS_RESET
-// Description : Reset control. If a bit is set it means the peripheral is in
-// reset. 0 means the peripheral's reset is deasserted.
-#define RESETS_RESET_OFFSET _u(0x00000000)
-#define RESETS_RESET_BITS _u(0x01ffffff)
-#define RESETS_RESET_RESET _u(0x01ffffff)
-// =============================================================================
-// Register : RESETS_WDSEL
-// Description : Watchdog select. If a bit is set then the watchdog will reset
-// this peripheral when the watchdog fires.
-#define RESETS_WDSEL_OFFSET _u(0x00000004)
-#define RESETS_WDSEL_BITS _u(0x01ffffff)
-#define RESETS_WDSEL_RESET _u(0x00000000)
-// =============================================================================
-// Register : RESETS_RESET_DONE
-// Description : Reset done. If a bit is set then a reset done signal has been
-// returned by the peripheral. This indicates that the
-// peripheral's registers are ready to be accessed.
-#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
-#define RESETS_RESET_DONE_BITS _u(0x01ffffff)
-#define RESETS_RESET_DONE_RESET _u(0x00000000)
-
-// -----------------------------------------------------------------------------
-// Field : RESETS_RESET_USBCTRL
-// Description : None
-#define RESETS_RESET_USBCTRL_RESET _u(0x1)
-#define RESETS_RESET_USBCTRL_BITS _u(0x01000000)
-#define RESETS_RESET_USBCTRL_MSB _u(24)
-#define RESETS_RESET_USBCTRL_LSB _u(24)
-#define RESETS_RESET_USBCTRL_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP
-// Description : Device address and endpoint control
-#define USB_ADDR_ENDP_OFFSET _u(0x00000000)
-#define USB_ADDR_ENDP_BITS _u(0x000f007f)
-#define USB_ADDR_ENDP_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP_ENDPOINT
-// Description : Device endpoint to send data to. Only valid for HOST mode.
-#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP_ADDRESS
-// Description : In device mode, the address that the device should respond to.
-// Set in response to a SET_ADDR setup packet from the host. In
-// host mode set to the address of the device to communicate with.
-#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP1
-// Description : Interrupt endpoint 1. Only valid for HOST mode.
-#define USB_ADDR_ENDP1_OFFSET _u(0x00000004)
-#define USB_ADDR_ENDP1_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP1_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP1_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP1_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP1_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP2
-// Description : Interrupt endpoint 2. Only valid for HOST mode.
-#define USB_ADDR_ENDP2_OFFSET _u(0x00000008)
-#define USB_ADDR_ENDP2_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP2_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP2_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP2_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP2_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP3
-// Description : Interrupt endpoint 3. Only valid for HOST mode.
-#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c)
-#define USB_ADDR_ENDP3_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP3_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP3_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP3_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP3_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP4
-// Description : Interrupt endpoint 4. Only valid for HOST mode.
-#define USB_ADDR_ENDP4_OFFSET _u(0x00000010)
-#define USB_ADDR_ENDP4_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP4_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP4_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP4_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP4_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP5
-// Description : Interrupt endpoint 5. Only valid for HOST mode.
-#define USB_ADDR_ENDP5_OFFSET _u(0x00000014)
-#define USB_ADDR_ENDP5_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP5_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP5_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP5_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP5_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP6
-// Description : Interrupt endpoint 6. Only valid for HOST mode.
-#define USB_ADDR_ENDP6_OFFSET _u(0x00000018)
-#define USB_ADDR_ENDP6_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP6_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP6_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP6_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP6_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP7
-// Description : Interrupt endpoint 7. Only valid for HOST mode.
-#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c)
-#define USB_ADDR_ENDP7_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP7_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP7_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP7_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP7_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP8
-// Description : Interrupt endpoint 8. Only valid for HOST mode.
-#define USB_ADDR_ENDP8_OFFSET _u(0x00000020)
-#define USB_ADDR_ENDP8_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP8_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP8_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP8_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP8_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP9
-// Description : Interrupt endpoint 9. Only valid for HOST mode.
-#define USB_ADDR_ENDP9_OFFSET _u(0x00000024)
-#define USB_ADDR_ENDP9_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP9_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP9_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP9_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP9_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP10
-// Description : Interrupt endpoint 10. Only valid for HOST mode.
-#define USB_ADDR_ENDP10_OFFSET _u(0x00000028)
-#define USB_ADDR_ENDP10_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP10_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP10_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP10_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP10_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP11
-// Description : Interrupt endpoint 11. Only valid for HOST mode.
-#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c)
-#define USB_ADDR_ENDP11_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP11_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP11_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP11_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP11_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP12
-// Description : Interrupt endpoint 12. Only valid for HOST mode.
-#define USB_ADDR_ENDP12_OFFSET _u(0x00000030)
-#define USB_ADDR_ENDP12_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP12_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP12_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP12_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP12_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP13
-// Description : Interrupt endpoint 13. Only valid for HOST mode.
-#define USB_ADDR_ENDP13_OFFSET _u(0x00000034)
-#define USB_ADDR_ENDP13_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP13_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP13_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP13_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP13_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP14
-// Description : Interrupt endpoint 14. Only valid for HOST mode.
-#define USB_ADDR_ENDP14_OFFSET _u(0x00000038)
-#define USB_ADDR_ENDP14_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP14_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP14_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP14_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP14_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_ADDR_ENDP15
-// Description : Interrupt endpoint 15. Only valid for HOST mode.
-#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c)
-#define USB_ADDR_ENDP15_BITS _u(0x060f007f)
-#define USB_ADDR_ENDP15_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE
-// Description : Interrupt EP requires preamble (is a low speed device on a full
-// speed hub)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26)
-#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP15_INTEP_DIR
-// Description : Direction of the interrupt endpoint. In=0, Out=1
-#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0)
-#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000)
-#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25)
-#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25)
-#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP15_ENDPOINT
-// Description : Endpoint number of the interrupt endpoint
-#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0)
-#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000)
-#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19)
-#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16)
-#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_ADDR_ENDP15_ADDRESS
-// Description : Device address
-#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00)
-#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f)
-#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6)
-#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0)
-#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW"
-// =============================================================================
-// Register : USB_MAIN_CTRL
-// Description : Main control register
-#define USB_MAIN_CTRL_OFFSET _u(0x00000040)
-#define USB_MAIN_CTRL_BITS _u(0x80000003)
-#define USB_MAIN_CTRL_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_MAIN_CTRL_SIM_TIMING
-// Description : Reduced timings for simulation
-#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0)
-#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000)
-#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31)
-#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31)
-#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_MAIN_CTRL_HOST_NDEVICE
-// Description : Device mode = 0, Host mode = 1
-#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0)
-#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002)
-#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1)
-#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1)
-#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_MAIN_CTRL_CONTROLLER_EN
-// Description : Enable controller
-#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0)
-#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001)
-#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0)
-#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0)
-#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW"
-// =============================================================================
-// Register : USB_SOF_WR
-// Description : Set the SOF (Start of Frame) frame number in the host
-// controller. The SOF packet is sent every 1ms and the host will
-// increment the frame number by 1 each time.
-#define USB_SOF_WR_OFFSET _u(0x00000044)
-#define USB_SOF_WR_BITS _u(0x000007ff)
-#define USB_SOF_WR_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_SOF_WR_COUNT
-// Description : None
-#define USB_SOF_WR_COUNT_RESET _u(0x000)
-#define USB_SOF_WR_COUNT_BITS _u(0x000007ff)
-#define USB_SOF_WR_COUNT_MSB _u(10)
-#define USB_SOF_WR_COUNT_LSB _u(0)
-#define USB_SOF_WR_COUNT_ACCESS "WF"
-// =============================================================================
-// Register : USB_SOF_RD
-// Description : Read the last SOF (Start of Frame) frame number seen. In device
-// mode the last SOF received from the host. In host mode the last
-// SOF sent by the host.
-#define USB_SOF_RD_OFFSET _u(0x00000048)
-#define USB_SOF_RD_BITS _u(0x000007ff)
-#define USB_SOF_RD_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_SOF_RD_COUNT
-// Description : None
-#define USB_SOF_RD_COUNT_RESET _u(0x000)
-#define USB_SOF_RD_COUNT_BITS _u(0x000007ff)
-#define USB_SOF_RD_COUNT_MSB _u(10)
-#define USB_SOF_RD_COUNT_LSB _u(0)
-#define USB_SOF_RD_COUNT_ACCESS "RO"
-// =============================================================================
-// Register : USB_SIE_CTRL
-// Description : SIE control register
-#define USB_SIE_CTRL_OFFSET _u(0x0000004c)
-#define USB_SIE_CTRL_BITS _u(0xff07bf5f)
-#define USB_SIE_CTRL_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_EP0_INT_STALL
-// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
-#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0)
-#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000)
-#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31)
-#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31)
-#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF
-// Description : Device: EP0 single buffered = 0, double buffered = 1
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0)
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000)
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30)
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30)
-#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_EP0_INT_1BUF
-// Description : Device: Set bit in BUFF_STATUS for every buffer completed on
-// EP0
-#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0)
-#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000)
-#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29)
-#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29)
-#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_EP0_INT_2BUF
-// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on
-// EP0
-#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0)
-#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000)
-#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28)
-#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28)
-#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_EP0_INT_NAK
-// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
-#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0)
-#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000)
-#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27)
-#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27)
-#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_DIRECT_EN
-// Description : Direct bus drive enable
-#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0)
-#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000)
-#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26)
-#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26)
-#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_DIRECT_DP
-// Description : Direct control of DP
-#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0)
-#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000)
-#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25)
-#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25)
-#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_DIRECT_DM
-// Description : Direct control of DM
-#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0)
-#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000)
-#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24)
-#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24)
-#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_TRANSCEIVER_PD
-// Description : Power down bus transceiver
-#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0)
-#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000)
-#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18)
-#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18)
-#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_RPU_OPT
-// Description : Device: Pull-up strength (0=1K2, 1=2k3)
-#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0)
-#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000)
-#define USB_SIE_CTRL_RPU_OPT_MSB _u(17)
-#define USB_SIE_CTRL_RPU_OPT_LSB _u(17)
-#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_PULLUP_EN
-// Description : Device: Enable pull up resistor
-#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0)
-#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000)
-#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16)
-#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16)
-#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_PULLDOWN_EN
-// Description : Host: Enable pull down resistors
-#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x0)
-#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000)
-#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15)
-#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15)
-#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_RESET_BUS
-// Description : Host: Reset bus
-#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0)
-#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000)
-#define USB_SIE_CTRL_RESET_BUS_MSB _u(13)
-#define USB_SIE_CTRL_RESET_BUS_LSB _u(13)
-#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_RESUME
-// Description : Device: Remote wakeup. Device can initiate its own resume after
-// suspend.
-#define USB_SIE_CTRL_RESUME_RESET _u(0x0)
-#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000)
-#define USB_SIE_CTRL_RESUME_MSB _u(12)
-#define USB_SIE_CTRL_RESUME_LSB _u(12)
-#define USB_SIE_CTRL_RESUME_ACCESS "SC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_VBUS_EN
-// Description : Host: Enable VBUS
-#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0)
-#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800)
-#define USB_SIE_CTRL_VBUS_EN_MSB _u(11)
-#define USB_SIE_CTRL_VBUS_EN_LSB _u(11)
-#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_KEEP_ALIVE_EN
-// Description : Host: Enable keep alive packet (for low speed bus)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10)
-#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_SOF_EN
-// Description : Host: Enable SOF generation (for full speed bus)
-#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0)
-#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200)
-#define USB_SIE_CTRL_SOF_EN_MSB _u(9)
-#define USB_SIE_CTRL_SOF_EN_LSB _u(9)
-#define USB_SIE_CTRL_SOF_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_SOF_SYNC
-// Description : Host: Delay packet(s) until after SOF
-#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0)
-#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100)
-#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8)
-#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8)
-#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_PREAMBLE_EN
-// Description : Host: Preable enable for LS device on FS hub
-#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0)
-#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040)
-#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6)
-#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6)
-#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_STOP_TRANS
-// Description : Host: Stop transaction
-#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0)
-#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010)
-#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4)
-#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4)
-#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_RECEIVE_DATA
-// Description : Host: Receive transaction (IN to host)
-#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0)
-#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008)
-#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3)
-#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3)
-#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_SEND_DATA
-// Description : Host: Send transaction (OUT from host)
-#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0)
-#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004)
-#define USB_SIE_CTRL_SEND_DATA_MSB _u(2)
-#define USB_SIE_CTRL_SEND_DATA_LSB _u(2)
-#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_SEND_SETUP
-// Description : Host: Send Setup packet
-#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0)
-#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002)
-#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1)
-#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1)
-#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_CTRL_START_TRANS
-// Description : Host: Start transaction
-#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0)
-#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001)
-#define USB_SIE_CTRL_START_TRANS_MSB _u(0)
-#define USB_SIE_CTRL_START_TRANS_LSB _u(0)
-#define USB_SIE_CTRL_START_TRANS_ACCESS "SC"
-// =============================================================================
-// Register : USB_SIE_STATUS
-// Description : SIE status register
-#define USB_SIE_STATUS_OFFSET _u(0x00000050)
-#define USB_SIE_STATUS_BITS _u(0xff0f0f1d)
-#define USB_SIE_STATUS_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_DATA_SEQ_ERROR
-// Description : Data Sequence Error.
-//
-// The device can raise a sequence error in the following
-// conditions:
-//
-// * A SETUP packet is received followed by a DATA1 packet (data
-// phase should always be DATA0) * An OUT packet is received from
-// the host but doesn't match the data pid in the buffer control
-// register read from DPSRAM
-//
-// The host can raise a data sequence error in the following
-// conditions:
-//
-// * An IN packet from the device has the wrong data PID
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0)
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000)
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31)
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31)
-#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_ACK_REC
-// Description : ACK received. Raised by both host and device.
-#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0)
-#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000)
-#define USB_SIE_STATUS_ACK_REC_MSB _u(30)
-#define USB_SIE_STATUS_ACK_REC_LSB _u(30)
-#define USB_SIE_STATUS_ACK_REC_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_STALL_REC
-// Description : Host: STALL received
-#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0)
-#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000)
-#define USB_SIE_STATUS_STALL_REC_MSB _u(29)
-#define USB_SIE_STATUS_STALL_REC_LSB _u(29)
-#define USB_SIE_STATUS_STALL_REC_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_NAK_REC
-// Description : Host: NAK received
-#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0)
-#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000)
-#define USB_SIE_STATUS_NAK_REC_MSB _u(28)
-#define USB_SIE_STATUS_NAK_REC_LSB _u(28)
-#define USB_SIE_STATUS_NAK_REC_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_RX_TIMEOUT
-// Description : RX timeout is raised by both the host and device if an ACK is
-// not received in the maximum time specified by the USB spec.
-#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0)
-#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000)
-#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27)
-#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27)
-#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_RX_OVERFLOW
-// Description : RX overflow is raised by the Serial RX engine if the incoming
-// data is too fast.
-#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0)
-#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000)
-#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26)
-#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26)
-#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_BIT_STUFF_ERROR
-// Description : Bit Stuff Error. Raised by the Serial RX engine.
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0)
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000)
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25)
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25)
-#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_CRC_ERROR
-// Description : CRC Error. Raised by the Serial RX engine.
-#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0)
-#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000)
-#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24)
-#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24)
-#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_BUS_RESET
-// Description : Device: bus reset received
-#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0)
-#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000)
-#define USB_SIE_STATUS_BUS_RESET_MSB _u(19)
-#define USB_SIE_STATUS_BUS_RESET_LSB _u(19)
-#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_TRANS_COMPLETE
-// Description : Transaction complete.
-//
-// Raised by device if:
-//
-// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in
-// the buffer control register
-//
-// Raised by host if:
-//
-// * A setup packet is sent when no data in or data out
-// transaction follows * An IN packet is received and the
-// `LAST_BUFF` bit is set in the buffer control register * An IN
-// packet is received with zero length * An OUT packet is sent and
-// the `LAST_BUFF` bit is set
-#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0)
-#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000)
-#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18)
-#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18)
-#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_SETUP_REC
-// Description : Device: Setup packet received
-#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0)
-#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000)
-#define USB_SIE_STATUS_SETUP_REC_MSB _u(17)
-#define USB_SIE_STATUS_SETUP_REC_LSB _u(17)
-#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_CONNECTED
-// Description : Device: connected
-#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0)
-#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000)
-#define USB_SIE_STATUS_CONNECTED_MSB _u(16)
-#define USB_SIE_STATUS_CONNECTED_LSB _u(16)
-#define USB_SIE_STATUS_CONNECTED_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_RESUME
-// Description : Host: Device has initiated a remote resume. Device: host has
-// initiated a resume.
-#define USB_SIE_STATUS_RESUME_RESET _u(0x0)
-#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800)
-#define USB_SIE_STATUS_RESUME_MSB _u(11)
-#define USB_SIE_STATUS_RESUME_LSB _u(11)
-#define USB_SIE_STATUS_RESUME_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_VBUS_OVER_CURR
-// Description : VBUS over current detected
-#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0)
-#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400)
-#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10)
-#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10)
-#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_SPEED
-// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10
-#define USB_SIE_STATUS_SPEED_RESET _u(0x0)
-#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300)
-#define USB_SIE_STATUS_SPEED_MSB _u(9)
-#define USB_SIE_STATUS_SPEED_LSB _u(8)
-#define USB_SIE_STATUS_SPEED_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_SUSPENDED
-// Description : Bus in suspended state. Valid for device and host. Host and
-// device will go into suspend if neither Keep Alive / SOF frames
-// are enabled.
-#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0)
-#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010)
-#define USB_SIE_STATUS_SUSPENDED_MSB _u(4)
-#define USB_SIE_STATUS_SUSPENDED_LSB _u(4)
-#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_LINE_STATE
-// Description : USB bus line state
-#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0)
-#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c)
-#define USB_SIE_STATUS_LINE_STATE_MSB _u(3)
-#define USB_SIE_STATUS_LINE_STATE_LSB _u(2)
-#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_SIE_STATUS_VBUS_DETECTED
-// Description : Device: VBUS Detected
-#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0)
-#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001)
-#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0)
-#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0)
-#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO"
-// =============================================================================
-// Register : USB_INT_EP_CTRL
-// Description : interrupt endpoint control register
-#define USB_INT_EP_CTRL_OFFSET _u(0x00000054)
-#define USB_INT_EP_CTRL_BITS _u(0x0000fffe)
-#define USB_INT_EP_CTRL_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE
-// Description : Host: Enable interrupt endpoint 1 -> 15
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000)
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe)
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15)
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1)
-#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW"
-// =============================================================================
-// Register : USB_BUFF_STATUS
-// Description : Buffer status register. A bit set here indicates that a buffer
-// has completed on the endpoint (if the buffer interrupt is
-// enabled). It is possible for 2 buffers to be completed, so
-// clearing the buffer status bit may instantly re set it on the
-// next clock cycle.
-#define USB_BUFF_STATUS_OFFSET _u(0x00000058)
-#define USB_BUFF_STATUS_BITS _u(0xffffffff)
-#define USB_BUFF_STATUS_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP15_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000)
-#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31)
-#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31)
-#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP15_IN
-// Description : None
-#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000)
-#define USB_BUFF_STATUS_EP15_IN_MSB _u(30)
-#define USB_BUFF_STATUS_EP15_IN_LSB _u(30)
-#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP14_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000)
-#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29)
-#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29)
-#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP14_IN
-// Description : None
-#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000)
-#define USB_BUFF_STATUS_EP14_IN_MSB _u(28)
-#define USB_BUFF_STATUS_EP14_IN_LSB _u(28)
-#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP13_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000)
-#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27)
-#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27)
-#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP13_IN
-// Description : None
-#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000)
-#define USB_BUFF_STATUS_EP13_IN_MSB _u(26)
-#define USB_BUFF_STATUS_EP13_IN_LSB _u(26)
-#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP12_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000)
-#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25)
-#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25)
-#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP12_IN
-// Description : None
-#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000)
-#define USB_BUFF_STATUS_EP12_IN_MSB _u(24)
-#define USB_BUFF_STATUS_EP12_IN_LSB _u(24)
-#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP11_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000)
-#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23)
-#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23)
-#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP11_IN
-// Description : None
-#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000)
-#define USB_BUFF_STATUS_EP11_IN_MSB _u(22)
-#define USB_BUFF_STATUS_EP11_IN_LSB _u(22)
-#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP10_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000)
-#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21)
-#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21)
-#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP10_IN
-// Description : None
-#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000)
-#define USB_BUFF_STATUS_EP10_IN_MSB _u(20)
-#define USB_BUFF_STATUS_EP10_IN_LSB _u(20)
-#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP9_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000)
-#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19)
-#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19)
-#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP9_IN
-// Description : None
-#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000)
-#define USB_BUFF_STATUS_EP9_IN_MSB _u(18)
-#define USB_BUFF_STATUS_EP9_IN_LSB _u(18)
-#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP8_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000)
-#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17)
-#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17)
-#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP8_IN
-// Description : None
-#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000)
-#define USB_BUFF_STATUS_EP8_IN_MSB _u(16)
-#define USB_BUFF_STATUS_EP8_IN_LSB _u(16)
-#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP7_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000)
-#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15)
-#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15)
-#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP7_IN
-// Description : None
-#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000)
-#define USB_BUFF_STATUS_EP7_IN_MSB _u(14)
-#define USB_BUFF_STATUS_EP7_IN_LSB _u(14)
-#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP6_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000)
-#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13)
-#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13)
-#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP6_IN
-// Description : None
-#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000)
-#define USB_BUFF_STATUS_EP6_IN_MSB _u(12)
-#define USB_BUFF_STATUS_EP6_IN_LSB _u(12)
-#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP5_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800)
-#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11)
-#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11)
-#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP5_IN
-// Description : None
-#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400)
-#define USB_BUFF_STATUS_EP5_IN_MSB _u(10)
-#define USB_BUFF_STATUS_EP5_IN_LSB _u(10)
-#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP4_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200)
-#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9)
-#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9)
-#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP4_IN
-// Description : None
-#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100)
-#define USB_BUFF_STATUS_EP4_IN_MSB _u(8)
-#define USB_BUFF_STATUS_EP4_IN_LSB _u(8)
-#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP3_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080)
-#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7)
-#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7)
-#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP3_IN
-// Description : None
-#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040)
-#define USB_BUFF_STATUS_EP3_IN_MSB _u(6)
-#define USB_BUFF_STATUS_EP3_IN_LSB _u(6)
-#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP2_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020)
-#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5)
-#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5)
-#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP2_IN
-// Description : None
-#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010)
-#define USB_BUFF_STATUS_EP2_IN_MSB _u(4)
-#define USB_BUFF_STATUS_EP2_IN_LSB _u(4)
-#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP1_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008)
-#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3)
-#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3)
-#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP1_IN
-// Description : None
-#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004)
-#define USB_BUFF_STATUS_EP1_IN_MSB _u(2)
-#define USB_BUFF_STATUS_EP1_IN_LSB _u(2)
-#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP0_OUT
-// Description : None
-#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002)
-#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1)
-#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1)
-#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_STATUS_EP0_IN
-// Description : None
-#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0)
-#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001)
-#define USB_BUFF_STATUS_EP0_IN_MSB _u(0)
-#define USB_BUFF_STATUS_EP0_IN_LSB _u(0)
-#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC"
-// =============================================================================
-// Register : USB_BUFF_CPU_SHOULD_HANDLE
-// Description : Which of the double buffers should be handled. Only valid if
-// using an interrupt per buffer (i.e. not per 2 buffers). Not
-// valid for host interrupt endpoint polling because they are only
-// single buffered.
-#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c)
-#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff)
-#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN
-// Description : None
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0)
-#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO"
-// =============================================================================
-// Register : USB_EP_ABORT
-// Description : Device only: Can be set to ignore the buffer control register
-// for this endpoint in case you would like to revoke a buffer. A
-// NAK will be sent for every access to the endpoint until this
-// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set
-// when it is safe to modify the buffer control register.
-#define USB_EP_ABORT_OFFSET _u(0x00000060)
-#define USB_EP_ABORT_BITS _u(0xffffffff)
-#define USB_EP_ABORT_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP15_OUT
-// Description : None
-#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000)
-#define USB_EP_ABORT_EP15_OUT_MSB _u(31)
-#define USB_EP_ABORT_EP15_OUT_LSB _u(31)
-#define USB_EP_ABORT_EP15_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP15_IN
-// Description : None
-#define USB_EP_ABORT_EP15_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000)
-#define USB_EP_ABORT_EP15_IN_MSB _u(30)
-#define USB_EP_ABORT_EP15_IN_LSB _u(30)
-#define USB_EP_ABORT_EP15_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP14_OUT
-// Description : None
-#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000)
-#define USB_EP_ABORT_EP14_OUT_MSB _u(29)
-#define USB_EP_ABORT_EP14_OUT_LSB _u(29)
-#define USB_EP_ABORT_EP14_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP14_IN
-// Description : None
-#define USB_EP_ABORT_EP14_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000)
-#define USB_EP_ABORT_EP14_IN_MSB _u(28)
-#define USB_EP_ABORT_EP14_IN_LSB _u(28)
-#define USB_EP_ABORT_EP14_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP13_OUT
-// Description : None
-#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000)
-#define USB_EP_ABORT_EP13_OUT_MSB _u(27)
-#define USB_EP_ABORT_EP13_OUT_LSB _u(27)
-#define USB_EP_ABORT_EP13_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP13_IN
-// Description : None
-#define USB_EP_ABORT_EP13_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000)
-#define USB_EP_ABORT_EP13_IN_MSB _u(26)
-#define USB_EP_ABORT_EP13_IN_LSB _u(26)
-#define USB_EP_ABORT_EP13_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP12_OUT
-// Description : None
-#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000)
-#define USB_EP_ABORT_EP12_OUT_MSB _u(25)
-#define USB_EP_ABORT_EP12_OUT_LSB _u(25)
-#define USB_EP_ABORT_EP12_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP12_IN
-// Description : None
-#define USB_EP_ABORT_EP12_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000)
-#define USB_EP_ABORT_EP12_IN_MSB _u(24)
-#define USB_EP_ABORT_EP12_IN_LSB _u(24)
-#define USB_EP_ABORT_EP12_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP11_OUT
-// Description : None
-#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000)
-#define USB_EP_ABORT_EP11_OUT_MSB _u(23)
-#define USB_EP_ABORT_EP11_OUT_LSB _u(23)
-#define USB_EP_ABORT_EP11_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP11_IN
-// Description : None
-#define USB_EP_ABORT_EP11_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000)
-#define USB_EP_ABORT_EP11_IN_MSB _u(22)
-#define USB_EP_ABORT_EP11_IN_LSB _u(22)
-#define USB_EP_ABORT_EP11_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP10_OUT
-// Description : None
-#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000)
-#define USB_EP_ABORT_EP10_OUT_MSB _u(21)
-#define USB_EP_ABORT_EP10_OUT_LSB _u(21)
-#define USB_EP_ABORT_EP10_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP10_IN
-// Description : None
-#define USB_EP_ABORT_EP10_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000)
-#define USB_EP_ABORT_EP10_IN_MSB _u(20)
-#define USB_EP_ABORT_EP10_IN_LSB _u(20)
-#define USB_EP_ABORT_EP10_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP9_OUT
-// Description : None
-#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000)
-#define USB_EP_ABORT_EP9_OUT_MSB _u(19)
-#define USB_EP_ABORT_EP9_OUT_LSB _u(19)
-#define USB_EP_ABORT_EP9_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP9_IN
-// Description : None
-#define USB_EP_ABORT_EP9_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000)
-#define USB_EP_ABORT_EP9_IN_MSB _u(18)
-#define USB_EP_ABORT_EP9_IN_LSB _u(18)
-#define USB_EP_ABORT_EP9_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP8_OUT
-// Description : None
-#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000)
-#define USB_EP_ABORT_EP8_OUT_MSB _u(17)
-#define USB_EP_ABORT_EP8_OUT_LSB _u(17)
-#define USB_EP_ABORT_EP8_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP8_IN
-// Description : None
-#define USB_EP_ABORT_EP8_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000)
-#define USB_EP_ABORT_EP8_IN_MSB _u(16)
-#define USB_EP_ABORT_EP8_IN_LSB _u(16)
-#define USB_EP_ABORT_EP8_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP7_OUT
-// Description : None
-#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000)
-#define USB_EP_ABORT_EP7_OUT_MSB _u(15)
-#define USB_EP_ABORT_EP7_OUT_LSB _u(15)
-#define USB_EP_ABORT_EP7_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP7_IN
-// Description : None
-#define USB_EP_ABORT_EP7_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000)
-#define USB_EP_ABORT_EP7_IN_MSB _u(14)
-#define USB_EP_ABORT_EP7_IN_LSB _u(14)
-#define USB_EP_ABORT_EP7_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP6_OUT
-// Description : None
-#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000)
-#define USB_EP_ABORT_EP6_OUT_MSB _u(13)
-#define USB_EP_ABORT_EP6_OUT_LSB _u(13)
-#define USB_EP_ABORT_EP6_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP6_IN
-// Description : None
-#define USB_EP_ABORT_EP6_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000)
-#define USB_EP_ABORT_EP6_IN_MSB _u(12)
-#define USB_EP_ABORT_EP6_IN_LSB _u(12)
-#define USB_EP_ABORT_EP6_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP5_OUT
-// Description : None
-#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800)
-#define USB_EP_ABORT_EP5_OUT_MSB _u(11)
-#define USB_EP_ABORT_EP5_OUT_LSB _u(11)
-#define USB_EP_ABORT_EP5_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP5_IN
-// Description : None
-#define USB_EP_ABORT_EP5_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400)
-#define USB_EP_ABORT_EP5_IN_MSB _u(10)
-#define USB_EP_ABORT_EP5_IN_LSB _u(10)
-#define USB_EP_ABORT_EP5_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP4_OUT
-// Description : None
-#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200)
-#define USB_EP_ABORT_EP4_OUT_MSB _u(9)
-#define USB_EP_ABORT_EP4_OUT_LSB _u(9)
-#define USB_EP_ABORT_EP4_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP4_IN
-// Description : None
-#define USB_EP_ABORT_EP4_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100)
-#define USB_EP_ABORT_EP4_IN_MSB _u(8)
-#define USB_EP_ABORT_EP4_IN_LSB _u(8)
-#define USB_EP_ABORT_EP4_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP3_OUT
-// Description : None
-#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080)
-#define USB_EP_ABORT_EP3_OUT_MSB _u(7)
-#define USB_EP_ABORT_EP3_OUT_LSB _u(7)
-#define USB_EP_ABORT_EP3_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP3_IN
-// Description : None
-#define USB_EP_ABORT_EP3_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040)
-#define USB_EP_ABORT_EP3_IN_MSB _u(6)
-#define USB_EP_ABORT_EP3_IN_LSB _u(6)
-#define USB_EP_ABORT_EP3_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP2_OUT
-// Description : None
-#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020)
-#define USB_EP_ABORT_EP2_OUT_MSB _u(5)
-#define USB_EP_ABORT_EP2_OUT_LSB _u(5)
-#define USB_EP_ABORT_EP2_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP2_IN
-// Description : None
-#define USB_EP_ABORT_EP2_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010)
-#define USB_EP_ABORT_EP2_IN_MSB _u(4)
-#define USB_EP_ABORT_EP2_IN_LSB _u(4)
-#define USB_EP_ABORT_EP2_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP1_OUT
-// Description : None
-#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008)
-#define USB_EP_ABORT_EP1_OUT_MSB _u(3)
-#define USB_EP_ABORT_EP1_OUT_LSB _u(3)
-#define USB_EP_ABORT_EP1_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP1_IN
-// Description : None
-#define USB_EP_ABORT_EP1_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004)
-#define USB_EP_ABORT_EP1_IN_MSB _u(2)
-#define USB_EP_ABORT_EP1_IN_LSB _u(2)
-#define USB_EP_ABORT_EP1_IN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP0_OUT
-// Description : None
-#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002)
-#define USB_EP_ABORT_EP0_OUT_MSB _u(1)
-#define USB_EP_ABORT_EP0_OUT_LSB _u(1)
-#define USB_EP_ABORT_EP0_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_EP0_IN
-// Description : None
-#define USB_EP_ABORT_EP0_IN_RESET _u(0x0)
-#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001)
-#define USB_EP_ABORT_EP0_IN_MSB _u(0)
-#define USB_EP_ABORT_EP0_IN_LSB _u(0)
-#define USB_EP_ABORT_EP0_IN_ACCESS "RW"
-// =============================================================================
-// Register : USB_EP_ABORT_DONE
-// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an
-// endpoint is idle so the programmer knows it is safe to modify
-// the buffer control register.
-#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064)
-#define USB_EP_ABORT_DONE_BITS _u(0xffffffff)
-#define USB_EP_ABORT_DONE_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP15_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000)
-#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31)
-#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31)
-#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP15_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000)
-#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30)
-#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30)
-#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP14_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000)
-#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29)
-#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29)
-#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP14_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000)
-#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28)
-#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28)
-#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP13_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000)
-#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27)
-#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27)
-#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP13_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000)
-#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26)
-#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26)
-#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP12_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000)
-#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25)
-#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25)
-#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP12_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000)
-#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24)
-#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24)
-#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP11_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000)
-#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23)
-#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23)
-#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP11_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000)
-#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22)
-#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22)
-#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP10_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000)
-#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21)
-#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21)
-#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP10_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000)
-#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20)
-#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20)
-#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP9_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000)
-#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19)
-#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19)
-#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP9_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000)
-#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18)
-#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18)
-#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP8_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000)
-#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17)
-#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17)
-#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP8_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000)
-#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16)
-#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16)
-#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP7_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000)
-#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15)
-#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15)
-#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP7_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000)
-#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14)
-#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14)
-#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP6_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000)
-#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13)
-#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13)
-#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP6_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000)
-#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12)
-#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12)
-#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP5_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800)
-#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11)
-#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11)
-#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP5_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400)
-#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10)
-#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10)
-#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP4_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200)
-#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9)
-#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9)
-#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP4_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100)
-#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8)
-#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8)
-#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP3_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080)
-#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7)
-#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7)
-#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP3_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040)
-#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6)
-#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6)
-#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP2_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020)
-#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5)
-#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5)
-#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP2_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010)
-#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4)
-#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4)
-#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP1_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008)
-#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3)
-#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3)
-#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP1_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004)
-#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2)
-#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2)
-#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP0_OUT
-// Description : None
-#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002)
-#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1)
-#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1)
-#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_ABORT_DONE_EP0_IN
-// Description : None
-#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0)
-#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001)
-#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0)
-#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0)
-#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC"
-// =============================================================================
-// Register : USB_EP_STALL_ARM
-// Description : Device: this bit must be set in conjunction with the `STALL`
-// bit in the buffer control register to send a STALL on EP0. The
-// device controller clears these bits when a SETUP packet is
-// received because the USB spec requires that a STALL condition
-// is cleared when a SETUP packet is received.
-#define USB_EP_STALL_ARM_OFFSET _u(0x00000068)
-#define USB_EP_STALL_ARM_BITS _u(0x00000003)
-#define USB_EP_STALL_ARM_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STALL_ARM_EP0_OUT
-// Description : None
-#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0)
-#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002)
-#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1)
-#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1)
-#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STALL_ARM_EP0_IN
-// Description : None
-#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0)
-#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001)
-#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0)
-#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0)
-#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW"
-// =============================================================================
-// Register : USB_NAK_POLL
-// Description : Used by the host controller. Sets the wait time in microseconds
-// before trying again if the device replies with a NAK.
-#define USB_NAK_POLL_OFFSET _u(0x0000006c)
-#define USB_NAK_POLL_BITS _u(0x03ff03ff)
-#define USB_NAK_POLL_RESET _u(0x00100010)
-// -----------------------------------------------------------------------------
-// Field : USB_NAK_POLL_DELAY_FS
-// Description : NAK polling interval for a full speed device
-#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010)
-#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000)
-#define USB_NAK_POLL_DELAY_FS_MSB _u(25)
-#define USB_NAK_POLL_DELAY_FS_LSB _u(16)
-#define USB_NAK_POLL_DELAY_FS_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_NAK_POLL_DELAY_LS
-// Description : NAK polling interval for a low speed device
-#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010)
-#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff)
-#define USB_NAK_POLL_DELAY_LS_MSB _u(9)
-#define USB_NAK_POLL_DELAY_LS_LSB _u(0)
-#define USB_NAK_POLL_DELAY_LS_ACCESS "RW"
-// =============================================================================
-// Register : USB_EP_STATUS_STALL_NAK
-// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL`
-// bits are set. For EP0 this comes from `SIE_CTRL`. For all other
-// endpoints it comes from the endpoint control register.
-#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070)
-#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff)
-#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000)
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31)
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31)
-#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP15_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000)
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30)
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30)
-#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000)
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29)
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29)
-#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP14_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000)
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28)
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28)
-#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000)
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27)
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27)
-#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP13_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000)
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26)
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26)
-#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000)
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25)
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25)
-#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP12_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000)
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24)
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24)
-#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000)
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23)
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23)
-#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP11_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000)
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22)
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22)
-#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000)
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21)
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21)
-#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP10_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000)
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20)
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20)
-#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000)
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19)
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19)
-#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP9_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000)
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18)
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18)
-#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000)
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17)
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17)
-#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP8_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000)
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16)
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16)
-#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000)
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15)
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15)
-#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP7_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000)
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14)
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14)
-#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000)
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13)
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13)
-#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP6_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000)
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12)
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12)
-#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800)
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11)
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11)
-#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP5_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400)
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10)
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10)
-#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200)
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9)
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9)
-#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP4_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100)
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8)
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8)
-#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080)
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7)
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7)
-#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP3_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040)
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6)
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6)
-#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020)
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5)
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5)
-#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP2_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010)
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4)
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4)
-#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008)
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3)
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3)
-#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP1_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004)
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2)
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2)
-#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002)
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1)
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1)
-#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC"
-// -----------------------------------------------------------------------------
-// Field : USB_EP_STATUS_STALL_NAK_EP0_IN
-// Description : None
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0)
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001)
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0)
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0)
-#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC"
-// =============================================================================
-// Register : USB_USB_MUXING
-// Description : Where to connect the USB controller. Should be to_phy by
-// default.
-#define USB_USB_MUXING_OFFSET _u(0x00000074)
-#define USB_USB_MUXING_BITS _u(0x0000000f)
-#define USB_USB_MUXING_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_USB_MUXING_SOFTCON
-// Description : None
-#define USB_USB_MUXING_SOFTCON_RESET _u(0x0)
-#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008)
-#define USB_USB_MUXING_SOFTCON_MSB _u(3)
-#define USB_USB_MUXING_SOFTCON_LSB _u(3)
-#define USB_USB_MUXING_SOFTCON_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_MUXING_TO_DIGITAL_PAD
-// Description : None
-#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0)
-#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004)
-#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2)
-#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2)
-#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_MUXING_TO_EXTPHY
-// Description : None
-#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0)
-#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002)
-#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1)
-#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1)
-#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_MUXING_TO_PHY
-// Description : None
-#define USB_USB_MUXING_TO_PHY_RESET _u(0x0)
-#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001)
-#define USB_USB_MUXING_TO_PHY_MSB _u(0)
-#define USB_USB_MUXING_TO_PHY_LSB _u(0)
-#define USB_USB_MUXING_TO_PHY_ACCESS "RW"
-// =============================================================================
-// Register : USB_USB_PWR
-// Description : Overrides for the power signals in the event that the VBUS
-// signals are not hooked up to GPIO. Set the value of the
-// override and then the override enable to switch over to the
-// override value.
-#define USB_USB_PWR_OFFSET _u(0x00000078)
-#define USB_USB_PWR_BITS _u(0x0000003f)
-#define USB_USB_PWR_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_USB_PWR_OVERCURR_DETECT_EN
-// Description : None
-#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0)
-#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020)
-#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5)
-#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5)
-#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_PWR_OVERCURR_DETECT
-// Description : None
-#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0)
-#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010)
-#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4)
-#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4)
-#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN
-// Description : None
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008)
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3)
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3)
-#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_PWR_VBUS_DETECT
-// Description : None
-#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0)
-#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004)
-#define USB_USB_PWR_VBUS_DETECT_MSB _u(2)
-#define USB_USB_PWR_VBUS_DETECT_LSB _u(2)
-#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN
-// Description : None
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002)
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1)
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1)
-#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USB_PWR_VBUS_EN
-// Description : None
-#define USB_USB_PWR_VBUS_EN_RESET _u(0x0)
-#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001)
-#define USB_USB_PWR_VBUS_EN_MSB _u(0)
-#define USB_USB_PWR_VBUS_EN_LSB _u(0)
-#define USB_USB_PWR_VBUS_EN_ACCESS "RW"
-// =============================================================================
-// Register : USB_USBPHY_DIRECT
-// Description : This register allows for direct control of the USB phy. Use in
-// conjunction with usbphy_direct_override register to enable each
-// override bit.
-#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c)
-#define USB_USBPHY_DIRECT_BITS _u(0x007fff77)
-#define USB_USBPHY_DIRECT_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DM_OVV
-// Description : DM over voltage
-#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000)
-#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22)
-#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22)
-#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DP_OVV
-// Description : DP over voltage
-#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000)
-#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21)
-#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21)
-#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DM_OVCN
-// Description : DM overcurrent
-#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000)
-#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20)
-#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20)
-#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DP_OVCN
-// Description : DP overcurrent
-#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000)
-#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19)
-#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19)
-#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_RX_DM
-// Description : DPM pin state
-#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000)
-#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18)
-#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18)
-#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_RX_DP
-// Description : DPP pin state
-#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000)
-#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17)
-#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17)
-#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_RX_DD
-// Description : Differential RX
-#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000)
-#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16)
-#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16)
-#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_TX_DIFFMODE
-// Description : TX_DIFFMODE=0: Single ended mode
-// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE
-// ignored)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15)
-#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_TX_FSSLEW
-// Description : TX_FSSLEW=0: Low speed slew rate
-// TX_FSSLEW=1: Full speed slew rate
-#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000)
-#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14)
-#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14)
-#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_TX_PD
-// Description : TX power down override (if override enable is set). 1 = powered
-// down.
-#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000)
-#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13)
-#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13)
-#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_RX_PD
-// Description : RX power down override (if override enable is set). 1 = powered
-// down.
-#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000)
-#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12)
-#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12)
-#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_TX_DM
-// Description : Output data. TX_DIFFMODE=1, Ignored
-// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive.
-// DPM=TX_DM
-#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800)
-#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11)
-#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11)
-#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_TX_DP
-// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair.
-// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
-// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive.
-// DPP=TX_DP
-#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400)
-#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10)
-#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10)
-#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_TX_DM_OE
-// Description : Output enable. If TX_DIFFMODE=1, Ignored.
-// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 -
-// DPM driving
-#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200)
-#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9)
-#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9)
-#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_TX_DP_OE
-// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 -
-// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
-// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 -
-// DPP driving
-#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100)
-#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8)
-#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8)
-#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN
-// Description : DM pull down enable
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040)
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6)
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6)
-#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN
-// Description : DM pull up enable
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020)
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5)
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5)
-#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL
-// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 -
-// Pull = Rpu1 + Rpu2
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010)
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4)
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4)
-#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN
-// Description : DP pull down enable
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004)
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2)
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2)
-#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN
-// Description : DP pull up enable
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002)
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1)
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1)
-#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL
-// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 -
-// Pull = Rpu1 + Rpu2
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001)
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0)
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0)
-#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW"
-// =============================================================================
-// Register : USB_USBPHY_DIRECT_OVERRIDE
-// Description : Override enable for each control in usbphy_direct
-#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080)
-#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff)
-#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200)
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9)
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9)
-#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5)
-#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1)
-#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN
-// Description : None
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0)
-#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
-// =============================================================================
-// Register : USB_USBPHY_TRIM
-// Description : Used to adjust trim values of USB phy pull down resistors.
-#define USB_USBPHY_TRIM_OFFSET _u(0x00000084)
-#define USB_USBPHY_TRIM_BITS _u(0x00001f1f)
-#define USB_USBPHY_TRIM_RESET _u(0x00001f1f)
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM
-// Description : Value to drive to USB PHY
-// DM pulldown resistor trim control
-// Experimental data suggests that the reset value will work, but
-// this register allows adjustment if required
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f)
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00)
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12)
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8)
-#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM
-// Description : Value to drive to USB PHY
-// DP pulldown resistor trim control
-// Experimental data suggests that the reset value will work, but
-// this register allows adjustment if required
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f)
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f)
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4)
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0)
-#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW"
-// =============================================================================
-// Register : USB_INTR
-// Description : Raw Interrupts
-#define USB_INTR_OFFSET _u(0x0000008c)
-#define USB_INTR_BITS _u(0x000fffff)
-#define USB_INTR_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_EP_STALL_NAK
-// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
-// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTR_EP_STALL_NAK_RESET _u(0x0)
-#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000)
-#define USB_INTR_EP_STALL_NAK_MSB _u(19)
-#define USB_INTR_EP_STALL_NAK_LSB _u(19)
-#define USB_INTR_EP_STALL_NAK_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_ABORT_DONE
-// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
-// bits in ABORT_DONE.
-#define USB_INTR_ABORT_DONE_RESET _u(0x0)
-#define USB_INTR_ABORT_DONE_BITS _u(0x00040000)
-#define USB_INTR_ABORT_DONE_MSB _u(18)
-#define USB_INTR_ABORT_DONE_LSB _u(18)
-#define USB_INTR_ABORT_DONE_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_DEV_SOF
-// Description : Set every time the device receives a SOF (Start of Frame)
-// packet. Cleared by reading SOF_RD
-#define USB_INTR_DEV_SOF_RESET _u(0x0)
-#define USB_INTR_DEV_SOF_BITS _u(0x00020000)
-#define USB_INTR_DEV_SOF_MSB _u(17)
-#define USB_INTR_DEV_SOF_LSB _u(17)
-#define USB_INTR_DEV_SOF_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_SETUP_REQ
-// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTR_SETUP_REQ_RESET _u(0x0)
-#define USB_INTR_SETUP_REQ_BITS _u(0x00010000)
-#define USB_INTR_SETUP_REQ_MSB _u(16)
-#define USB_INTR_SETUP_REQ_LSB _u(16)
-#define USB_INTR_SETUP_REQ_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_DEV_RESUME_FROM_HOST
-// Description : Set when the device receives a resume from the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0)
-#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
-#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15)
-#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15)
-#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_DEV_SUSPEND
-// Description : Set when the device suspend state changes. Cleared by writing
-// to SIE_STATUS.SUSPENDED
-#define USB_INTR_DEV_SUSPEND_RESET _u(0x0)
-#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000)
-#define USB_INTR_DEV_SUSPEND_MSB _u(14)
-#define USB_INTR_DEV_SUSPEND_LSB _u(14)
-#define USB_INTR_DEV_SUSPEND_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_DEV_CONN_DIS
-// Description : Set when the device connection state changes. Cleared by
-// writing to SIE_STATUS.CONNECTED
-#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0)
-#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000)
-#define USB_INTR_DEV_CONN_DIS_MSB _u(13)
-#define USB_INTR_DEV_CONN_DIS_LSB _u(13)
-#define USB_INTR_DEV_CONN_DIS_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_BUS_RESET
-// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTR_BUS_RESET_RESET _u(0x0)
-#define USB_INTR_BUS_RESET_BITS _u(0x00001000)
-#define USB_INTR_BUS_RESET_MSB _u(12)
-#define USB_INTR_BUS_RESET_LSB _u(12)
-#define USB_INTR_BUS_RESET_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECTED
-#define USB_INTR_VBUS_DETECT_RESET _u(0x0)
-#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800)
-#define USB_INTR_VBUS_DETECT_MSB _u(11)
-#define USB_INTR_VBUS_DETECT_LSB _u(11)
-#define USB_INTR_VBUS_DETECT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_STALL
-// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTR_STALL_RESET _u(0x0)
-#define USB_INTR_STALL_BITS _u(0x00000400)
-#define USB_INTR_STALL_MSB _u(10)
-#define USB_INTR_STALL_LSB _u(10)
-#define USB_INTR_STALL_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_ERROR_CRC
-// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTR_ERROR_CRC_RESET _u(0x0)
-#define USB_INTR_ERROR_CRC_BITS _u(0x00000200)
-#define USB_INTR_ERROR_CRC_MSB _u(9)
-#define USB_INTR_ERROR_CRC_LSB _u(9)
-#define USB_INTR_ERROR_CRC_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_ERROR_BIT_STUFF
-// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0)
-#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100)
-#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8)
-#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8)
-#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_ERROR_RX_OVERFLOW
-// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0)
-#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
-#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7)
-#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7)
-#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_ERROR_RX_TIMEOUT
-// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0)
-#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
-#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6)
-#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6)
-#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_ERROR_DATA_SEQ
-// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0)
-#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020)
-#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5)
-#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5)
-#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_BUFF_STATUS
-// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
-// all bits in BUFF_STATUS.
-#define USB_INTR_BUFF_STATUS_RESET _u(0x0)
-#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010)
-#define USB_INTR_BUFF_STATUS_MSB _u(4)
-#define USB_INTR_BUFF_STATUS_LSB _u(4)
-#define USB_INTR_BUFF_STATUS_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_TRANS_COMPLETE
-// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
-// writing to this bit.
-#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0)
-#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008)
-#define USB_INTR_TRANS_COMPLETE_MSB _u(3)
-#define USB_INTR_TRANS_COMPLETE_LSB _u(3)
-#define USB_INTR_TRANS_COMPLETE_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_HOST_SOF
-// Description : Host: raised every time the host sends a SOF (Start of Frame).
-// Cleared by reading SOF_RD
-#define USB_INTR_HOST_SOF_RESET _u(0x0)
-#define USB_INTR_HOST_SOF_BITS _u(0x00000004)
-#define USB_INTR_HOST_SOF_MSB _u(2)
-#define USB_INTR_HOST_SOF_LSB _u(2)
-#define USB_INTR_HOST_SOF_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_HOST_RESUME
-// Description : Host: raised when a device wakes up the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTR_HOST_RESUME_RESET _u(0x0)
-#define USB_INTR_HOST_RESUME_BITS _u(0x00000002)
-#define USB_INTR_HOST_RESUME_MSB _u(1)
-#define USB_INTR_HOST_RESUME_LSB _u(1)
-#define USB_INTR_HOST_RESUME_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTR_HOST_CONN_DIS
-// Description : Host: raised when a device is connected or disconnected (i.e.
-// when SIE_STATUS.SPEED changes). Cleared by writing to
-// SIE_STATUS.SPEED
-#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0)
-#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001)
-#define USB_INTR_HOST_CONN_DIS_MSB _u(0)
-#define USB_INTR_HOST_CONN_DIS_LSB _u(0)
-#define USB_INTR_HOST_CONN_DIS_ACCESS "RO"
-// =============================================================================
-// Register : USB_INTE
-// Description : Interrupt Enable
-#define USB_INTE_OFFSET _u(0x00000090)
-#define USB_INTE_BITS _u(0x000fffff)
-#define USB_INTE_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_EP_STALL_NAK
-// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
-// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTE_EP_STALL_NAK_RESET _u(0x0)
-#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000)
-#define USB_INTE_EP_STALL_NAK_MSB _u(19)
-#define USB_INTE_EP_STALL_NAK_LSB _u(19)
-#define USB_INTE_EP_STALL_NAK_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_ABORT_DONE
-// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
-// bits in ABORT_DONE.
-#define USB_INTE_ABORT_DONE_RESET _u(0x0)
-#define USB_INTE_ABORT_DONE_BITS _u(0x00040000)
-#define USB_INTE_ABORT_DONE_MSB _u(18)
-#define USB_INTE_ABORT_DONE_LSB _u(18)
-#define USB_INTE_ABORT_DONE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_DEV_SOF
-// Description : Set every time the device receives a SOF (Start of Frame)
-// packet. Cleared by reading SOF_RD
-#define USB_INTE_DEV_SOF_RESET _u(0x0)
-#define USB_INTE_DEV_SOF_BITS _u(0x00020000)
-#define USB_INTE_DEV_SOF_MSB _u(17)
-#define USB_INTE_DEV_SOF_LSB _u(17)
-#define USB_INTE_DEV_SOF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_SETUP_REQ
-// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTE_SETUP_REQ_RESET _u(0x0)
-#define USB_INTE_SETUP_REQ_BITS _u(0x00010000)
-#define USB_INTE_SETUP_REQ_MSB _u(16)
-#define USB_INTE_SETUP_REQ_LSB _u(16)
-#define USB_INTE_SETUP_REQ_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_DEV_RESUME_FROM_HOST
-// Description : Set when the device receives a resume from the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0)
-#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
-#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15)
-#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15)
-#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_DEV_SUSPEND
-// Description : Set when the device suspend state changes. Cleared by writing
-// to SIE_STATUS.SUSPENDED
-#define USB_INTE_DEV_SUSPEND_RESET _u(0x0)
-#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000)
-#define USB_INTE_DEV_SUSPEND_MSB _u(14)
-#define USB_INTE_DEV_SUSPEND_LSB _u(14)
-#define USB_INTE_DEV_SUSPEND_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_DEV_CONN_DIS
-// Description : Set when the device connection state changes. Cleared by
-// writing to SIE_STATUS.CONNECTED
-#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0)
-#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000)
-#define USB_INTE_DEV_CONN_DIS_MSB _u(13)
-#define USB_INTE_DEV_CONN_DIS_LSB _u(13)
-#define USB_INTE_DEV_CONN_DIS_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_BUS_RESET
-// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTE_BUS_RESET_RESET _u(0x0)
-#define USB_INTE_BUS_RESET_BITS _u(0x00001000)
-#define USB_INTE_BUS_RESET_MSB _u(12)
-#define USB_INTE_BUS_RESET_LSB _u(12)
-#define USB_INTE_BUS_RESET_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECTED
-#define USB_INTE_VBUS_DETECT_RESET _u(0x0)
-#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800)
-#define USB_INTE_VBUS_DETECT_MSB _u(11)
-#define USB_INTE_VBUS_DETECT_LSB _u(11)
-#define USB_INTE_VBUS_DETECT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_STALL
-// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTE_STALL_RESET _u(0x0)
-#define USB_INTE_STALL_BITS _u(0x00000400)
-#define USB_INTE_STALL_MSB _u(10)
-#define USB_INTE_STALL_LSB _u(10)
-#define USB_INTE_STALL_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_ERROR_CRC
-// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTE_ERROR_CRC_RESET _u(0x0)
-#define USB_INTE_ERROR_CRC_BITS _u(0x00000200)
-#define USB_INTE_ERROR_CRC_MSB _u(9)
-#define USB_INTE_ERROR_CRC_LSB _u(9)
-#define USB_INTE_ERROR_CRC_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_ERROR_BIT_STUFF
-// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0)
-#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100)
-#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8)
-#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8)
-#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_ERROR_RX_OVERFLOW
-// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0)
-#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
-#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7)
-#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7)
-#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_ERROR_RX_TIMEOUT
-// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0)
-#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
-#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6)
-#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6)
-#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_ERROR_DATA_SEQ
-// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0)
-#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020)
-#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5)
-#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5)
-#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_BUFF_STATUS
-// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
-// all bits in BUFF_STATUS.
-#define USB_INTE_BUFF_STATUS_RESET _u(0x0)
-#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010)
-#define USB_INTE_BUFF_STATUS_MSB _u(4)
-#define USB_INTE_BUFF_STATUS_LSB _u(4)
-#define USB_INTE_BUFF_STATUS_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_TRANS_COMPLETE
-// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
-// writing to this bit.
-#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0)
-#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008)
-#define USB_INTE_TRANS_COMPLETE_MSB _u(3)
-#define USB_INTE_TRANS_COMPLETE_LSB _u(3)
-#define USB_INTE_TRANS_COMPLETE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_HOST_SOF
-// Description : Host: raised every time the host sends a SOF (Start of Frame).
-// Cleared by reading SOF_RD
-#define USB_INTE_HOST_SOF_RESET _u(0x0)
-#define USB_INTE_HOST_SOF_BITS _u(0x00000004)
-#define USB_INTE_HOST_SOF_MSB _u(2)
-#define USB_INTE_HOST_SOF_LSB _u(2)
-#define USB_INTE_HOST_SOF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_HOST_RESUME
-// Description : Host: raised when a device wakes up the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTE_HOST_RESUME_RESET _u(0x0)
-#define USB_INTE_HOST_RESUME_BITS _u(0x00000002)
-#define USB_INTE_HOST_RESUME_MSB _u(1)
-#define USB_INTE_HOST_RESUME_LSB _u(1)
-#define USB_INTE_HOST_RESUME_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTE_HOST_CONN_DIS
-// Description : Host: raised when a device is connected or disconnected (i.e.
-// when SIE_STATUS.SPEED changes). Cleared by writing to
-// SIE_STATUS.SPEED
-#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0)
-#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001)
-#define USB_INTE_HOST_CONN_DIS_MSB _u(0)
-#define USB_INTE_HOST_CONN_DIS_LSB _u(0)
-#define USB_INTE_HOST_CONN_DIS_ACCESS "RW"
-// =============================================================================
-// Register : USB_INTF
-// Description : Interrupt Force
-#define USB_INTF_OFFSET _u(0x00000094)
-#define USB_INTF_BITS _u(0x000fffff)
-#define USB_INTF_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_EP_STALL_NAK
-// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
-// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTF_EP_STALL_NAK_RESET _u(0x0)
-#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000)
-#define USB_INTF_EP_STALL_NAK_MSB _u(19)
-#define USB_INTF_EP_STALL_NAK_LSB _u(19)
-#define USB_INTF_EP_STALL_NAK_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_ABORT_DONE
-// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
-// bits in ABORT_DONE.
-#define USB_INTF_ABORT_DONE_RESET _u(0x0)
-#define USB_INTF_ABORT_DONE_BITS _u(0x00040000)
-#define USB_INTF_ABORT_DONE_MSB _u(18)
-#define USB_INTF_ABORT_DONE_LSB _u(18)
-#define USB_INTF_ABORT_DONE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_DEV_SOF
-// Description : Set every time the device receives a SOF (Start of Frame)
-// packet. Cleared by reading SOF_RD
-#define USB_INTF_DEV_SOF_RESET _u(0x0)
-#define USB_INTF_DEV_SOF_BITS _u(0x00020000)
-#define USB_INTF_DEV_SOF_MSB _u(17)
-#define USB_INTF_DEV_SOF_LSB _u(17)
-#define USB_INTF_DEV_SOF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_SETUP_REQ
-// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTF_SETUP_REQ_RESET _u(0x0)
-#define USB_INTF_SETUP_REQ_BITS _u(0x00010000)
-#define USB_INTF_SETUP_REQ_MSB _u(16)
-#define USB_INTF_SETUP_REQ_LSB _u(16)
-#define USB_INTF_SETUP_REQ_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_DEV_RESUME_FROM_HOST
-// Description : Set when the device receives a resume from the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0)
-#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
-#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15)
-#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15)
-#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_DEV_SUSPEND
-// Description : Set when the device suspend state changes. Cleared by writing
-// to SIE_STATUS.SUSPENDED
-#define USB_INTF_DEV_SUSPEND_RESET _u(0x0)
-#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000)
-#define USB_INTF_DEV_SUSPEND_MSB _u(14)
-#define USB_INTF_DEV_SUSPEND_LSB _u(14)
-#define USB_INTF_DEV_SUSPEND_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_DEV_CONN_DIS
-// Description : Set when the device connection state changes. Cleared by
-// writing to SIE_STATUS.CONNECTED
-#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0)
-#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000)
-#define USB_INTF_DEV_CONN_DIS_MSB _u(13)
-#define USB_INTF_DEV_CONN_DIS_LSB _u(13)
-#define USB_INTF_DEV_CONN_DIS_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_BUS_RESET
-// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTF_BUS_RESET_RESET _u(0x0)
-#define USB_INTF_BUS_RESET_BITS _u(0x00001000)
-#define USB_INTF_BUS_RESET_MSB _u(12)
-#define USB_INTF_BUS_RESET_LSB _u(12)
-#define USB_INTF_BUS_RESET_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECTED
-#define USB_INTF_VBUS_DETECT_RESET _u(0x0)
-#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800)
-#define USB_INTF_VBUS_DETECT_MSB _u(11)
-#define USB_INTF_VBUS_DETECT_LSB _u(11)
-#define USB_INTF_VBUS_DETECT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_STALL
-// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTF_STALL_RESET _u(0x0)
-#define USB_INTF_STALL_BITS _u(0x00000400)
-#define USB_INTF_STALL_MSB _u(10)
-#define USB_INTF_STALL_LSB _u(10)
-#define USB_INTF_STALL_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_ERROR_CRC
-// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTF_ERROR_CRC_RESET _u(0x0)
-#define USB_INTF_ERROR_CRC_BITS _u(0x00000200)
-#define USB_INTF_ERROR_CRC_MSB _u(9)
-#define USB_INTF_ERROR_CRC_LSB _u(9)
-#define USB_INTF_ERROR_CRC_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_ERROR_BIT_STUFF
-// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0)
-#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100)
-#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8)
-#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8)
-#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_ERROR_RX_OVERFLOW
-// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0)
-#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
-#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7)
-#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7)
-#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_ERROR_RX_TIMEOUT
-// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0)
-#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
-#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6)
-#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6)
-#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_ERROR_DATA_SEQ
-// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0)
-#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020)
-#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5)
-#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5)
-#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_BUFF_STATUS
-// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
-// all bits in BUFF_STATUS.
-#define USB_INTF_BUFF_STATUS_RESET _u(0x0)
-#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010)
-#define USB_INTF_BUFF_STATUS_MSB _u(4)
-#define USB_INTF_BUFF_STATUS_LSB _u(4)
-#define USB_INTF_BUFF_STATUS_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_TRANS_COMPLETE
-// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
-// writing to this bit.
-#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0)
-#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008)
-#define USB_INTF_TRANS_COMPLETE_MSB _u(3)
-#define USB_INTF_TRANS_COMPLETE_LSB _u(3)
-#define USB_INTF_TRANS_COMPLETE_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_HOST_SOF
-// Description : Host: raised every time the host sends a SOF (Start of Frame).
-// Cleared by reading SOF_RD
-#define USB_INTF_HOST_SOF_RESET _u(0x0)
-#define USB_INTF_HOST_SOF_BITS _u(0x00000004)
-#define USB_INTF_HOST_SOF_MSB _u(2)
-#define USB_INTF_HOST_SOF_LSB _u(2)
-#define USB_INTF_HOST_SOF_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_HOST_RESUME
-// Description : Host: raised when a device wakes up the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTF_HOST_RESUME_RESET _u(0x0)
-#define USB_INTF_HOST_RESUME_BITS _u(0x00000002)
-#define USB_INTF_HOST_RESUME_MSB _u(1)
-#define USB_INTF_HOST_RESUME_LSB _u(1)
-#define USB_INTF_HOST_RESUME_ACCESS "RW"
-// -----------------------------------------------------------------------------
-// Field : USB_INTF_HOST_CONN_DIS
-// Description : Host: raised when a device is connected or disconnected (i.e.
-// when SIE_STATUS.SPEED changes). Cleared by writing to
-// SIE_STATUS.SPEED
-#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0)
-#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001)
-#define USB_INTF_HOST_CONN_DIS_MSB _u(0)
-#define USB_INTF_HOST_CONN_DIS_LSB _u(0)
-#define USB_INTF_HOST_CONN_DIS_ACCESS "RW"
-// =============================================================================
-// Register : USB_INTS
-// Description : Interrupt status after masking & forcing
-#define USB_INTS_OFFSET _u(0x00000098)
-#define USB_INTS_BITS _u(0x000fffff)
-#define USB_INTS_RESET _u(0x00000000)
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_EP_STALL_NAK
-// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
-// clearing all bits in EP_STATUS_STALL_NAK.
-#define USB_INTS_EP_STALL_NAK_RESET _u(0x0)
-#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000)
-#define USB_INTS_EP_STALL_NAK_MSB _u(19)
-#define USB_INTS_EP_STALL_NAK_LSB _u(19)
-#define USB_INTS_EP_STALL_NAK_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_ABORT_DONE
-// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
-// bits in ABORT_DONE.
-#define USB_INTS_ABORT_DONE_RESET _u(0x0)
-#define USB_INTS_ABORT_DONE_BITS _u(0x00040000)
-#define USB_INTS_ABORT_DONE_MSB _u(18)
-#define USB_INTS_ABORT_DONE_LSB _u(18)
-#define USB_INTS_ABORT_DONE_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_DEV_SOF
-// Description : Set every time the device receives a SOF (Start of Frame)
-// packet. Cleared by reading SOF_RD
-#define USB_INTS_DEV_SOF_RESET _u(0x0)
-#define USB_INTS_DEV_SOF_BITS _u(0x00020000)
-#define USB_INTS_DEV_SOF_MSB _u(17)
-#define USB_INTS_DEV_SOF_LSB _u(17)
-#define USB_INTS_DEV_SOF_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_SETUP_REQ
-// Description : Device. Source: SIE_STATUS.SETUP_REC
-#define USB_INTS_SETUP_REQ_RESET _u(0x0)
-#define USB_INTS_SETUP_REQ_BITS _u(0x00010000)
-#define USB_INTS_SETUP_REQ_MSB _u(16)
-#define USB_INTS_SETUP_REQ_LSB _u(16)
-#define USB_INTS_SETUP_REQ_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_DEV_RESUME_FROM_HOST
-// Description : Set when the device receives a resume from the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0)
-#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
-#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15)
-#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15)
-#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_DEV_SUSPEND
-// Description : Set when the device suspend state changes. Cleared by writing
-// to SIE_STATUS.SUSPENDED
-#define USB_INTS_DEV_SUSPEND_RESET _u(0x0)
-#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000)
-#define USB_INTS_DEV_SUSPEND_MSB _u(14)
-#define USB_INTS_DEV_SUSPEND_LSB _u(14)
-#define USB_INTS_DEV_SUSPEND_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_DEV_CONN_DIS
-// Description : Set when the device connection state changes. Cleared by
-// writing to SIE_STATUS.CONNECTED
-#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0)
-#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000)
-#define USB_INTS_DEV_CONN_DIS_MSB _u(13)
-#define USB_INTS_DEV_CONN_DIS_LSB _u(13)
-#define USB_INTS_DEV_CONN_DIS_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_BUS_RESET
-// Description : Source: SIE_STATUS.BUS_RESET
-#define USB_INTS_BUS_RESET_RESET _u(0x0)
-#define USB_INTS_BUS_RESET_BITS _u(0x00001000)
-#define USB_INTS_BUS_RESET_MSB _u(12)
-#define USB_INTS_BUS_RESET_LSB _u(12)
-#define USB_INTS_BUS_RESET_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECTED
-#define USB_INTS_VBUS_DETECT_RESET _u(0x0)
-#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800)
-#define USB_INTS_VBUS_DETECT_MSB _u(11)
-#define USB_INTS_VBUS_DETECT_LSB _u(11)
-#define USB_INTS_VBUS_DETECT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_STALL
-// Description : Source: SIE_STATUS.STALL_REC
-#define USB_INTS_STALL_RESET _u(0x0)
-#define USB_INTS_STALL_BITS _u(0x00000400)
-#define USB_INTS_STALL_MSB _u(10)
-#define USB_INTS_STALL_LSB _u(10)
-#define USB_INTS_STALL_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_ERROR_CRC
-// Description : Source: SIE_STATUS.CRC_ERROR
-#define USB_INTS_ERROR_CRC_RESET _u(0x0)
-#define USB_INTS_ERROR_CRC_BITS _u(0x00000200)
-#define USB_INTS_ERROR_CRC_MSB _u(9)
-#define USB_INTS_ERROR_CRC_LSB _u(9)
-#define USB_INTS_ERROR_CRC_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_ERROR_BIT_STUFF
-// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
-#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0)
-#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100)
-#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8)
-#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8)
-#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_ERROR_RX_OVERFLOW
-// Description : Source: SIE_STATUS.RX_OVERFLOW
-#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0)
-#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
-#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7)
-#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7)
-#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_ERROR_RX_TIMEOUT
-// Description : Source: SIE_STATUS.RX_TIMEOUT
-#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0)
-#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
-#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6)
-#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6)
-#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_ERROR_DATA_SEQ
-// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
-#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0)
-#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020)
-#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5)
-#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5)
-#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_BUFF_STATUS
-// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
-// all bits in BUFF_STATUS.
-#define USB_INTS_BUFF_STATUS_RESET _u(0x0)
-#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010)
-#define USB_INTS_BUFF_STATUS_MSB _u(4)
-#define USB_INTS_BUFF_STATUS_LSB _u(4)
-#define USB_INTS_BUFF_STATUS_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_TRANS_COMPLETE
-// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
-// writing to this bit.
-#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0)
-#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008)
-#define USB_INTS_TRANS_COMPLETE_MSB _u(3)
-#define USB_INTS_TRANS_COMPLETE_LSB _u(3)
-#define USB_INTS_TRANS_COMPLETE_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_HOST_SOF
-// Description : Host: raised every time the host sends a SOF (Start of Frame).
-// Cleared by reading SOF_RD
-#define USB_INTS_HOST_SOF_RESET _u(0x0)
-#define USB_INTS_HOST_SOF_BITS _u(0x00000004)
-#define USB_INTS_HOST_SOF_MSB _u(2)
-#define USB_INTS_HOST_SOF_LSB _u(2)
-#define USB_INTS_HOST_SOF_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_HOST_RESUME
-// Description : Host: raised when a device wakes up the host. Cleared by
-// writing to SIE_STATUS.RESUME
-#define USB_INTS_HOST_RESUME_RESET _u(0x0)
-#define USB_INTS_HOST_RESUME_BITS _u(0x00000002)
-#define USB_INTS_HOST_RESUME_MSB _u(1)
-#define USB_INTS_HOST_RESUME_LSB _u(1)
-#define USB_INTS_HOST_RESUME_ACCESS "RO"
-// -----------------------------------------------------------------------------
-// Field : USB_INTS_HOST_CONN_DIS
-// Description : Host: raised when a device is connected or disconnected (i.e.
-// when SIE_STATUS.SPEED changes). Cleared by writing to
-// SIE_STATUS.SPEED
-#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0)
-#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001)
-#define USB_INTS_HOST_CONN_DIS_MSB _u(0)
-#define USB_INTS_HOST_CONN_DIS_LSB _u(0)
-#define USB_INTS_HOST_CONN_DIS_ACCESS "RO"
-
-// =============================================================================
-// Register : M0PLUS_NVIC_ICPR
-// Description : Use the Interrupt Clear-Pending Register to clear pending
-// interrupts and determine which interrupts are currently
-// pending.
-#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280)
-#define M0PLUS_NVIC_ICPR_BITS _u(0xffffffff)
-#define M0PLUS_NVIC_ICPR_RESET _u(0x00000000)
-// =============================================================================
-// Register : M0PLUS_NVIC_ISER
-// Description : Use the Interrupt Set-Enable Register to enable interrupts and
-// determine which interrupts are currently enabled.
-// If a pending interrupt is enabled, the NVIC activates the
-// interrupt based on its priority. If an interrupt is not
-// enabled, asserting its interrupt signal changes the interrupt
-// state to pending, but the NVIC never activates the interrupt,
-// regardless of its priority.
-#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100)
-#define M0PLUS_NVIC_ISER_BITS _u(0xffffffff)
-#define M0PLUS_NVIC_ISER_RESET _u(0x00000000)
-
-typedef struct {
- // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
- volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
-
- // Starts at ep1
- struct usb_device_dpram_ep_ctrl {
- io_rw_32 in;
- io_rw_32 out;
- } ep_ctrl[USB_NUM_ENDPOINTS - 1];
-
- // Starts at ep0
- struct usb_device_dpram_ep_buf_ctrl {
- io_rw_32 in;
- io_rw_32 out;
- } ep_buf_ctrl[USB_NUM_ENDPOINTS];
-
- // EP0 buffers are fixed. Assumes single buffered mode for EP0
- uint8_t ep0_buf_a[0x40];
- uint8_t ep0_buf_b[0x40];
-
- // Rest of DPRAM can be carved up as needed
- uint8_t epx_data[USB_DPRAM_MAX - 0x180];
-} usb_device_dpram_t;
-
-typedef struct {
- // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
- volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
-
- // Interrupt endpoint control 1 -> 15
- struct usb_host_dpram_ep_ctrl {
- io_rw_32 ctrl;
- io_rw_32 spare;
- } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
-
- io_rw_32 epx_buf_ctrl;
- io_rw_32 _spare0;
-
- // Interrupt endpoint buffer control
- struct usb_host_dpram_ep_buf_ctrl {
- io_rw_32 ctrl;
- io_rw_32 spare;
- } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
-
- io_rw_32 epx_ctrl;
-
- uint8_t _spare1[124];
-
- // Should start at 0x180
- uint8_t epx_data[USB_DPRAM_MAX - 0x180];
-} usb_host_dpram_t;
-
-typedef struct {
- _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
- // Device address and endpoint control
- // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to
- // 0x0000007f [6:0] : ADDRESS (0): In device mode, the address that the device should respond to
- io_rw_32 dev_addr_ctrl;
-
- _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
- // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
- //
- // Interrupt endpoint 1
- // 0x04000000 [26] : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub)
- // 0x02000000 [25] : INTEP_DIR (0): Direction of the interrupt endpoint
- // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint
- // 0x0000007f [6:0] : ADDRESS (0): Device address
- io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15
-
- _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
- // Main control register
- // 0x80000000 [31] : SIM_TIMING (0): Reduced timings for simulation
- // 0x00000002 [1] : HOST_NDEVICE (0): Device mode = 0, Host mode = 1
- // 0x00000001 [0] : CONTROLLER_EN (0): Enable controller
- io_rw_32 main_ctrl;
-
- _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
- // Set the SOF (Start of Frame) frame number in the host controller
- // 0x000007ff [10:0] : COUNT (0)
- io_wo_32 sof_rw;
-
- _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
- // Read the last SOF (Start of Frame) frame number seen
- // 0x000007ff [10:0] : COUNT (0)
- io_ro_32 sof_rd;
-
- _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
- // SIE control register
- // 0x80000000 [31] : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
- // 0x40000000 [30] : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1
- // 0x20000000 [29] : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0
- // 0x10000000 [28] : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
- // 0x08000000 [27] : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
- // 0x04000000 [26] : DIRECT_EN (0): Direct bus drive enable
- // 0x02000000 [25] : DIRECT_DP (0): Direct control of DP
- // 0x01000000 [24] : DIRECT_DM (0): Direct control of DM
- // 0x00040000 [18] : TRANSCEIVER_PD (0): Power down bus transceiver
- // 0x00020000 [17] : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3)
- // 0x00010000 [16] : PULLUP_EN (0): Device: Enable pull up resistor
- // 0x00008000 [15] : PULLDOWN_EN (0): Host: Enable pull down resistors
- // 0x00002000 [13] : RESET_BUS (0): Host: Reset bus
- // 0x00001000 [12] : RESUME (0): Device: Remote wakeup
- // 0x00000800 [11] : VBUS_EN (0): Host: Enable VBUS
- // 0x00000400 [10] : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus)
- // 0x00000200 [9] : SOF_EN (0): Host: Enable SOF generation (for full speed bus)
- // 0x00000100 [8] : SOF_SYNC (0): Host: Delay packet(s) until after SOF
- // 0x00000040 [6] : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub
- // 0x00000010 [4] : STOP_TRANS (0): Host: Stop transaction
- // 0x00000008 [3] : RECEIVE_DATA (0): Host: Receive transaction (IN to host)
- // 0x00000004 [2] : SEND_DATA (0): Host: Send transaction (OUT from host)
- // 0x00000002 [1] : SEND_SETUP (0): Host: Send Setup packet
- // 0x00000001 [0] : START_TRANS (0): Host: Start transaction
- io_rw_32 sie_ctrl;
-
- _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
- // SIE status register
- // 0x80000000 [31] : DATA_SEQ_ERROR (0): Data Sequence Error
- // 0x40000000 [30] : ACK_REC (0): ACK received
- // 0x20000000 [29] : STALL_REC (0): Host: STALL received
- // 0x10000000 [28] : NAK_REC (0): Host: NAK received
- // 0x08000000 [27] : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in...
- // 0x04000000 [26] : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast
- // 0x02000000 [25] : BIT_STUFF_ERROR (0): Bit Stuff Error
- // 0x01000000 [24] : CRC_ERROR (0): CRC Error
- // 0x00080000 [19] : BUS_RESET (0): Device: bus reset received
- // 0x00040000 [18] : TRANS_COMPLETE (0): Transaction complete
- // 0x00020000 [17] : SETUP_REC (0): Device: Setup packet received
- // 0x00010000 [16] : CONNECTED (0): Device: connected
- // 0x00000800 [11] : RESUME (0): Host: Device has initiated a remote resume
- // 0x00000400 [10] : VBUS_OVER_CURR (0): VBUS over current detected
- // 0x00000300 [9:8] : SPEED (0): Host: device speed
- // 0x00000010 [4] : SUSPENDED (0): Bus in suspended state
- // 0x0000000c [3:2] : LINE_STATE (0): USB bus line state
- // 0x00000001 [0] : VBUS_DETECTED (0): Device: VBUS Detected
- io_rw_32 sie_status;
-
- _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
- // interrupt endpoint control register
- // 0x0000fffe [15:1] : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15
- io_rw_32 int_ep_ctrl;
-
- _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
- // Buffer status register
- // 0x80000000 [31] : EP15_OUT (0)
- // 0x40000000 [30] : EP15_IN (0)
- // 0x20000000 [29] : EP14_OUT (0)
- // 0x10000000 [28] : EP14_IN (0)
- // 0x08000000 [27] : EP13_OUT (0)
- // 0x04000000 [26] : EP13_IN (0)
- // 0x02000000 [25] : EP12_OUT (0)
- // 0x01000000 [24] : EP12_IN (0)
- // 0x00800000 [23] : EP11_OUT (0)
- // 0x00400000 [22] : EP11_IN (0)
- // 0x00200000 [21] : EP10_OUT (0)
- // 0x00100000 [20] : EP10_IN (0)
- // 0x00080000 [19] : EP9_OUT (0)
- // 0x00040000 [18] : EP9_IN (0)
- // 0x00020000 [17] : EP8_OUT (0)
- // 0x00010000 [16] : EP8_IN (0)
- // 0x00008000 [15] : EP7_OUT (0)
- // 0x00004000 [14] : EP7_IN (0)
- // 0x00002000 [13] : EP6_OUT (0)
- // 0x00001000 [12] : EP6_IN (0)
- // 0x00000800 [11] : EP5_OUT (0)
- // 0x00000400 [10] : EP5_IN (0)
- // 0x00000200 [9] : EP4_OUT (0)
- // 0x00000100 [8] : EP4_IN (0)
- // 0x00000080 [7] : EP3_OUT (0)
- // 0x00000040 [6] : EP3_IN (0)
- // 0x00000020 [5] : EP2_OUT (0)
- // 0x00000010 [4] : EP2_IN (0)
- // 0x00000008 [3] : EP1_OUT (0)
- // 0x00000004 [2] : EP1_IN (0)
- // 0x00000002 [1] : EP0_OUT (0)
- // 0x00000001 [0] : EP0_IN (0)
- io_rw_32 buf_status;
-
- _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
- // Which of the double buffers should be handled
- // 0x80000000 [31] : EP15_OUT (0)
- // 0x40000000 [30] : EP15_IN (0)
- // 0x20000000 [29] : EP14_OUT (0)
- // 0x10000000 [28] : EP14_IN (0)
- // 0x08000000 [27] : EP13_OUT (0)
- // 0x04000000 [26] : EP13_IN (0)
- // 0x02000000 [25] : EP12_OUT (0)
- // 0x01000000 [24] : EP12_IN (0)
- // 0x00800000 [23] : EP11_OUT (0)
- // 0x00400000 [22] : EP11_IN (0)
- // 0x00200000 [21] : EP10_OUT (0)
- // 0x00100000 [20] : EP10_IN (0)
- // 0x00080000 [19] : EP9_OUT (0)
- // 0x00040000 [18] : EP9_IN (0)
- // 0x00020000 [17] : EP8_OUT (0)
- // 0x00010000 [16] : EP8_IN (0)
- // 0x00008000 [15] : EP7_OUT (0)
- // 0x00004000 [14] : EP7_IN (0)
- // 0x00002000 [13] : EP6_OUT (0)
- // 0x00001000 [12] : EP6_IN (0)
- // 0x00000800 [11] : EP5_OUT (0)
- // 0x00000400 [10] : EP5_IN (0)
- // 0x00000200 [9] : EP4_OUT (0)
- // 0x00000100 [8] : EP4_IN (0)
- // 0x00000080 [7] : EP3_OUT (0)
- // 0x00000040 [6] : EP3_IN (0)
- // 0x00000020 [5] : EP2_OUT (0)
- // 0x00000010 [4] : EP2_IN (0)
- // 0x00000008 [3] : EP1_OUT (0)
- // 0x00000004 [2] : EP1_IN (0)
- // 0x00000002 [1] : EP0_OUT (0)
- // 0x00000001 [0] : EP0_IN (0)
- io_ro_32 buf_cpu_should_handle;
-
- _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
- // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer
- // 0x80000000 [31] : EP15_OUT (0)
- // 0x40000000 [30] : EP15_IN (0)
- // 0x20000000 [29] : EP14_OUT (0)
- // 0x10000000 [28] : EP14_IN (0)
- // 0x08000000 [27] : EP13_OUT (0)
- // 0x04000000 [26] : EP13_IN (0)
- // 0x02000000 [25] : EP12_OUT (0)
- // 0x01000000 [24] : EP12_IN (0)
- // 0x00800000 [23] : EP11_OUT (0)
- // 0x00400000 [22] : EP11_IN (0)
- // 0x00200000 [21] : EP10_OUT (0)
- // 0x00100000 [20] : EP10_IN (0)
- // 0x00080000 [19] : EP9_OUT (0)
- // 0x00040000 [18] : EP9_IN (0)
- // 0x00020000 [17] : EP8_OUT (0)
- // 0x00010000 [16] : EP8_IN (0)
- // 0x00008000 [15] : EP7_OUT (0)
- // 0x00004000 [14] : EP7_IN (0)
- // 0x00002000 [13] : EP6_OUT (0)
- // 0x00001000 [12] : EP6_IN (0)
- // 0x00000800 [11] : EP5_OUT (0)
- // 0x00000400 [10] : EP5_IN (0)
- // 0x00000200 [9] : EP4_OUT (0)
- // 0x00000100 [8] : EP4_IN (0)
- // 0x00000080 [7] : EP3_OUT (0)
- // 0x00000040 [6] : EP3_IN (0)
- // 0x00000020 [5] : EP2_OUT (0)
- // 0x00000010 [4] : EP2_IN (0)
- // 0x00000008 [3] : EP1_OUT (0)
- // 0x00000004 [2] : EP1_IN (0)
- // 0x00000002 [1] : EP0_OUT (0)
- // 0x00000001 [0] : EP0_IN (0)
- io_rw_32 abort;
-
- _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
- // Device only: Used in conjunction with `EP_ABORT`
- // 0x80000000 [31] : EP15_OUT (0)
- // 0x40000000 [30] : EP15_IN (0)
- // 0x20000000 [29] : EP14_OUT (0)
- // 0x10000000 [28] : EP14_IN (0)
- // 0x08000000 [27] : EP13_OUT (0)
- // 0x04000000 [26] : EP13_IN (0)
- // 0x02000000 [25] : EP12_OUT (0)
- // 0x01000000 [24] : EP12_IN (0)
- // 0x00800000 [23] : EP11_OUT (0)
- // 0x00400000 [22] : EP11_IN (0)
- // 0x00200000 [21] : EP10_OUT (0)
- // 0x00100000 [20] : EP10_IN (0)
- // 0x00080000 [19] : EP9_OUT (0)
- // 0x00040000 [18] : EP9_IN (0)
- // 0x00020000 [17] : EP8_OUT (0)
- // 0x00010000 [16] : EP8_IN (0)
- // 0x00008000 [15] : EP7_OUT (0)
- // 0x00004000 [14] : EP7_IN (0)
- // 0x00002000 [13] : EP6_OUT (0)
- // 0x00001000 [12] : EP6_IN (0)
- // 0x00000800 [11] : EP5_OUT (0)
- // 0x00000400 [10] : EP5_IN (0)
- // 0x00000200 [9] : EP4_OUT (0)
- // 0x00000100 [8] : EP4_IN (0)
- // 0x00000080 [7] : EP3_OUT (0)
- // 0x00000040 [6] : EP3_IN (0)
- // 0x00000020 [5] : EP2_OUT (0)
- // 0x00000010 [4] : EP2_IN (0)
- // 0x00000008 [3] : EP1_OUT (0)
- // 0x00000004 [2] : EP1_IN (0)
- // 0x00000002 [1] : EP0_OUT (0)
- // 0x00000001 [0] : EP0_IN (0)
- io_rw_32 abort_done;
-
- _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
- // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0
- // 0x00000002 [1] : EP0_OUT (0)
- // 0x00000001 [0] : EP0_IN (0)
- io_rw_32 ep_stall_arm;
-
- _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
- // Used by the host controller
- // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device
- // 0x000003ff [9:0] : DELAY_LS (0x10): NAK polling interval for a low speed device
- io_rw_32 nak_poll;
-
- _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
- // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
- // 0x80000000 [31] : EP15_OUT (0)
- // 0x40000000 [30] : EP15_IN (0)
- // 0x20000000 [29] : EP14_OUT (0)
- // 0x10000000 [28] : EP14_IN (0)
- // 0x08000000 [27] : EP13_OUT (0)
- // 0x04000000 [26] : EP13_IN (0)
- // 0x02000000 [25] : EP12_OUT (0)
- // 0x01000000 [24] : EP12_IN (0)
- // 0x00800000 [23] : EP11_OUT (0)
- // 0x00400000 [22] : EP11_IN (0)
- // 0x00200000 [21] : EP10_OUT (0)
- // 0x00100000 [20] : EP10_IN (0)
- // 0x00080000 [19] : EP9_OUT (0)
- // 0x00040000 [18] : EP9_IN (0)
- // 0x00020000 [17] : EP8_OUT (0)
- // 0x00010000 [16] : EP8_IN (0)
- // 0x00008000 [15] : EP7_OUT (0)
- // 0x00004000 [14] : EP7_IN (0)
- // 0x00002000 [13] : EP6_OUT (0)
- // 0x00001000 [12] : EP6_IN (0)
- // 0x00000800 [11] : EP5_OUT (0)
- // 0x00000400 [10] : EP5_IN (0)
- // 0x00000200 [9] : EP4_OUT (0)
- // 0x00000100 [8] : EP4_IN (0)
- // 0x00000080 [7] : EP3_OUT (0)
- // 0x00000040 [6] : EP3_IN (0)
- // 0x00000020 [5] : EP2_OUT (0)
- // 0x00000010 [4] : EP2_IN (0)
- // 0x00000008 [3] : EP1_OUT (0)
- // 0x00000004 [2] : EP1_IN (0)
- // 0x00000002 [1] : EP0_OUT (0)
- // 0x00000001 [0] : EP0_IN (0)
- io_rw_32 ep_nak_stall_status;
-
- _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
- // Where to connect the USB controller
- // 0x00000008 [3] : SOFTCON (0)
- // 0x00000004 [2] : TO_DIGITAL_PAD (0)
- // 0x00000002 [1] : TO_EXTPHY (0)
- // 0x00000001 [0] : TO_PHY (0)
- io_rw_32 muxing;
-
- _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
- // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
- // 0x00000020 [5] : OVERCURR_DETECT_EN (0)
- // 0x00000010 [4] : OVERCURR_DETECT (0)
- // 0x00000008 [3] : VBUS_DETECT_OVERRIDE_EN (0)
- // 0x00000004 [2] : VBUS_DETECT (0)
- // 0x00000002 [1] : VBUS_EN_OVERRIDE_EN (0)
- // 0x00000001 [0] : VBUS_EN (0)
- io_rw_32 pwr;
-
- _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
- // This register allows for direct control of the USB phy
- // 0x00400000 [22] : DM_OVV (0): DM over voltage
- // 0x00200000 [21] : DP_OVV (0): DP over voltage
- // 0x00100000 [20] : DM_OVCN (0): DM overcurrent
- // 0x00080000 [19] : DP_OVCN (0): DP overcurrent
- // 0x00040000 [18] : RX_DM (0): DPM pin state
- // 0x00020000 [17] : RX_DP (0): DPP pin state
- // 0x00010000 [16] : RX_DD (0): Differential RX
- // 0x00008000 [15] : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode
- // 0x00004000 [14] : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate
- // 0x00002000 [13] : TX_PD (0): TX power down override (if override enable is set)
- // 0x00001000 [12] : RX_PD (0): RX power down override (if override enable is set)
- // 0x00000800 [11] : TX_DM (0): Output data
- // 0x00000400 [10] : TX_DP (0): Output data
- // 0x00000200 [9] : TX_DM_OE (0): Output enable
- // 0x00000100 [8] : TX_DP_OE (0): Output enable
- // 0x00000040 [6] : DM_PULLDN_EN (0): DM pull down enable
- // 0x00000020 [5] : DM_PULLUP_EN (0): DM pull up enable
- // 0x00000010 [4] : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor
- // 0x00000004 [2] : DP_PULLDN_EN (0): DP pull down enable
- // 0x00000002 [1] : DP_PULLUP_EN (0): DP pull up enable
- // 0x00000001 [0] : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor
- io_rw_32 phy_direct;
-
- _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
- // Override enable for each control in usbphy_direct
- // 0x00008000 [15] : TX_DIFFMODE_OVERRIDE_EN (0)
- // 0x00001000 [12] : DM_PULLUP_OVERRIDE_EN (0)
- // 0x00000800 [11] : TX_FSSLEW_OVERRIDE_EN (0)
- // 0x00000400 [10] : TX_PD_OVERRIDE_EN (0)
- // 0x00000200 [9] : RX_PD_OVERRIDE_EN (0)
- // 0x00000100 [8] : TX_DM_OVERRIDE_EN (0)
- // 0x00000080 [7] : TX_DP_OVERRIDE_EN (0)
- // 0x00000040 [6] : TX_DM_OE_OVERRIDE_EN (0)
- // 0x00000020 [5] : TX_DP_OE_OVERRIDE_EN (0)
- // 0x00000010 [4] : DM_PULLDN_EN_OVERRIDE_EN (0)
- // 0x00000008 [3] : DP_PULLDN_EN_OVERRIDE_EN (0)
- // 0x00000004 [2] : DP_PULLUP_EN_OVERRIDE_EN (0)
- // 0x00000002 [1] : DM_PULLUP_HISEL_OVERRIDE_EN (0)
- // 0x00000001 [0] : DP_PULLUP_HISEL_OVERRIDE_EN (0)
- io_rw_32 phy_direct_override;
-
- _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
- // Used to adjust trim values of USB phy pull down resistors
- // 0x00001f00 [12:8] : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY
- // 0x0000001f [4:0] : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY
- io_rw_32 phy_trim;
-
- uint32_t _pad0;
-
- _REG_(USB_INTR_OFFSET) // USB_INTR
- // Raw Interrupts
- // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
- // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
- // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
- // 0x00010000 [16] : SETUP_REQ (0): Device
- // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
- // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
- // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
- // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
- // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
- // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
- // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
- // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
- // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
- // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
- // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
- // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
- // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
- // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
- // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
- // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
- io_ro_32 intr;
-
- _REG_(USB_INTE_OFFSET) // USB_INTE
- // Interrupt Enable
- // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
- // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
- // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
- // 0x00010000 [16] : SETUP_REQ (0): Device
- // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
- // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
- // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
- // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
- // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
- // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
- // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
- // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
- // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
- // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
- // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
- // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
- // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
- // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
- // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
- // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
- io_rw_32 inte;
-
- _REG_(USB_INTF_OFFSET) // USB_INTF
- // Interrupt Force
- // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
- // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
- // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
- // 0x00010000 [16] : SETUP_REQ (0): Device
- // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
- // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
- // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
- // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
- // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
- // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
- // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
- // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
- // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
- // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
- // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
- // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
- // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
- // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
- // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
- // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
- io_rw_32 intf;
-
- _REG_(USB_INTS_OFFSET) // USB_INTS
- // Interrupt status after masking & forcing
- // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
- // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
- // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
- // 0x00010000 [16] : SETUP_REQ (0): Device
- // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
- // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
- // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
- // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
- // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
- // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
- // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
- // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
- // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
- // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
- // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
- // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
- // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
- // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
- // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
- // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
- io_ro_32 ints;
-} usb_hw_t;
-
-typedef struct {
- _REG_(RESETS_RESET_OFFSET) // RESETS_RESET
- // Reset control
- // 0x01000000 [24] : usbctrl (1)
- // 0x00800000 [23] : uart1 (1)
- // 0x00400000 [22] : uart0 (1)
- // 0x00200000 [21] : timer (1)
- // 0x00100000 [20] : tbman (1)
- // 0x00080000 [19] : sysinfo (1)
- // 0x00040000 [18] : syscfg (1)
- // 0x00020000 [17] : spi1 (1)
- // 0x00010000 [16] : spi0 (1)
- // 0x00008000 [15] : rtc (1)
- // 0x00004000 [14] : pwm (1)
- // 0x00002000 [13] : pll_usb (1)
- // 0x00001000 [12] : pll_sys (1)
- // 0x00000800 [11] : pio1 (1)
- // 0x00000400 [10] : pio0 (1)
- // 0x00000200 [9] : pads_qspi (1)
- // 0x00000100 [8] : pads_bank0 (1)
- // 0x00000080 [7] : jtag (1)
- // 0x00000040 [6] : io_qspi (1)
- // 0x00000020 [5] : io_bank0 (1)
- // 0x00000010 [4] : i2c1 (1)
- // 0x00000008 [3] : i2c0 (1)
- // 0x00000004 [2] : dma (1)
- // 0x00000002 [1] : busctrl (1)
- // 0x00000001 [0] : adc (1)
- io_rw_32 reset;
-
- _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
- // Watchdog select
- // 0x01000000 [24] : usbctrl (0)
- // 0x00800000 [23] : uart1 (0)
- // 0x00400000 [22] : uart0 (0)
- // 0x00200000 [21] : timer (0)
- // 0x00100000 [20] : tbman (0)
- // 0x00080000 [19] : sysinfo (0)
- // 0x00040000 [18] : syscfg (0)
- // 0x00020000 [17] : spi1 (0)
- // 0x00010000 [16] : spi0 (0)
- // 0x00008000 [15] : rtc (0)
- // 0x00004000 [14] : pwm (0)
- // 0x00002000 [13] : pll_usb (0)
- // 0x00001000 [12] : pll_sys (0)
- // 0x00000800 [11] : pio1 (0)
- // 0x00000400 [10] : pio0 (0)
- // 0x00000200 [9] : pads_qspi (0)
- // 0x00000100 [8] : pads_bank0 (0)
- // 0x00000080 [7] : jtag (0)
- // 0x00000040 [6] : io_qspi (0)
- // 0x00000020 [5] : io_bank0 (0)
- // 0x00000010 [4] : i2c1 (0)
- // 0x00000008 [3] : i2c0 (0)
- // 0x00000004 [2] : dma (0)
- // 0x00000002 [1] : busctrl (0)
- // 0x00000001 [0] : adc (0)
- io_rw_32 wdsel;
-
- _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
- // Reset done
- // 0x01000000 [24] : usbctrl (0)
- // 0x00800000 [23] : uart1 (0)
- // 0x00400000 [22] : uart0 (0)
- // 0x00200000 [21] : timer (0)
- // 0x00100000 [20] : tbman (0)
- // 0x00080000 [19] : sysinfo (0)
- // 0x00040000 [18] : syscfg (0)
- // 0x00020000 [17] : spi1 (0)
- // 0x00010000 [16] : spi0 (0)
- // 0x00008000 [15] : rtc (0)
- // 0x00004000 [14] : pwm (0)
- // 0x00002000 [13] : pll_usb (0)
- // 0x00001000 [12] : pll_sys (0)
- // 0x00000800 [11] : pio1 (0)
- // 0x00000400 [10] : pio0 (0)
- // 0x00000200 [9] : pads_qspi (0)
- // 0x00000100 [8] : pads_bank0 (0)
- // 0x00000080 [7] : jtag (0)
- // 0x00000040 [6] : io_qspi (0)
- // 0x00000020 [5] : io_bank0 (0)
- // 0x00000010 [4] : i2c1 (0)
- // 0x00000008 [3] : i2c0 (0)
- // 0x00000004 [2] : dma (0)
- // 0x00000002 [1] : busctrl (0)
- // 0x00000001 [0] : adc (0)
- io_ro_32 reset_done;
-} resets_hw_t;
-
-#define USBCTRL_REGS_BASE _u(0x50110000)
-#define USBCTRL_DPRAM_BASE _u(0x50100000)
-#define RESETS_BASE _u(0x4000c000)
-#define PPB_BASE _u(0xe0000000)
-
-#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
-#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
-#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
-#define resets_hw ((resets_hw_t *)RESETS_BASE)
-
-#define REG_ALIAS_RW_BITS (0x0u << 12u)
-#define REG_ALIAS_XOR_BITS (0x1u << 12u)
-#define REG_ALIAS_SET_BITS (0x2u << 12u)
-#define REG_ALIAS_CLR_BITS (0x3u << 12u)
-
-#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
-#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr)))
-#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
-#define usb_hw_set hw_set_alias(usb_hw)
-
-#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
-#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr)))
-#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
-#define usb_hw_clear hw_clear_alias(usb_hw)
-
-/*! \brief Atomically set the specified bits to 1 in a HW register
- * \ingroup hardware_base
- *
- * \param addr Address of writable register
- * \param mask Bit-mask specifying bits to set
- */
-__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask)
-{
- *(io_rw_32 *)hw_set_alias_untyped((volatile void *)addr) = mask;
-}
-
-/*! \brief Atomically clear the specified bits to 0 in a HW register
- * \ingroup hardware_base
- *
- * \param addr Address of writable register
- * \param mask Bit-mask specifying bits to clear
- */
-__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
-{
- *(io_rw_32 *)hw_clear_alias_untyped((volatile void *)addr) = mask;
-}
-
-/*! \brief Reset the specified HW blocks
- * \ingroup hardware_resets
- *
- * \param bits Bit pattern indicating blocks to reset. See \ref reset_bitmask
- */
-static inline void reset_block(uint32_t bits)
-{
- hw_set_bits(&resets_hw->reset, bits);
-}
-
-/*! \brief Bring specified HW blocks out of reset and wait for completion
- * \ingroup hardware_resets
- *
- * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask
- */
-static inline void unreset_block_wait(uint32_t bits)
-{
- hw_clear_bits(&resets_hw->reset, bits);
- while (~resets_hw->reset_done & bits) {
- }
-} \ No newline at end of file
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-31 03:37:33 +0000