Update ch58x dcd porting

2 files changed, 827 insertions, 0 deletions

diff --git a/port/ch32/usb_ch58x_dc_usbfs.c b/port/ch32/usb_ch58x_dc_usbfs.c
new file mode 100644
index 00000000..3e0f2181
--- /dev/null
+++ b/port/ch32/usb_ch58x_dc_usbfs.c
@@ -0,0 +1,583 @@
+#include "usb_dc.h"
+#include "usbd_core.h"
+#include "usb_ch58x_usbfs_reg.h"
+
+/**
+ * @brief   Related register macro
+ */
+#define USB0_BASE 0x40008000u
+#define USB1_BASE 0x40008400u
+
+#ifndef USBD
+#define USBD USB0_BASE
+#endif
+#define CH58x_USBFS_DEV ((USB_FS_TypeDef *)USBD)
+
+/*!< 8-bit value of endpoint control register */
+#define EPn_CTRL(epid) \
+    *(volatile uint8_t *)(&(CH58x_USBFS_DEV->UEP0_CTRL) + epid * 4 + (epid / 5) * 48)
+
+/*!< The length register value of the endpoint send buffer */
+#define EPn_TX_LEN(epid) \
+    *(volatile uint8_t *)(&(CH58x_USBFS_DEV->UEP0_T_LEN) + epid * 4 + (epid / 5) * 48)
+
+/*!< Read setup packet to use in ep0 in */
+#define GET_SETUP_PACKET(data_add) \
+    *(struct usb_setup_packet *)data_add
+
+/*!< Set epid ep tx valid */
+#define EPn_SET_TX_VALID(epid) \
+    EPn_CTRL(epid) = EPn_CTRL(epid) & ~MASK_UEP_T_RES | UEP_T_RES_ACK;
+/*!< Set epid ep rx valid */
+#define EPn_SET_RX_VALID(epid) \
+    EPn_CTRL(epid) = EPn_CTRL(epid) & ~MASK_UEP_R_RES | UEP_R_RES_ACK;
+/*!< Set epid ep tx nak */
+#define EPn_SET_TX_NAK(epid) \
+    EPn_CTRL(epid) = EPn_CTRL(epid) & ~MASK_UEP_T_RES | UEP_T_RES_NAK;
+/*!< Set epid ep rx nak */
+#define EPn_SET_RX_NAK(epid) \
+    EPn_CTRL(epid) = EPn_CTRL(epid) & ~MASK_UEP_R_RES | UEP_R_RES_NAK;
+/*!< Set epid ep tx stall */
+#define EPn_SET_TX_STALL(epid) \
+    EPn_CTRL(epid) = EPn_CTRL(epid) & ~MASK_UEP_T_RES | UEP_T_RES_STALL
+/*!< Set epid ep rx stall */
+#define EPn_SET_RX_STALL(epid) \
+    EPn_CTRL(epid) = EPn_CTRL(epid) & ~MASK_UEP_R_RES | UEP_R_RES_STALL
+/*!< Set epid ep tx len */
+#define EPn_SET_TX_LEN(epid, len) \
+    EPn_TX_LEN(epid) = len
+/*!< Get epid ep rx len */
+#define EPn_GET_RX_LEN(epid) \
+    R8_USB_RX_LEN
+
+/*!< ep nums */
+#ifndef EP_NUMS
+#define EP_NUMS 5
+#endif
+/*!< ep mps */
+#define EP_MPS 64
+/*!< set ep4 in mps 64 */
+#define EP4_IN_MPS EP_MPS
+/*!< set ep4 out mps 64 */
+#define EP4_OUT_MPS EP_MPS
+
+/*!< User defined assignment endpoint RAM */
+__attribute__((aligned(4))) uint8_t ep0_data_buff[64 + EP4_OUT_MPS + EP4_IN_MPS]; /*!< ep0(64)+ep4_out(64)+ep4_in(64) */
+__attribute__((aligned(4))) uint8_t ep1_data_buff[64 + 64];                       /*!< ep1_out(64)+ep1_in(64) */
+__attribute__((aligned(4))) uint8_t ep2_data_buff[64 + 64];                       /*!< ep2_out(64)+ep2_in(64) */
+__attribute__((aligned(4))) uint8_t ep3_data_buff[64 + 64];                       /*!< ep3_out(64)+ep3_in(64) */
+#if (EP_NUMS == 8)
+/**
+ * This dcd porting can be used on ch581, ch582, ch583,
+ * and also on ch571, ch572, and ch573. Note that only five endpoints are available for ch571, ch572, and ch573.
+ */
+__attribute__((aligned(4))) uint8_t ep5_data_buff[64 + 64]; /*!< ep5_out(64)+ep5_in(64) */
+__attribute__((aligned(4))) uint8_t ep6_data_buff[64 + 64]; /*!< ep6_out(64)+ep6_in(64) */
+__attribute__((aligned(4))) uint8_t ep7_data_buff[64 + 64]; /*!< ep7_out(64)+ep7_in(64) */
+#endif
+/**
+ * @brief   Endpoint information structure
+ */
+typedef struct _usbd_ep_info {
+    uint8_t mps;          /*!< Maximum packet length of endpoint */
+    uint8_t eptype;       /*!< Endpoint Type */
+    uint8_t *ep_ram_addr; /*!< Endpoint buffer address */
+
+    uint8_t ep_enable; /* Endpoint enable */
+    uint8_t *xfer_buf;
+    uint32_t xfer_len;
+    uint32_t actual_xfer_len;
+} usbd_ep_info;
+
+/*!< ch58x usb */
+static struct _ch58x_core_prvi {
+    uint8_t address; /*!< Address */
+    usbd_ep_info ep_in[EP_NUMS];
+    usbd_ep_info ep_out[EP_NUMS];
+    struct usb_setup_packet setup;
+} usb_dc_cfg;
+
+__WEAK void usb_dc_low_level_init(void)
+{
+}
+
+__WEAK void usb_dc_low_level_deinit(void)
+{
+}
+
+/**
+ * @brief            Set address
+ * @pre              None
+ * @param[in]        address ：8-bit valid address
+ * @retval           >=0 success otherwise failure
+ */
+int usbd_set_address(const uint8_t address)
+{
+    if (address == 0) {
+        CH58x_USBFS_DEV->USB_DEV_AD = (CH58x_USBFS_DEV->USB_DEV_AD & 0x80) | address;
+    }
+    usb_dc_cfg.address = address;
+    return 0;
+}
+
+/**
+ * @brief            Open endpoint
+ * @pre              None
+ * @param[in]        ep_cfg : Endpoint configuration structure pointer
+ * @retval           >=0 success otherwise failure
+ */
+int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
+{
+    /*!< ep id */
+    uint8_t epid = USB_EP_GET_IDX(ep_cfg->ep_addr);
+    if (epid > (EP_NUMS - 1)) {
+        /**
+         * If you use ch58x, you can change the EP_NUMS set to 8
+         */
+        USB_LOG_ERR("Ep addr %d overflow\r\n", ep_cfg->ep_addr);
+        return -1;
+    }
+
+    /*!< ep max packet length */
+    uint8_t mps = ep_cfg->ep_mps;
+    /*!< update ep max packet length */
+    if (USB_EP_DIR_IS_IN(ep_cfg->ep_addr)) {
+        /*!< in */
+        usb_dc_cfg.ep_in[epid].mps = mps;
+        usb_dc_cfg.ep_in[epid].ep_enable = true;
+    } else if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
+        /*!< out */
+        usb_dc_cfg.ep_out[epid].ep_enable = true;
+        usb_dc_cfg.ep_out[epid].mps = mps;
+    }
+    return 0;
+}
+
+/**
+ * @brief            Close endpoint
+ * @pre              None
+ * @param[in]        ep ： Endpoint address
+ * @retval           >=0 success otherwise failure
+ */
+int usbd_ep_close(const uint8_t ep)
+{
+    /*!< ep id */
+    uint8_t epid = USB_EP_GET_IDX(ep);
+    if (USB_EP_DIR_IS_IN(ep)) {
+        /*!< in */
+        usb_dc_cfg.ep_in[epid].ep_enable = false;
+    } else if (USB_EP_DIR_IS_OUT(ep)) {
+        /*!< out */
+        usb_dc_cfg.ep_out[epid].ep_enable = false;
+    }
+    return 0;
+}
+
+/**
+ * @brief Setup in ep transfer setting and start transfer.
+ *
+ * This function is asynchronous.
+ * This function is similar to uart with tx dma.
+ *
+ * This function is called to write data to the specified endpoint. The
+ * supplied usbd_endpoint_callback function will be called when data is transmitted
+ * out.
+ *
+ * @param[in]  ep        Endpoint address corresponding to the one
+ *                       listed in the device configuration table
+ * @param[in]  data      Pointer to data to write
+ * @param[in]  data_len  Length of the data requested to write. This may
+ *                       be zero for a zero length status packet.
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (!data && data_len) {
+        return -1;
+    }
+    if (!usb_dc_cfg.ep_in[ep_idx].ep_enable) {
+        return -2;
+    }
+    if ((uint32_t)data & 0x03) {
+        return -3;
+    }
+
+    usb_dc_cfg.ep_in[ep_idx].xfer_buf = (uint8_t *)data;
+    usb_dc_cfg.ep_in[ep_idx].xfer_len = data_len;
+    usb_dc_cfg.ep_in[ep_idx].actual_xfer_len = 0;
+
+    if (data_len == 0) {
+        /*!< write 0 len data */
+        EPn_SET_TX_LEN(ep_idx, 0);
+        /*!< enable tx */
+        EPn_SET_TX_VALID(ep_idx);
+        /*!< return */
+        return 0;
+    } else {
+        /*!< Not zlp */
+        data_len = MIN(data_len, usb_dc_cfg.ep_in[ep_idx].mps);
+        /*!< write buff */
+        memcpy(usb_dc_cfg.ep_in[ep_idx].ep_ram_addr, data, data_len);
+        /*!< write real_wt_nums len data */
+        EPn_SET_TX_LEN(ep_idx, data_len);
+        /*!< enable tx */
+        EPn_SET_TX_VALID(ep_idx);
+    }
+    return 0;
+}
+
+/**
+ * @brief Setup out ep transfer setting and start transfer.
+ *
+ * This function is asynchronous.
+ * This function is similar to uart with rx dma.
+ *
+ * This function is called to read data to the specified endpoint. The
+ * supplied usbd_endpoint_callback function will be called when data is received
+ * in.
+ *
+ * @param[in]  ep        Endpoint address corresponding to the one
+ *                       listed in the device configuration table
+ * @param[in]  data      Pointer to data to read
+ * @param[in]  data_len  Max length of the data requested to read.
+ *
+ * @return 0 on success, negative errno code on fail.
+ */
+int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (!data && data_len) {
+        return -1;
+    }
+    if (!usb_dc_cfg.ep_out[ep_idx].ep_enable) {
+        return -2;
+    }
+    if ((uint32_t)data & 0x03) {
+        return -3;
+    }
+
+    usb_dc_cfg.ep_out[ep_idx].xfer_buf = (uint8_t *)data;
+    usb_dc_cfg.ep_out[ep_idx].xfer_len = data_len;
+    usb_dc_cfg.ep_out[ep_idx].actual_xfer_len = 0;
+
+    if (data_len == 0) {
+        return 0;
+    } else {
+        data_len = MIN(data_len, usb_dc_cfg.ep_out[ep_idx].mps);
+    }
+    return 0;
+}
+
+/**
+ * @brief            Endpoint setting stall
+ * @pre              None
+ * @param[in]        ep ： Endpoint address
+ * @retval           >=0 success otherwise failure
+ */
+int usbd_ep_set_stall(const uint8_t ep)
+{
+    /*!< ep id */
+    uint8_t epid = USB_EP_GET_IDX(ep);
+    EPn_SET_RX_STALL(epid);
+    EPn_SET_TX_STALL(epid);
+    return 0;
+}
+
+/**
+ * @brief            Endpoint clear stall
+ * @pre              None
+ * @param[in]        ep ： Endpoint address
+ * @retval           >=0 success otherwise failure
+ */
+int usbd_ep_clear_stall(const uint8_t ep)
+{
+    int ret;
+    switch (ep) {
+        case 0x82:
+            CH58x_USBFS_DEV->UEP2_CTRL = (CH58x_USBFS_DEV->UEP2_CTRL & ~(RB_UEP_T_TOG | MASK_UEP_T_RES)) | UEP_T_RES_NAK;
+            ret = 0;
+            break;
+        case 0x02:
+            CH58x_USBFS_DEV->UEP2_CTRL = (CH58x_USBFS_DEV->UEP2_CTRL & ~(RB_UEP_R_TOG | MASK_UEP_R_RES)) | UEP_R_RES_ACK;
+            ret = 0;
+            break;
+        case 0x81:
+            CH58x_USBFS_DEV->UEP1_CTRL = (CH58x_USBFS_DEV->UEP1_CTRL & ~(RB_UEP_T_TOG | MASK_UEP_T_RES)) | UEP_T_RES_NAK;
+            ret = 0;
+            break;
+        case 0x01:
+            CH58x_USBFS_DEV->UEP1_CTRL = (CH58x_USBFS_DEV->UEP1_CTRL & ~(RB_UEP_R_TOG | MASK_UEP_R_RES)) | UEP_R_RES_ACK;
+            ret = 0;
+            break;
+        default:
+            /*!< Unsupported endpoint */
+            ret = -1;
+            break;
+    }
+    return ret;
+}
+
+/**
+ * @brief            Check endpoint status
+ * @pre              None
+ * @param[in]        ep ： Endpoint address
+ * @param[out]       stalled ： Outgoing endpoint status
+ * @retval           >=0 success otherwise failure
+ */
+int usbd_ep_get_stall(const uint8_t ep, uint8_t *stalled)
+{
+    return 0;
+}
+
+/**
+ * @brief            USB initialization
+ * @pre              None
+ * @param[in]        None
+ * @retval           >=0 success otherwise failure
+ */
+int usb_dc_init(void)
+{
+    usb_dc_cfg.ep_in[0].ep_ram_addr = ep0_data_buff;
+    usb_dc_cfg.ep_out[0].ep_ram_addr = ep0_data_buff;
+
+    usb_dc_cfg.ep_in[1].ep_ram_addr = ep1_data_buff + 64;
+    usb_dc_cfg.ep_out[1].ep_ram_addr = ep1_data_buff;
+
+    usb_dc_cfg.ep_in[2].ep_ram_addr = ep2_data_buff + 64;
+    usb_dc_cfg.ep_out[2].ep_ram_addr = ep2_data_buff;
+
+    usb_dc_cfg.ep_in[3].ep_ram_addr = ep3_data_buff + 64;
+    usb_dc_cfg.ep_out[3].ep_ram_addr = ep3_data_buff;
+
+    usb_dc_cfg.ep_in[4].ep_ram_addr = ep0_data_buff + 64 + EP4_OUT_MPS;
+    usb_dc_cfg.ep_out[4].ep_ram_addr = ep0_data_buff + 64;
+#if (EP_NUMS == 8)
+    usb_dc_cfg.ep_in[5].ep_ram_addr = ep5_data_buff + 64;
+    usb_dc_cfg.ep_out[5].ep_ram_addr = ep5_data_buff;
+
+    usb_dc_cfg.ep_in[6].ep_ram_addr = ep6_data_buff + 64;
+    usb_dc_cfg.ep_out[6].ep_ram_addr = ep6_data_buff;
+
+    usb_dc_cfg.ep_in[7].ep_ram_addr = ep7_data_buff + 64;
+    usb_dc_cfg.ep_out[7].ep_ram_addr = ep7_data_buff;
+#endif
+    /*!< Set the mode first and cancel RB_UC_CLR_ALL */
+    CH58x_USBFS_DEV->USB_CTRL = 0x00;
+    CH58x_USBFS_DEV->UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN; /*!< EP4 OUT+IN   EP1 OUT+IN */
+    CH58x_USBFS_DEV->UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN; /*!< EP2 OUT+IN   EP3 OUT+IN */
+#if (EP_NUMS == 8)
+    CH58x_USBFS_DEV->UEP567_MOD = RB_UEP5_RX_EN | RB_UEP5_TX_EN | RB_UEP6_RX_EN | RB_UEP6_TX_EN | RB_UEP7_RX_EN | RB_UEP7_TX_EN; /*!< EP5 EP6 EP7   OUT+IN */
+#endif
+    CH58x_USBFS_DEV->UEP0_DMA = (uint16_t)(uint32_t)ep0_data_buff;
+    CH58x_USBFS_DEV->UEP1_DMA = (uint16_t)(uint32_t)ep1_data_buff;
+    CH58x_USBFS_DEV->UEP2_DMA = (uint16_t)(uint32_t)ep2_data_buff;
+    CH58x_USBFS_DEV->UEP3_DMA = (uint16_t)(uint32_t)ep3_data_buff;
+#if (EP_NUMS == 8)
+    CH58x_USBFS_DEV->UEP5_DMA = (uint16_t)(uint32_t)ep5_data_buff;
+    CH58x_USBFS_DEV->UEP6_DMA = (uint16_t)(uint32_t)ep6_data_buff;
+    CH58x_USBFS_DEV->UEP7_DMA = (uint16_t)(uint32_t)ep7_data_buff;
+#endif
+    CH58x_USBFS_DEV->UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    CH58x_USBFS_DEV->UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
+    CH58x_USBFS_DEV->UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
+    CH58x_USBFS_DEV->UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
+    CH58x_USBFS_DEV->UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+#if (EP_NUMS == 8)
+    CH58x_USBFS_DEV->UEP5_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
+    CH58x_USBFS_DEV->UEP6_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
+    CH58x_USBFS_DEV->UEP7_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
+#endif
+    CH58x_USBFS_DEV->USB_DEV_AD = 0x00;
+
+    /*!< Start the USB device and DMA, and automatically return to NAK before the interrupt flag is cleared during the interrupt */
+    CH58x_USBFS_DEV->USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN;
+    if ((uint32_t) & (CH58x_USBFS_DEV->USB_CTRL) == (uint32_t)USB0_BASE) {
+        /*!< USB0 */
+        R16_PIN_ANALOG_IE |= RB_PIN_USB_IE | RB_PIN_USB_DP_PU;
+    } else if ((uint32_t) & (CH58x_USBFS_DEV->USB_CTRL) == (uint32_t)USB1_BASE) {
+        /*!< USB1 */
+        R16_PIN_ANALOG_IE |= RB_PIN_USB2_IE | RB_PIN_USB2_DP_PU;
+    }
+
+    CH58x_USBFS_DEV->USB_INT_FG = 0xff;                        /*!< Clear interrupt flag */
+    CH58x_USBFS_DEV->UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN; /*!< Allow USB port */
+    CH58x_USBFS_DEV->USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER;
+
+    usb_dc_low_level_init();
+    return 0;
+}
+
+/**
+ * @brief            USB interrupt processing function
+ * @pre              None
+ * @param[in]        None
+ * @retval           None
+ */
+__attribute__((interrupt("WCH-Interrupt-fast")))
+__attribute__((section(".highcode"))) void
+USB_IRQHandler(void)
+{
+    volatile uint8_t intflag = 0;
+    intflag = CH58x_USBFS_DEV->USB_INT_FG;
+
+    if (intflag & RB_UIF_TRANSFER) {
+        if ((CH58x_USBFS_DEV->USB_INT_ST & MASK_UIS_TOKEN) != MASK_UIS_TOKEN) {
+            uint8_t epid = ((CH58x_USBFS_DEV->USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) & 0x0f);
+            switch ((CH58x_USBFS_DEV->USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) & 0xf0) {
+                case UIS_TOKEN_IN:
+                    if (epid == 0) {
+                        /**
+                         * IN  The host takes away the data that has been stored in FIFO
+                         */
+                        switch (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT) {
+                            case 1:
+                                /*!< Get */
+                                CH58x_USBFS_DEV->UEP0_CTRL ^= RB_UEP_T_TOG;
+                                /**
+                                 * Here is to take away the last data, and the IN interrupt will be triggered only after it is successfully taken away.
+                                 * Therefore, the status of the in endpoint is set to NAK here. If there is data transmission,
+                                 * the endpoint status will be set to ack again in the in handler of EP0.
+                                 */
+                                EPn_SET_TX_NAK(0);
+
+                                /*!< IN */
+                                if (usb_dc_cfg.ep_in[0].xfer_len > usb_dc_cfg.ep_in[0].mps) {
+                                    usb_dc_cfg.ep_in[0].xfer_len -= usb_dc_cfg.ep_in[0].mps;
+                                    usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].mps;
+                                    usbd_event_ep_in_complete_handler(0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len);
+                                } else {
+                                    usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].xfer_len;
+                                    usb_dc_cfg.ep_in[0].xfer_len = 0;
+                                    usbd_event_ep_in_complete_handler(0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len);
+                                }
+                                break;
+                            case 0:
+                                /*!< Set */
+                                switch (usb_dc_cfg.setup.bRequest) {
+                                    case USB_REQUEST_SET_ADDRESS:
+                                        /*!< Fill in the equipment address */
+                                        CH58x_USBFS_DEV->USB_DEV_AD = (CH58x_USBFS_DEV->USB_DEV_AD & RB_UDA_GP_BIT) | usb_dc_cfg.address;
+                                        /**
+                                         * In the state phase after setting the address, the host has sent an in token packet of data1 to take the packet of 0 length,
+                                         * Ch58x USB IP needs to manually set the status of the in endpoint to NAK
+                                         */
+                                        EPn_SET_TX_NAK(0);
+                                        EPn_SET_RX_VALID(0);
+                                        break;
+                                    default:
+                                        /*!< Normal out state phase */
+                                        /**
+                                         * The host has sent an in token packet of data1 and taken the packet of 0 length.
+                                         * Here, you only need to set the status of the in endpoint to NAK and out endpoint ACK
+                                         */
+                                        EPn_SET_TX_NAK(0);
+                                        EPn_SET_RX_VALID(0);
+                                        break;
+                                }
+                                break;
+                        }
+                    } else {
+                        if (epid == 4) {
+                            CH58x_USBFS_DEV->UEP4_CTRL ^= RB_UEP_T_TOG;
+                        }
+                        EPn_SET_TX_NAK(epid);
+                        if (usb_dc_cfg.ep_in[epid].xfer_len > usb_dc_cfg.ep_in[epid].mps) {
+                            /*!< Need start in again */
+                            usb_dc_cfg.ep_in[epid].xfer_buf += usb_dc_cfg.ep_in[epid].mps;
+                            usb_dc_cfg.ep_in[epid].xfer_len -= usb_dc_cfg.ep_in[epid].mps;
+                            usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].mps;
+                            if (usb_dc_cfg.ep_in[epid].xfer_len > usb_dc_cfg.ep_in[epid].mps) {
+                                memcpy(usb_dc_cfg.ep_in[epid].ep_ram_addr, usb_dc_cfg.ep_in[epid].xfer_buf, usb_dc_cfg.ep_in[epid].mps);
+                            } else {
+                                memcpy(usb_dc_cfg.ep_in[epid].ep_ram_addr, usb_dc_cfg.ep_in[epid].xfer_buf, usb_dc_cfg.ep_in[epid].xfer_len);
+                            }
+                            EPn_SET_TX_VALID(epid);
+                        } else {
+                            usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].xfer_len;
+                            usb_dc_cfg.ep_in[epid].xfer_len = 0;
+                            usbd_event_ep_in_complete_handler(epid | 0x80, usb_dc_cfg.ep_in[epid].actual_xfer_len);
+                        }
+                    }
+                    break;
+                case UIS_TOKEN_OUT:
+                    if (epid == 0) {
+                        /*!< ep0 out */
+                        CH58x_USBFS_DEV->UEP0_CTRL ^= RB_UEP_R_TOG;
+                        uint32_t read_count = EPn_GET_RX_LEN(0);
+                        memcpy(usb_dc_cfg.ep_out[epid].xfer_buf, usb_dc_cfg.ep_out[epid].ep_ram_addr, read_count);
+
+                        usb_dc_cfg.ep_out[0].actual_xfer_len += read_count;
+                        usb_dc_cfg.ep_out[0].xfer_len -= read_count;
+                        usbd_event_ep_out_complete_handler(0x00, usb_dc_cfg.ep_out[0].actual_xfer_len);
+                        EPn_SET_RX_VALID(0);
+                    } else {
+                        if ((CH58x_USBFS_DEV->USB_INT_ST) & RB_UIS_TOG_OK) {
+                            if (epid == 4) {
+                                CH58x_USBFS_DEV->UEP4_CTRL ^= RB_UEP_R_TOG;
+                            }
+                            uint32_t read_count = EPn_GET_RX_LEN(epid);
+                            memcpy(usb_dc_cfg.ep_out[epid].xfer_buf, usb_dc_cfg.ep_out[epid].ep_ram_addr, read_count);
+                            usb_dc_cfg.ep_out[epid].xfer_buf += read_count;
+                            usb_dc_cfg.ep_out[epid].actual_xfer_len += read_count;
+                            usb_dc_cfg.ep_out[epid].xfer_len -= read_count;
+
+                            if ((read_count < usb_dc_cfg.ep_out[epid].mps) || (usb_dc_cfg.ep_out[epid].xfer_len == 0)) {
+                                usbd_event_ep_out_complete_handler(((epid)&0x7f), usb_dc_cfg.ep_out[epid].actual_xfer_len);
+                            } else {
+                                EPn_SET_RX_VALID(epid);
+                            }
+                        }
+                    }
+                    break;
+                default:
+                    break;
+            }
+            CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_TRANSFER;
+        }
+
+        if (CH58x_USBFS_DEV->USB_INT_ST & RB_UIS_SETUP_ACT) {
+            /*!< Setup */
+            /**
+             * Setup the device must respond with ACK, and the next data phase is DATA1
+             * If it is sent, the data1 packet will be sent.
+             * If it is received, the data1 packet is expected to be received.
+             * If it is in, the host will send the data1 out packet to complete the status phase after the in completes.
+             * If it is out, the host will send the data1 in packet to complete the status phase after the out completes.
+             */
+            CH58x_USBFS_DEV->UEP0_CTRL = RB_UEP_R_TOG | RB_UEP_T_TOG | UEP_R_RES_ACK | UEP_T_RES_NAK;
+            /*!< get setup packet */
+            usb_dc_cfg.setup = GET_SETUP_PACKET(usb_dc_cfg.ep_out[0].ep_ram_addr);
+            if (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT == 0) {
+               /**
+                * Ep0 The next in must be the status stage.
+                * The device must reply to the host data 0 length packet.
+                * Here, set the transmission length to 0 and the transmission status to ACK,
+                * and wait for the host to send the in token to retrieve
+                */
+                EPn_SET_TX_LEN(0, 0);
+                EPn_SET_TX_VALID(0);
+            }
+            usbd_event_ep0_setup_complete_handler((uint8_t *)&(usb_dc_cfg.setup));
+            /*!< enable ep0 rx */
+            EPn_SET_RX_VALID(0);
+            CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_TRANSFER;
+        }
+    } else if (intflag & RB_UIF_BUS_RST) {
+        /*!< Reset */
+        CH58x_USBFS_DEV->USB_DEV_AD = 0;
+        CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_BUS_RST;
+        usbd_event_reset_handler();
+    } else if (intflag & RB_UIF_SUSPEND) {
+        if (CH58x_USBFS_DEV->USB_MIS_ST & RB_UMS_SUSPEND) {
+            /*!< Suspend */
+        } else {
+            /*!< Wake up */
+        }
+        CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_SUSPEND;
+    } else {
+        CH58x_USBFS_DEV->USB_INT_FG = intflag;
+    }
+}
diff --git a/port/ch32/usb_ch58x_usbfs_reg.h b/port/ch32/usb_ch58x_usbfs_reg.h
new file mode 100644
index 00000000..93d87d1d
--- /dev/null
+++ b/port/ch32/usb_ch58x_usbfs_reg.h
@@ -0,0 +1,244 @@
+#pragma once
+
+#define __IO volatile
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RB_UC_HOST_MODE  0x80 // enable USB host mode: 0=device mode, 1=host mode
+#define RB_UC_LOW_SPEED  0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps
+#define RB_UC_DEV_PU_EN  0x20 // USB device enable and internal pullup resistance enable
+#define RB_UC_SYS_CTRL1  0x20 // USB system control high bit
+#define RB_UC_SYS_CTRL0  0x10 // USB system control low bit
+#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control
+#define RB_UC_INT_BUSY   0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
+#define RB_UC_RESET_SIE  0x04 // force reset USB SIE, need software clear
+#define RB_UC_CLR_ALL    0x02 // force clear FIFO and count of USB
+#define RB_UC_DMA_EN     0x01 // DMA enable and DMA interrupt enable for USB
+
+#define RB_UD_PD_DIS    0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define RB_UD_DP_PIN    0x20 // ReadOnly: indicate current UDP pin level
+#define RB_UD_DM_PIN    0x10 // ReadOnly: indicate current UDM pin level
+#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
+#define RB_UD_GP_BIT    0x02 // general purpose bit
+#define RB_UD_PORT_EN   0x01 // enable USB physical port I/O: 0=disable, 1=enable
+
+#define RB_UH_PD_DIS    0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define RB_UH_DP_PIN    0x20 // ReadOnly: indicate current UDP pin level
+#define RB_UH_DM_PIN    0x10 // ReadOnly: indicate current UDM pin level
+#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
+#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
+#define RB_UH_PORT_EN   0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
+
+#define RB_UIE_DEV_SOF  0x80 // enable interrupt for SOF received for USB device mode
+#define RB_UIE_DEV_NAK  0x40 // enable interrupt for NAK responded for USB device mode
+#define RB_UIE_FIFO_OV  0x10 // enable interrupt for FIFO overflow
+#define RB_UIE_HST_SOF  0x08 // enable interrupt for host SOF timer action for USB host mode
+#define RB_UIE_SUSPEND  0x04 // enable interrupt for USB suspend or resume event
+#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion
+#define RB_UIE_DETECT   0x01 // enable interrupt for USB device detected event for USB host mode
+#define RB_UIE_BUS_RST  0x01 // enable interrupt for USB bus reset event for USB device mode
+
+#define RB_UDA_GP_BIT 0x80 // general purpose bit
+#define MASK_USB_ADDR 0x7F // bit mask for USB device address
+
+#define RB_UMS_SOF_PRES   0x80 // RO, indicate host SOF timer presage status
+#define RB_UMS_SOF_ACT    0x40 // RO, indicate host SOF timer action status for USB host
+#define RB_UMS_SIE_FREE   0x20 // RO, indicate USB SIE free status
+#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty)
+#define RB_UMS_BUS_RESET  0x08 // RO, indicate USB bus reset status
+#define RB_UMS_SUSPEND    0x04 // RO, indicate USB suspend status
+#define RB_UMS_DM_LEVEL   0x02 // RO, indicate UDM level saved at device attached to USB host
+#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host
+
+#define RB_U_IS_NAK     0x80 // RO, indicate current USB transfer is NAK received
+#define RB_U_TOG_OK     0x40 // RO, indicate current USB transfer toggle is OK
+#define RB_U_SIE_FREE   0x20 // RO, indicate USB SIE free status
+#define RB_UIF_FIFO_OV  0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
+#define RB_UIF_HST_SOF  0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
+#define RB_UIF_SUSPEND  0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
+#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
+#define RB_UIF_DETECT   0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
+#define RB_UIF_BUS_RST  0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
+
+#define RB_UIS_SETUP_ACT 0x80 // RO, indicate SETUP token & 8 bytes setup request received for USB device mode
+#define RB_UIS_TOG_OK    0x40 // RO, indicate current USB transfer toggle is OK
+#define RB_UIS_TOKEN1    0x20 // RO, current token PID code bit 1 received for USB device mode
+#define RB_UIS_TOKEN0    0x10 // RO, current token PID code bit 0 received for USB device mode
+#define MASK_UIS_TOKEN   0x30 // RO, bit mask of current token PID code received for USB device mode
+#define UIS_TOKEN_OUT    0x00
+#define UIS_TOKEN_SOF    0x10
+#define UIS_TOKEN_IN     0x20
+#define UIS_TOKEN_SETUP  0x30
+
+#define MASK_UIS_ENDP  0x0F // RO, bit mask of current transfer endpoint number for USB device mode
+#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
+
+#define R8_USB_RX_LEN   (*((uint8_t *)0x40008008)) // USB receiving length
+#define RB_UEP1_RX_EN   0x80                       // enable USB endpoint 1 receiving (OUT)
+#define RB_UEP1_TX_EN   0x40                       // enable USB endpoint 1 transmittal (IN)
+#define RB_UEP1_BUF_MOD 0x10                       // buffer mode of USB endpoint 1
+
+#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
+#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
+
+#define RB_UEP3_RX_EN   0x80 // enable USB endpoint 3 receiving (OUT)
+#define RB_UEP3_TX_EN   0x40 // enable USB endpoint 3 transmittal (IN)
+#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
+#define RB_UEP2_RX_EN   0x08 // enable USB endpoint 2 receiving (OUT)
+#define RB_UEP2_TX_EN   0x04 // enable USB endpoint 2 transmittal (IN)
+#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
+
+#define RB_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT)
+#define RB_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN)
+#define RB_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT)
+#define RB_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN)
+#define RB_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT)
+#define RB_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN)
+
+#define RB_UH_EP_TX_EN    0x40 // enable USB host OUT endpoint transmittal
+#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
+
+#define RB_UH_EP_RX_EN    0x08 // enable USB host IN endpoint receiving
+#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
+
+#define RB_UEP_R_TOG    0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
+#define RB_UEP_T_TOG    0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
+#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
+#define RB_UEP_R_RES1   0x08 // handshake response type high bit for USB endpoint X receiving (OUT)
+#define RB_UEP_R_RES0   0x04 // handshake response type low bit for USB endpoint X receiving (OUT)
+#define MASK_UEP_R_RES  0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT)
+#define UEP_R_RES_ACK   0x00
+#define UEP_R_RES_TOUT  0x04
+#define UEP_R_RES_NAK   0x08
+#define UEP_R_RES_STALL 0x0C
+
+#define RB_UEP_T_RES1   0x02 // handshake response type high bit for USB endpoint X transmittal (IN)
+#define RB_UEP_T_RES0   0x01 // handshake response type low bit for USB endpoint X transmittal (IN)
+#define MASK_UEP_T_RES  0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
+#define UEP_T_RES_ACK   0x00
+#define UEP_T_RES_TOUT  0x01
+#define UEP_T_RES_NAK   0x02
+#define UEP_T_RES_STALL 0x03
+
+#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub
+#define RB_UH_SOF_EN     0x40 // USB host automatic SOF enable
+
+#define R8_UH_EP_PID  R8_UEP2_T_LEN // host endpoint and PID
+#define MASK_UH_TOKEN 0xF0          // bit mask of token PID for USB host transfer
+#define MASK_UH_ENDP  0x0F          // bit mask of endpoint number for USB host transfer
+
+#define R8_UH_RX_CTRL    R8_UEP2_CTRL // host receiver endpoint control
+#define RB_UH_R_TOG      0x80         // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
+#define RB_UH_R_AUTO_TOG 0x10         // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define RB_UH_R_RES      0x04         // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
+
+#define R8_UH_TX_LEN R8_UEP3_T_LEN // host transmittal endpoint transmittal length
+
+#define RB_UH_T_TOG      0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
+#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define RB_UH_T_RES      0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
+
+#define R16_PIN_ANALOG_IE (*((uint16_t *)0x4000101A)) // RW, analog pin enable and digital input disable
+#define RB_PIN_USB_IE     0x80                        // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable
+#define RB_PIN_USB_DP_PU  0x40                        // RW, USB UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode
+#define RB_PIN_USB2_IE    0x20                        // RW, USB2 analog I/O enable: 0=analog I/O disable, 1=analog I/O enable
+#define RB_PIN_USB2_DP_PU 0x10                        // RW, USB2 UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode
+/*!< USB Regs */
+typedef struct
+{
+    __IO uint8_t USB_CTRL; /*!< 0x40008000 */
+    union {
+        __IO uint8_t UDEV_CTRL;  /*!< 0x40008001 */
+        __IO uint8_t UHOST_CTRL; /*!< 0x40008001 */
+    };
+    __IO uint8_t USB_INT_EN;  /*!< 0x40008002 */
+    __IO uint8_t USB_DEV_AD;  /*!< 0x40008003 */
+    __IO uint8_t USB_STATUS0; /*!< 0x40008004 */
+    __IO uint8_t USB_MIS_ST;  /*!< 0x40008005 */
+    __IO uint8_t USB_INT_FG;  /*!< 0x40008006 */
+    __IO uint8_t USB_INT_ST;  /*!< 0x40008007 */
+    __IO uint8_t USB_RX_LEN;  /*!< 0x40008008 */
+    __IO uint8_t Reserve1;    /*!< 0x40008009 */
+    __IO uint8_t Reserve2;    /*!< 0x4000800a */
+    __IO uint8_t Reserve3;    /*!< 0x4000800b */
+    __IO uint8_t UEP4_1_MOD;  /*!< 0x4000800c */
+    union {
+        __IO uint8_t UEP2_3_MOD; /*!< 0x4000800d */
+        __IO uint8_t UH_EP_MOD;  /*!< 0x4000800d */
+    };
+    __IO uint8_t UEP567_MOD; /*!< 0x4000800e */
+    __IO uint8_t Reserve4;   /*!< 0x4000800f */
+    __IO uint16_t UEP0_DMA;  /*!< 0x40008010 */
+    __IO uint16_t Reserve5;  /*!< 0x40008012 */
+    __IO uint16_t UEP1_DMA;  /*!< 0x40008014 */
+    __IO uint16_t Reserve6;  /*!< 0x40008016 */
+    union {
+        __IO uint16_t UEP2_DMA;  /*!< 0x40008018 */
+        __IO uint16_t UH_RX_DMA; /*!< 0x40008018 */
+    };
+    __IO uint16_t Reserve7; /*!< 0x4000801a */
+    union {
+        __IO uint16_t UEP3_DMA;  /*!< 0x4000801c */
+        __IO uint16_t UH_TX_DMA; /*!< 0x4000801c */
+    };
+    __IO uint16_t Reserve8;  /*!< 0x4000801e */
+    __IO uint8_t UEP0_T_LEN; /*!< 0x40008020 */
+    __IO uint8_t Reserve9;   /*!< 0x40008021 */
+    __IO uint8_t UEP0_CTRL;  /*!< 0x40008022 */
+    __IO uint8_t Reserve10;  /*!< 0x40008023 */
+    __IO uint8_t UEP1_T_LEN; /*!< 0x40008024 */
+    __IO uint8_t Reserve11;  /*!< 0x40008025 */
+    union {
+        __IO uint8_t UEP1_CTRL; /*!< 0x40008026 */
+        __IO uint8_t UH_SETUP;  /*!< 0x40008026 */
+    };
+    __IO uint8_t Reserve12; /*!< 0x40008027 */
+    union {
+        __IO uint8_t UEP2_T_LEN; /*!< 0x40008028 */
+        __IO uint8_t UH_EP_PID;  /*!< 0x40008028 */
+    };
+    __IO uint8_t Reserve13; /*!< 0x40008029 */
+    union {
+        __IO uint8_t UEP2_CTRL;  /*!< 0x4000802a */
+        __IO uint8_t UH_RX_CTRL; /*!< 0x4000802a */
+    };
+    __IO uint8_t Reserve14; /*!< 0x4000802b */
+    union {
+        __IO uint8_t UEP3_T_LEN; /*!< 0x4000802c */
+        __IO uint8_t UH_TX_LEN;  /*!< 0x4000802c */
+    };
+    __IO uint8_t Reserve15; /*!< 0x4000802d */
+    union {
+        __IO uint8_t UEP3_CTRL;  /*!< 0x4000802e */
+        __IO uint8_t UH_TX_CTRL; /*!< 0x4000802e */
+    };
+    __IO uint8_t Reserve16;     /*!< 0x4000802f */
+    __IO uint8_t UEP4_T_LEN;    /*!< 0x40008030 */
+    __IO uint8_t Reserve17;     /*!< 0x40008031 */
+    __IO uint8_t UEP4_CTRL;     /*!< 0x40008032 */
+    __IO uint8_t Reserve18[33]; /*!< 0x40008033 */
+    __IO uint16_t UEP5_DMA;     /*!< 0x40008054 */
+    __IO uint16_t Reserve19;    /*!< 0x40008056 */
+    __IO uint16_t UEP6_DMA;     /*!< 0x40008058 */
+    __IO uint16_t Reserve20;    /*!< 0x4000805a */
+    __IO uint16_t UEP7_DMA;     /*!< 0x4000805c */
+    __IO uint8_t Reserve21[6];  /*!< 0x4000805e */
+    __IO uint8_t UEP5_T_LEN;    /*!< 0x40008064 */
+    __IO uint8_t Reserve22;     /*!< 0x40008065 */
+    __IO uint8_t UEP5_CTRL;     /*!< 0x40008066 */
+    __IO uint8_t Reserve23;     /*!< 0x40008067 */
+    __IO uint8_t UEP6_T_LEN;    /*!< 0x40008068 */
+    __IO uint8_t Reserve24;     /*!< 0x40008069 */
+    __IO uint8_t UEP6_CTRL;     /*!< 0x4000806a */
+    __IO uint8_t Reserve25;     /*!< 0x4000806b */
+    __IO uint8_t UEP7_T_LEN;    /*!< 0x4000806c */
+    __IO uint8_t Reserve26;     /*!< 0x4000806d */
+    __IO uint8_t UEP7_CTRL;     /*!< 0x4000806e */
+} USB_FS_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif