diff options
| author | sakumisu <[email protected]> | 2021-12-04 19:28:20 +0800 |
|---|---|---|
| committer | sakumisu <[email protected]> | 2021-12-04 19:28:20 +0800 |
| commit | 9b9f7764107ab3710cc184326ef7a86b55cd10ec (patch) | |
| tree | c4bafc8c293aa816c521be07e63fb742e65010ba | |
| parent | 1ac20b5fdefe91cd1eb01697244747f31dce7a5c (diff) | |
add common usb ip dcd porting
| -rw-r--r-- | port/dw2/README.md | 3 | ||||
| -rw-r--r-- | port/dw2/usb_dw_regs.h | 1786 | ||||
| -rw-r--r-- | port/fsdev/README.md | 2 | ||||
| -rw-r--r-- | port/fsdev/usb_dc_fsdev.c | 497 | ||||
| -rw-r--r-- | port/fsdev/usb_fsdev_regs.h | 2764 |
5 files changed, 5052 insertions, 0 deletions
diff --git a/port/dw2/README.md b/port/dw2/README.md new file mode 100644 index 00000000..001102ae --- /dev/null +++ b/port/dw2/README.md @@ -0,0 +1,3 @@ +# Note + +使用 DesignWare USB OTG IP 的使用该 port
\ No newline at end of file diff --git a/port/dw2/usb_dw_regs.h b/port/dw2/usb_dw_regs.h new file mode 100644 index 00000000..5dc679e2 --- /dev/null +++ b/port/dw2/usb_dw_regs.h @@ -0,0 +1,1786 @@ +#ifndef __USB_DW_REG_H__ +#define __USB_DW_REG_H__ + +#define __IO volatile /*!< Defines 'read / write' permissions */ +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000UL +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ + +/******************** Bit definition forUSB_OTG_HCFG register ********************/ + +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ + +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ + +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ + + +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_I2CPADEN_Pos (17U) +#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/ +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ +#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U) +#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/ + +/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ + +/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ + +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ +#define USB_OTG_DOEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DOEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DOEPCTL_SNPM_Pos (20U) +#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ +#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ +#define USB_OTG_DOEPCTL_STALL_Pos (21U) +#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ +#define USB_OTG_DOEPCTL_CNAK_Pos (26U) +#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DOEPCTL_SNAK_Pos (27U) +#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DOEPCTL_EPENA_Pos (31U) +#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_DOEPINT register ********************/ +#define USB_OTG_DOEPINT_XFRC_Pos (0U) +#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DOEPINT_EPDISD_Pos (1U) +#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */ +#define USB_OTG_DOEPINT_STUP_Pos (3U) +#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ +#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) +#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) +#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */ +#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */ +#define USB_OTG_DOEPINT_NYET_Pos (14U) +#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */ +/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ + +#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ + +#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) +#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for PCGCCTL register ********************/ +#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) +#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ +#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) +#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ +#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ + +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ + + + +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + +#define EP_ADDR_MSK 0xFU + +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) + + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_OTG_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_OTG_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_OTG_HCStateTypeDef; + +/** + * @brief USB Instance Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + +} USB_OTG_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type_ */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +} USB_OTG_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type_ */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ +} USB_OTG_HCTypeDef; + +#endif
\ No newline at end of file diff --git a/port/fsdev/README.md b/port/fsdev/README.md new file mode 100644 index 00000000..b2aeeee3 --- /dev/null +++ b/port/fsdev/README.md @@ -0,0 +1,2 @@ +# Note +与 STM32 USB IP 同系列的使用该 port
\ No newline at end of file diff --git a/port/fsdev/usb_dc_fsdev.c b/port/fsdev/usb_dc_fsdev.c new file mode 100644 index 00000000..2be7688b --- /dev/null +++ b/port/fsdev/usb_dc_fsdev.c @@ -0,0 +1,497 @@ +#include "usbd_core.h" +#include "usb_fsdev_regs.h" + +#define USBD_IRQHandler USB_LP_CAN1_RX0_IRQHandler //use actual usb irq name instead + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 8 +#endif + +#ifndef USB_RAM_SIZE +#define USB_RAM_SIZE 512 +#endif + +#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS) + +static void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +static void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +/* Endpoint state */ +struct usb_dc_ep_state { + /** Endpoint max packet size */ + uint16_t ep_mps; + /** Endpoint Transfer Type. + * May be Bulk, Interrupt, Control or Isochronous + */ + uint8_t ep_type; + uint8_t ep_stalled; /** Endpoint stall flag */ + uint16_t ep_pma_buf_len; /** Previously allocated buffer size */ + uint16_t ep_pma_addr; /**ep pmd allocated addr*/ +}; + +/* Driver state */ +struct usb_dc_config_priv { + USB_TypeDef *Instance; /*!< Register base address */ + __IO uint8_t USB_Address; /*!< USB Address */ + struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ + uint32_t pma_offset; +} usb_dc_cfg; + +int usb_dc_init(void) +{ + memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv)); + + usb_dc_cfg.Instance = USB; + usb_dc_cfg.pma_offset = USB_BTABLE_SIZE; + + USB_TypeDef *USBx = usb_dc_cfg.Instance; + + HAL_PCD_MspInit(&usb_dc_cfg); + + /* Init Device */ + /* CNTR_FRES = 1 */ + USBx->CNTR = (uint16_t)USB_CNTR_FRES; + + /* CNTR_FRES = 0 */ + USBx->CNTR = 0U; + + /* Clear pending interrupts */ + USBx->ISTR = 0U; + + /*Set Btable Address*/ + USBx->BTABLE = BTABLE_ADDRESS; + + uint32_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM; + + /* Set interrupt mask */ + USBx->CNTR = (uint16_t)winterruptmask; + + return 0; +} + +void usb_dc_deinit(void) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + /* disable all interrupts and force USB reset */ + USBx->CNTR = (uint16_t)USB_CNTR_FRES; + + /* clear interrupt status register */ + USBx->ISTR = 0U; + + /* switch-off device */ + USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); + + HAL_PCD_MspDeInit(&usb_dc_cfg); +} + +int usbd_set_address(const uint8_t addr) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + + if (addr == 0U) { + /* set device address and enable function */ + USBx->DADDR = (uint16_t)USB_DADDR_EF; + } + + usb_dc_cfg.USB_Address = addr; + return 0; +} + +int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr); + + if (!ep_cfg) { + return -1; + } + + uint16_t wEpRegVal; + + wEpRegVal = PCD_GET_ENDPOINT(USBx, ep_idx) & USB_EP_T_MASK; + /* initialize Endpoint */ + switch (ep_cfg->ep_type) { + case EP_TYPE_CTRL: + wEpRegVal |= USB_EP_CONTROL; + break; + + case EP_TYPE_BULK: + wEpRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wEpRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wEpRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + break; + } + PCD_SET_ENDPOINT(USBx, ep_idx, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); + + PCD_SET_EP_ADDRESS(USBx, ep_idx, ep_idx); + if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) { + usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps; + usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type; + if (usb_dc_cfg.out_ep[ep_idx].ep_mps > usb_dc_cfg.out_ep[ep_idx].ep_pma_buf_len) { + if (usb_dc_cfg.pma_offset + usb_dc_cfg.out_ep[ep_idx].ep_mps >= 512) { + return -1; + } + usb_dc_cfg.out_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps; + usb_dc_cfg.out_ep[ep_idx].ep_pma_addr = usb_dc_cfg.pma_offset; + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(USBx, ep_idx, usb_dc_cfg.pma_offset); + usb_dc_cfg.pma_offset += ep_cfg->ep_mps; + } + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(USBx, ep_idx, ep_cfg->ep_mps); + PCD_CLEAR_RX_DTOG(USBx, ep_idx); + + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID); + } else { + usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps; + usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type; + if (usb_dc_cfg.in_ep[ep_idx].ep_mps > usb_dc_cfg.in_ep[ep_idx].ep_pma_buf_len) { + if (usb_dc_cfg.pma_offset + usb_dc_cfg.in_ep[ep_idx].ep_mps >= USB_RAM_SIZE) { + return -1; + } + usb_dc_cfg.in_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps; + usb_dc_cfg.in_ep[ep_idx].ep_pma_addr = usb_dc_cfg.pma_offset; + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(USBx, ep_idx, usb_dc_cfg.pma_offset); + usb_dc_cfg.pma_offset += ep_cfg->ep_mps; + } + + PCD_CLEAR_TX_DTOG(USBx, ep_idx); + if (ep_cfg->ep_type != EP_TYPE_ISOC) { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_NAK); + } else { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_DIS); + } + } + return 0; +} +int usbd_ep_close(const uint8_t ep) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_CLEAR_RX_DTOG(USBx, ep_idx); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_DIS); + } else { + PCD_CLEAR_TX_DTOG(USBx, ep_idx); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_DIS); + } + return 0; +} +int usbd_ep_set_stall(const uint8_t ep) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_STALL); + } else { + PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_STALL); + } + return 0; +} +int usbd_ep_clear_stall(const uint8_t ep) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_CLEAR_TX_DTOG(USBx, ep_idx); + + if (usb_dc_cfg.in_ep[ep_idx].ep_type != EP_TYPE_ISOC) { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_NAK); + } + } else { + PCD_CLEAR_RX_DTOG(USBx, ep_idx); + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID); + } + return 0; +} +int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + } else { + } + return 0; +} + +int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!data_len) { + PCD_SET_EP_TX_CNT(USBx, ep_idx, (uint16_t)0); + PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_VALID); + return 0; + } + + if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) { + data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps; + } + + USB_WritePMA(USBx, (uint8_t *)data, usb_dc_cfg.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len); + PCD_SET_EP_TX_CNT(USBx, ep_idx, (uint16_t)data_len); + PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_VALID); + + if (ret_bytes) { + *ret_bytes = data_len; + } + + return 0; +} + +int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + uint32_t read_count; + if (!data && max_data_len) { + return -1; + } + + if (!max_data_len) { + if (ep_idx != 0x00) + PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID); + + return 0; + } + + read_count = PCD_GET_EP_RX_CNT(USBx, ep_idx); + read_count = MIN(read_count, max_data_len); + USB_ReadPMA(USBx, (uint8_t *)data, + usb_dc_cfg.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count); + + if (read_bytes) { + *read_bytes = read_count; + } + + return 0; +} + +/** + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void USBD_IRQHandler(void) +{ + USB_TypeDef *USBx = usb_dc_cfg.Instance; + + uint16_t wIstr, wEPVal; + uint8_t epindex; + wIstr = USBx->ISTR; + + uint16_t store_ep[8]; + if (wIstr & USB_ISTR_CTR) { + while ((USBx->ISTR & USB_ISTR_CTR) != 0U) { + wIstr = USBx->ISTR; + + /* extract highest priority endpoint number */ + epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (epindex == 0U) { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(USBx, 0); + usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL); + if ((usb_dc_cfg.USB_Address > 0U) && (PCD_GET_EP_TX_CNT(USBx, 0) == 0U)) { + USBx->DADDR = ((uint16_t)usb_dc_cfg.USB_Address | USB_DADDR_EF); + usb_dc_cfg.USB_Address = 0U; + } + } + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + + wEPVal = PCD_GET_ENDPOINT(USBx, 0); + + if ((wEPVal & USB_EP_SETUP) != 0U) { + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(USBx, 0); + + /* Process SETUP Packet*/ + usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL); + PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID); + } else if ((wEPVal & USB_EP_CTR_RX) != 0U) { + PCD_CLEAR_RX_EP_CTR(USBx, 0); + /* Process Control Data OUT Packet */ + usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL); + PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID); + } + } else { + /* Decode and service non control endpoints interrupt */ + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(USBx, epindex); + + if ((wEPVal & USB_EP_CTR_RX) != 0U) { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(USBx, epindex); + usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epindex & 0x7f)); + } + + if ((wEPVal & USB_EP_CTR_TX) != 0U) { + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(USBx, epindex); + usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epindex | 0x80)); + } + } + } + } + if (wIstr & USB_ISTR_RESET) { + usbd_event_notify_handler(USBD_EVENT_RESET, NULL); + + USBx->ISTR &= (uint16_t)(~USB_ISTR_RESET); + } + if (wIstr & USB_ISTR_PMAOVR) { + USBx->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR); + } + if (wIstr & USB_ISTR_ERR) { + USBx->ISTR &= (uint16_t)(~USB_ISTR_ERR); + } + if (wIstr & USB_ISTR_WKUP) { + USBx->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE); + USBx->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); + + USBx->ISTR &= (uint16_t)(~USB_ISTR_WKUP); + } + if (wIstr & USB_ISTR_SUSP) { + /* WA: To Clear Wakeup flag if raised with suspend signal */ + + /* Store Endpoint register */ + for (uint8_t i = 0U; i < 8U; i++) { + store_ep[i] = PCD_GET_ENDPOINT(USBx, i); + } + + /* FORCE RESET */ + USBx->CNTR |= (uint16_t)(USB_CNTR_FRES); + + /* CLEAR RESET */ + USBx->CNTR &= (uint16_t)(~USB_CNTR_FRES); + + /* wait for reset flag in ISTR */ + while ((USBx->ISTR & USB_ISTR_RESET) == 0U) { + } + + /* Clear Reset Flag */ + USBx->ISTR &= (uint16_t)(~USB_ISTR_RESET); + /* Restore Registre */ + for (uint8_t i = 0U; i < 8U; i++) { + PCD_SET_ENDPOINT(USBx, i, store_ep[i]); + } + + /* Force low-power mode in the macrocell */ + USBx->CNTR |= (uint16_t)USB_CNTR_FSUSP; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + USBx->ISTR &= (uint16_t)(~USB_ISTR_SUSP); + + USBx->CNTR |= (uint16_t)USB_CNTR_LP_MODE; + } + if (wIstr & USB_ISTR_SOF) { + USBx->ISTR &= (uint16_t)(~USB_ISTR_SOF); + } + if (wIstr & USB_ISTR_ESOF) { + USBx->ISTR &= (uint16_t)(~USB_ISTR_ESOF); + } +} + +static void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp1, temp2; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { + temp1 = *pBuf; + pBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8)); + *pdwVal = (uint16_t)temp2; + pdwVal++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + + pBuf++; + } +} + +/** + * @brief Copy data from packet memory area (PMA) to user memory buffer + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +static void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (uint32_t)wNBytes >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { + temp = *(__IO uint16_t *)pdwVal; + pdwVal++; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + pBuf++; + *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + pBuf++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + } + + if ((wNBytes % 2U) != 0U) { + temp = *pdwVal; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + } +} diff --git a/port/fsdev/usb_fsdev_regs.h b/port/fsdev/usb_fsdev_regs.h new file mode 100644 index 00000000..3441dcbf --- /dev/null +++ b/port/fsdev/usb_fsdev_regs.h @@ -0,0 +1,2764 @@ +#ifndef __USB_FSDEV_REG_H__ +#define __USB_FSDEV_REG_H__ + +#define __IO volatile /*!< Defines 'read / write' permissions */ +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ +} USB_TypeDef; + +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ +#define APB1PERIPH_BASE PERIPH_BASE +/* USB device FS */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ + +#define USB ((USB_TypeDef *)USB_BASE) + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ + +/* bit positions */ +#define USB_EP_CTR_RX_Pos (15U) +#define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX_Pos (14U) +#define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT_Pos (12U) +#define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ +#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP_Pos (11U) +#define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD_Pos (9U) +#define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ +#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ +#define USB_EP_KIND_Pos (8U) +#define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ +#define USB_EP_CTR_TX_Pos (7U) +#define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX_Pos (6U) +#define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT_Pos (4U) +#define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ +#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD_Pos (0U) +#define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ +#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK_Pos (9U) +#define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ +#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */ +#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA_Pos (0U) +#define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX_Pos (4U) +#define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP0R_DTOG_TX_Pos (6U) +#define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX_Pos (7U) +#define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND_Pos (8U) +#define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE_Pos (9U) +#define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP0R_SETUP_Pos (11U) +#define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX_Pos (12U) +#define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP0R_DTOG_RX_Pos (14U) +#define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX_Pos (15U) +#define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA_Pos (0U) +#define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX_Pos (4U) +#define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP1R_DTOG_TX_Pos (6U) +#define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX_Pos (7U) +#define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND_Pos (8U) +#define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE_Pos (9U) +#define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP1R_SETUP_Pos (11U) +#define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX_Pos (12U) +#define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP1R_DTOG_RX_Pos (14U) +#define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX_Pos (15U) +#define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA_Pos (0U) +#define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX_Pos (4U) +#define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP2R_DTOG_TX_Pos (6U) +#define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX_Pos (7U) +#define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND_Pos (8U) +#define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE_Pos (9U) +#define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP2R_SETUP_Pos (11U) +#define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX_Pos (12U) +#define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP2R_DTOG_RX_Pos (14U) +#define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX_Pos (15U) +#define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA_Pos (0U) +#define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX_Pos (4U) +#define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP3R_DTOG_TX_Pos (6U) +#define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX_Pos (7U) +#define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND_Pos (8U) +#define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE_Pos (9U) +#define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP3R_SETUP_Pos (11U) +#define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX_Pos (12U) +#define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP3R_DTOG_RX_Pos (14U) +#define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX_Pos (15U) +#define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA_Pos (0U) +#define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX_Pos (4U) +#define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP4R_DTOG_TX_Pos (6U) +#define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX_Pos (7U) +#define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND_Pos (8U) +#define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE_Pos (9U) +#define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP4R_SETUP_Pos (11U) +#define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX_Pos (12U) +#define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP4R_DTOG_RX_Pos (14U) +#define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX_Pos (15U) +#define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA_Pos (0U) +#define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX_Pos (4U) +#define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP5R_DTOG_TX_Pos (6U) +#define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX_Pos (7U) +#define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND_Pos (8U) +#define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE_Pos (9U) +#define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP5R_SETUP_Pos (11U) +#define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX_Pos (12U) +#define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP5R_DTOG_RX_Pos (14U) +#define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX_Pos (15U) +#define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA_Pos (0U) +#define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX_Pos (4U) +#define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP6R_DTOG_TX_Pos (6U) +#define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX_Pos (7U) +#define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND_Pos (8U) +#define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE_Pos (9U) +#define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP6R_SETUP_Pos (11U) +#define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX_Pos (12U) +#define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP6R_DTOG_RX_Pos (14U) +#define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX_Pos (15U) +#define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA_Pos (0U) +#define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX_Pos (4U) +#define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP7R_DTOG_TX_Pos (6U) +#define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX_Pos (7U) +#define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND_Pos (8U) +#define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE_Pos (9U) +#define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP7R_SETUP_Pos (11U) +#define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX_Pos (12U) +#define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP7R_DTOG_RX_Pos (14U) +#define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX_Pos (15U) +#define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES_Pos (0U) +#define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ +#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ +#define USB_CNTR_PDWN_Pos (1U) +#define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ +#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ +#define USB_CNTR_LP_MODE_Pos (2U) +#define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ +#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ +#define USB_CNTR_FSUSP_Pos (3U) +#define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ +#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ +#define USB_CNTR_RESUME_Pos (4U) +#define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ +#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ +#define USB_CNTR_ESOFM_Pos (8U) +#define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ +#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM_Pos (9U) +#define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ +#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM_Pos (10U) +#define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ +#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM_Pos (11U) +#define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ +#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM_Pos (12U) +#define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ +#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM_Pos (13U) +#define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ +#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM_Pos (14U) +#define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM_Pos (15U) +#define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ +#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID_Pos (0U) +#define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ +#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ +#define USB_ISTR_DIR_Pos (4U) +#define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ +#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ +#define USB_ISTR_ESOF_Pos (8U) +#define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ +#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF_Pos (9U) +#define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ +#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ +#define USB_ISTR_RESET_Pos (10U) +#define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ +#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ +#define USB_ISTR_SUSP_Pos (11U) +#define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ +#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ +#define USB_ISTR_WKUP_Pos (12U) +#define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ +#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ +#define USB_ISTR_ERR_Pos (13U) +#define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ +#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ +#define USB_ISTR_PMAOVR_Pos (14U) +#define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ +#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR_Pos (15U) +#define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ +#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN_Pos (0U) +#define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ +#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ +#define USB_FNR_LSOF_Pos (11U) +#define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ +#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ +#define USB_FNR_LCK_Pos (13U) +#define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ +#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ +#define USB_FNR_RXDM_Pos (14U) +#define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ +#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP_Pos (15U) +#define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ +#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD_Pos (0U) +#define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ +#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0_Pos (0U) +#define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ +#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ +#define USB_DADDR_ADD1_Pos (1U) +#define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ +#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ +#define USB_DADDR_ADD2_Pos (2U) +#define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ +#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ +#define USB_DADDR_ADD3_Pos (3U) +#define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ +#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ +#define USB_DADDR_ADD4_Pos (4U) +#define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ +#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ +#define USB_DADDR_ADD5_Pos (5U) +#define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ +#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ +#define USB_DADDR_ADD6_Pos (6U) +#define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ +#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ + +#define USB_DADDR_EF_Pos (7U) +#define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ +#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE_Pos (3U) +#define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ +#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) +#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) +#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) +#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) +#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) +#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) +#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) +#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) +#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) +#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) +#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) +#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) +#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) +#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) +#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) +#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) +#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) +#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) +#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) +#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) +#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) +#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) +#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) +#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) +#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) +#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT0_RX_BLSIZE_Pos (15U) +#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) +#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT1_RX_BLSIZE_Pos (15U) +#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) +#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT2_RX_BLSIZE_Pos (15U) +#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) +#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT3_RX_BLSIZE_Pos (15U) +#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) +#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT4_RX_BLSIZE_Pos (15U) +#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) +#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT5_RX_BLSIZE_Pos (15U) +#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) +#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT6_RX_BLSIZE_Pos (15U) +#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) +#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT7_RX_BLSIZE_Pos (15U) +#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) *//******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ + +/* bit positions */ +#define USB_EP_CTR_RX_Pos (15U) +#define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX_Pos (14U) +#define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT_Pos (12U) +#define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ +#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP_Pos (11U) +#define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD_Pos (9U) +#define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ +#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ +#define USB_EP_KIND_Pos (8U) +#define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ +#define USB_EP_CTR_TX_Pos (7U) +#define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX_Pos (6U) +#define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT_Pos (4U) +#define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ +#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD_Pos (0U) +#define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ +#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK_Pos (9U) +#define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ +#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */ +#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA_Pos (0U) +#define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX_Pos (4U) +#define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP0R_DTOG_TX_Pos (6U) +#define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX_Pos (7U) +#define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND_Pos (8U) +#define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE_Pos (9U) +#define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP0R_SETUP_Pos (11U) +#define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX_Pos (12U) +#define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP0R_DTOG_RX_Pos (14U) +#define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX_Pos (15U) +#define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA_Pos (0U) +#define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX_Pos (4U) +#define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP1R_DTOG_TX_Pos (6U) +#define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX_Pos (7U) +#define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND_Pos (8U) +#define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE_Pos (9U) +#define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP1R_SETUP_Pos (11U) +#define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX_Pos (12U) +#define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP1R_DTOG_RX_Pos (14U) +#define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX_Pos (15U) +#define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA_Pos (0U) +#define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX_Pos (4U) +#define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP2R_DTOG_TX_Pos (6U) +#define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX_Pos (7U) +#define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND_Pos (8U) +#define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE_Pos (9U) +#define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP2R_SETUP_Pos (11U) +#define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX_Pos (12U) +#define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP2R_DTOG_RX_Pos (14U) +#define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX_Pos (15U) +#define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA_Pos (0U) +#define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX_Pos (4U) +#define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP3R_DTOG_TX_Pos (6U) +#define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX_Pos (7U) +#define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND_Pos (8U) +#define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE_Pos (9U) +#define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP3R_SETUP_Pos (11U) +#define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX_Pos (12U) +#define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP3R_DTOG_RX_Pos (14U) +#define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX_Pos (15U) +#define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA_Pos (0U) +#define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX_Pos (4U) +#define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP4R_DTOG_TX_Pos (6U) +#define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX_Pos (7U) +#define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND_Pos (8U) +#define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE_Pos (9U) +#define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP4R_SETUP_Pos (11U) +#define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX_Pos (12U) +#define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP4R_DTOG_RX_Pos (14U) +#define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX_Pos (15U) +#define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA_Pos (0U) +#define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX_Pos (4U) +#define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP5R_DTOG_TX_Pos (6U) +#define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX_Pos (7U) +#define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND_Pos (8U) +#define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE_Pos (9U) +#define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP5R_SETUP_Pos (11U) +#define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX_Pos (12U) +#define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP5R_DTOG_RX_Pos (14U) +#define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX_Pos (15U) +#define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA_Pos (0U) +#define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX_Pos (4U) +#define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP6R_DTOG_TX_Pos (6U) +#define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX_Pos (7U) +#define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND_Pos (8U) +#define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE_Pos (9U) +#define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP6R_SETUP_Pos (11U) +#define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX_Pos (12U) +#define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP6R_DTOG_RX_Pos (14U) +#define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX_Pos (15U) +#define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA_Pos (0U) +#define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX_Pos (4U) +#define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP7R_DTOG_TX_Pos (6U) +#define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX_Pos (7U) +#define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND_Pos (8U) +#define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE_Pos (9U) +#define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP7R_SETUP_Pos (11U) +#define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX_Pos (12U) +#define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP7R_DTOG_RX_Pos (14U) +#define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX_Pos (15U) +#define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES_Pos (0U) +#define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ +#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ +#define USB_CNTR_PDWN_Pos (1U) +#define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ +#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ +#define USB_CNTR_LP_MODE_Pos (2U) +#define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ +#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ +#define USB_CNTR_FSUSP_Pos (3U) +#define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ +#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ +#define USB_CNTR_RESUME_Pos (4U) +#define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ +#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ +#define USB_CNTR_ESOFM_Pos (8U) +#define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ +#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM_Pos (9U) +#define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ +#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM_Pos (10U) +#define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ +#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM_Pos (11U) +#define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ +#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM_Pos (12U) +#define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ +#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM_Pos (13U) +#define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ +#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM_Pos (14U) +#define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM_Pos (15U) +#define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ +#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID_Pos (0U) +#define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ +#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ +#define USB_ISTR_DIR_Pos (4U) +#define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ +#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ +#define USB_ISTR_ESOF_Pos (8U) +#define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ +#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF_Pos (9U) +#define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ +#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ +#define USB_ISTR_RESET_Pos (10U) +#define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ +#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ +#define USB_ISTR_SUSP_Pos (11U) +#define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ +#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ +#define USB_ISTR_WKUP_Pos (12U) +#define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ +#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ +#define USB_ISTR_ERR_Pos (13U) +#define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ +#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ +#define USB_ISTR_PMAOVR_Pos (14U) +#define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ +#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR_Pos (15U) +#define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ +#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN_Pos (0U) +#define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ +#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ +#define USB_FNR_LSOF_Pos (11U) +#define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ +#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ +#define USB_FNR_LCK_Pos (13U) +#define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ +#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ +#define USB_FNR_RXDM_Pos (14U) +#define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ +#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP_Pos (15U) +#define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ +#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD_Pos (0U) +#define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ +#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0_Pos (0U) +#define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ +#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ +#define USB_DADDR_ADD1_Pos (1U) +#define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ +#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ +#define USB_DADDR_ADD2_Pos (2U) +#define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ +#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ +#define USB_DADDR_ADD3_Pos (3U) +#define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ +#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ +#define USB_DADDR_ADD4_Pos (4U) +#define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ +#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ +#define USB_DADDR_ADD5_Pos (5U) +#define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ +#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ +#define USB_DADDR_ADD6_Pos (6U) +#define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ +#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ + +#define USB_DADDR_EF_Pos (7U) +#define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ +#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE_Pos (3U) +#define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ +#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) +#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) +#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) +#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) +#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) +#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) +#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) +#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) +#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) +#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) +#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) +#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) +#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) +#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) +#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) +#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) +#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) +#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) +#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) +#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) +#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) +#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) +#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) +#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) +#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) +#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT0_RX_BLSIZE_Pos (15U) +#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) +#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT1_RX_BLSIZE_Pos (15U) +#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) +#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT2_RX_BLSIZE_Pos (15U) +#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) +#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT3_RX_BLSIZE_Pos (15U) +#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) +#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT4_RX_BLSIZE_Pos (15U) +#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) +#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT5_RX_BLSIZE_Pos (15U) +#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) +#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT6_RX_BLSIZE_Pos (15U) +#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) +#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT7_RX_BLSIZE_Pos (15U) +#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + + +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_FS_SPEED 2U +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +#define BTABLE_ADDRESS 0x000U +#define PMA_ACCESS 2U +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 10) +#define USB_CNTRX_BLSIZE (0x1U << 15) + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ + } while(0) /* PCD_SET_EP_KIND */ + +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_EP_KIND */ + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_RX_EP_CTR */ + +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \ + } while(0) /* PCD_CLEAR_TX_EP_CTR */ + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ + } while(0) /* PCD_RX_DTOG */ + +#define PCD_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ + } while(0) /* PCD_TX_DTOG */ +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ + { \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_RX_DTOG */ + +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ + { \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_TX_DTOG */ + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_ADDRESS */ + +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_TX_ADDRESS */ + +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_RX_ADDRESS */ + +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U))))) + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ + (wNBlocks) = (wCount) >> 5; \ + if (((wCount) & 0x1fU) == 0U) \ + { \ + (wNBlocks)--; \ + } \ + *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ + } while(0) /* PCD_CALC_BLK32 */ + +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ + (wNBlocks) = (wCount) >> 1; \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ + } while(0) /* PCD_CALC_BLK2 */ + +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ + do { \ + uint32_t wNBlocks; \ + if ((wCount) == 0U) \ + { \ + *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + } \ + } while(0) /* PCD_SET_EP_CNT_RX_REG */ + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ + } while(0) + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + *_wRegVal = (uint16_t)(wCount); \ + } while(0) + +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ + } while(0) + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ + do { \ + PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ + } while(0) /* PCD_SET_EP_DBUF0_ADDR */ + +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ + do { \ + PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF1_ADDR */ + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ + do { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + /* OUT endpoint */ \ + { \ + PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + } \ + } while(0) /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + uint32_t _wBase = (uint32_t)(USBx); \ + __IO uint16_t *_wEPRegVal; \ + \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + _wBase += (uint32_t)(USBx)->BTABLE; \ + _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + *_wEPRegVal = (uint16_t)(wCount); \ + } \ + } \ + } while(0) /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + } while(0) /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + +#endif
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