fix(idf): fix p4 config

Signed-off-by: sakumisu <[email protected]>

1 files changed, 74 insertions, 13 deletions

diff --git a/osal/idf/usb_config.h b/osal/idf/usb_config.h
index b970f705..414a4c74 100644
--- a/osal/idf/usb_config.h
+++ b/osal/idf/usb_config.h
@@ -25,9 +25,16 @@
 #define CONFIG_USB_ALIGN_SIZE 4
 #endif
 
+// #define CONFIG_USB_DCACHE_ENABLE
+
 /* attribute data into no cache ram */
 #define USB_NOCACHE_RAM_SECTION
 
+/* use usb_memcpy default for high performance but cost more flash memory.
+ * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
+*/
+// #define CONFIG_USB_MEMCPY_DISABLE
+
 /* ================= USB Device Stack Configuration ================ */
 
 /* Ep0 in and out transfer buffer */
@@ -49,6 +56,9 @@
 /* Enable test mode */
 // #define CONFIG_USBDEV_TEST_MODE
 
+/* enable advance desc register api */
+#define CONFIG_USBDEV_ADVANCE_DESC
+
 /* move ep0 setup handler from isr to thread */
 // #define CONFIG_USBDEV_EP0_THREAD
 
@@ -84,7 +94,7 @@
 // #define CONFIG_USBDEV_MSC_POLLING
 
 /* move msc read & write from isr to thread */
-// #define CONFIG_USBDEV_MSC_THREAD
+#define CONFIG_USBDEV_MSC_THREAD
 
 #ifndef CONFIG_USBDEV_MSC_PRIO
 #define CONFIG_USBDEV_MSC_PRIO 4
@@ -94,6 +104,28 @@
 #define CONFIG_USBDEV_MSC_STACKSIZE 2048
 #endif
 
+#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE
+#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS
+#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME
+#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
+#endif
+
+#define CONFIG_USBDEV_MTP_THREAD
+
+#ifndef CONFIG_USBDEV_MTP_PRIO
+#define CONFIG_USBDEV_MTP_PRIO 4
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_STACKSIZE
+#define CONFIG_USBDEV_MTP_STACKSIZE 4096
+#endif
+
 #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
 #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
 #endif
@@ -112,6 +144,7 @@
 #endif
 
 #define CONFIG_USBDEV_RNDIS_USING_LWIP
+#define CONFIG_USBDEV_CDC_ECM_USING_LWIP
 
 /* ================ USB HOST Stack Configuration ================== */
 
@@ -137,7 +170,7 @@
 #define CONFIG_USBHOST_PSC_STACKSIZE 2048
 #endif
 
-// #define CONFIG_USBHOST_GET_STRING_DESC
+//#define CONFIG_USBHOST_GET_STRING_DESC
 
 // #define CONFIG_USBHOST_MSOS_ENABLE
 #ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
@@ -236,11 +269,27 @@
 
 #define CONFIG_USB_DWC2_DMA_ENABLE
 
-#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32P4
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define ESP_USBD_BASE           0x50000000UL
+
+#define CONFIG_USBDEV_MAX_BUS 1
+#define CONFIG_USBDEV_EP_NUM 7 // 16
+
+/* ---------------- DWC2 Configuration ---------------- */
+//esp32s2/s3 can support up to 5 IN endpoints(include ep0) at the same time
+#define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
+#define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
+#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
+#define CONFIG_USB_DWC2_TX2_FIFO_SIZE (512 / 4)
+#define CONFIG_USB_DWC2_TX3_FIFO_SIZE (512 / 4)
+#define CONFIG_USB_DWC2_TX4_FIFO_SIZE (512 / 4)
+#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (64 / 4)
+#define CONFIG_USB_DWC2_TX6_FIFO_SIZE (64 / 4)
+#define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
+#define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
+
+#define CONFIG_USB_DWC2_DMA_ENABLE
 #define CONFIG_USB_HS
-#define ESP_USBD_BASE           0x60080000
-// todo: check c5, p4 in later
-#define CONFIG_USBDEV_EP_NUM 7
 #else
 #error "Unsupported SoC"
 #endif
@@ -265,12 +314,24 @@
  */
 #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((200 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
 
-#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32P4
-// todo: check c5, p4 in later
-#define ESP_USBH_BASE               0x60080000
-#define CONFIG_USBHOST_PIPE_NUM 8
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define ESP_USBH_BASE               0x50000000UL
+
+#define CONFIG_USBHOST_MAX_BUS 1
+#define CONFIG_USBHOST_PIPE_NUM 16
+
+/* ---------------- DWC2 Configuration ---------------- */
+/* largest non-periodic USB packet used / 4 */
+#define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4)
+/* largest periodic USB packet used / 4 */
+#define CONFIG_USB_DWC2_PTX_FIFO_SIZE (512 / 4)
+/*
+ * (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
+ * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
+ */
+#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((896 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
+
+#define CONFIG_USB_HS
 #else
 #error "Unsupported SoC"
-#endif
-
-#define CONFIG_USBDEV_ADVANCE_DESC
\ No newline at end of file
+#endif
\ No newline at end of file