read ehci hcor offset from hccr caplength

3 files changed, 17 insertions, 18 deletions

diff --git a/cherryusb_config_template.h b/cherryusb_config_template.h
index a0e7be64..ed09c706 100644
--- a/cherryusb_config_template.h
+++ b/cherryusb_config_template.h
@@ -159,7 +159,6 @@
 /* ================ EHCI Configuration ================ */
 
 #define CONFIG_USB_EHCI_HCCR_OFFSET     (0x0)
-#define CONFIG_USB_EHCI_HCOR_OFFSET     (0x10)
 #define CONFIG_USB_OHCI_HCOR_OFFSET     (0x400)
 #define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
 // #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
diff --git a/port/ehci/usb_ehci_priv.h b/port/ehci/usb_ehci_priv.h
index a134c668..771dae3a 100644
--- a/port/ehci/usb_ehci_priv.h
+++ b/port/ehci/usb_ehci_priv.h
@@ -11,7 +11,7 @@
 #include "usb_hc_ehci.h"
 
 #define EHCI_HCCR ((struct ehci_hccr *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET))
-#define EHCI_HCOR ((struct ehci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCOR_OFFSET))
+#define EHCI_HCOR ((struct ehci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET + g_ehci_hcd[bus->hcd.hcd_id].hcor_offset))
 
 #define EHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x) & ~0x1F)
 #define EHCI_ADDR2QH(x)  ((struct ehci_qh_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F))
@@ -57,7 +57,7 @@ struct ehci_hcd {
     uint8_t n_cc;  /* Number of Companion Controller */
     uint8_t n_pcc; /* Number of ports supported per companion host controller */
     uint8_t n_ports;
-    uint8_t hccr_offset;
+    uint8_t hcor_offset;
 };
 
 extern struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS];
diff --git a/port/ehci/usb_hc_ehci.c b/port/ehci/usb_hc_ehci.c
index 413f5112..eee70d7f 100644
--- a/port/ehci/usb_hc_ehci.c
+++ b/port/ehci/usb_hc_ehci.c
@@ -760,20 +760,6 @@ int usb_hc_init(struct usbh_bus *bus)
 
     usb_hc_low_level_init(bus);
 
-    EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
-    while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) {
-        usb_osal_msleep(1);
-        timeout++;
-        if (timeout > 100) {
-            return -USB_ERR_TIMEOUT;
-        }
-    }
-
-    usb_hc_low_level2_init(bus);
-
-    EHCI_HCOR->usbintr = 0;
-    EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
-
     USB_LOG_INFO("EHCI HCIVERSION:0x%04x\r\n", (unsigned int)EHCI_HCCR->hciversion);
     USB_LOG_INFO("EHCI HCSPARAMS:0x%06x\r\n", (unsigned int)EHCI_HCCR->hcsparams);
     USB_LOG_INFO("EHCI HCCPARAMS:0x%04x\r\n", (unsigned int)EHCI_HCCR->hccparams);
@@ -783,7 +769,7 @@ int usb_hc_init(struct usbh_bus *bus)
     g_ehci_hcd[bus->hcd.hcd_id].n_cc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NCC_MASK) >> EHCI_HCSPARAMS_NCC_SHIFT;
     g_ehci_hcd[bus->hcd.hcd_id].n_pcc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPCC_MASK) >> EHCI_HCSPARAMS_NPCC_SHIFT;
     g_ehci_hcd[bus->hcd.hcd_id].has_tt = g_ehci_hcd[bus->hcd.hcd_id].n_cc ? false : true;
-    g_ehci_hcd[bus->hcd.hcd_id].hccr_offset = EHCI_HCCR->caplength;
+    g_ehci_hcd[bus->hcd.hcd_id].hcor_offset = EHCI_HCCR->caplength;
 
     USB_LOG_INFO("EHCI ppc:%u, n_ports:%u, n_cc:%u, n_pcc:%u\r\n",
                  g_ehci_hcd[bus->hcd.hcd_id].ppc,
@@ -791,6 +777,20 @@ int usb_hc_init(struct usbh_bus *bus)
                  g_ehci_hcd[bus->hcd.hcd_id].n_cc,
                  g_ehci_hcd[bus->hcd.hcd_id].n_pcc);
 
+    EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
+    while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) {
+        usb_osal_msleep(1);
+        timeout++;
+        if (timeout > 100) {
+            return -USB_ERR_TIMEOUT;
+        }
+    }
+
+    usb_hc_low_level2_init(bus);
+
+    EHCI_HCOR->usbintr = 0;
+    EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
+
     /* Set the Current Asynchronous List Address. */
     EHCI_HCOR->asynclistaddr = EHCI_PTR2ADDR(&g_async_qh_head[bus->hcd.hcd_id]);
     /* Set the Periodic Frame List Base Address. */