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authorsakumisu <[email protected]>2025-07-13 17:17:48 +0800
committersakumisu <[email protected]>2025-07-13 20:25:58 +0800
commite32486f9a8d6ae966940fdd60b429f86de8a839b (patch)
treea83701eadfb269a9701520ce78d9068378f2aeb8
parent064507bfe8327703b097c0ef09a582733a14a055 (diff)
feat: support sifli
Signed-off-by: sakumisu <[email protected]>
-rw-r--r--Kconfig4
-rw-r--r--Kconfig.rtt4
-rw-r--r--Kconfig.rttpkg4
-rw-r--r--SConscript6
-rw-r--r--cherryusb.cmake6
-rw-r--r--docs/source/q&a.rst2
-rw-r--r--port/musb/usb_dc_musb.c11
-rw-r--r--port/musb/usb_glue_sifli.c162
-rw-r--r--port/musb/usb_hc_musb.c9
9 files changed, 207 insertions, 1 deletions
diff --git a/Kconfig b/Kconfig
index ae5e7f15..cd593c29 100644
--- a/Kconfig
+++ b/Kconfig
@@ -52,6 +52,8 @@ if CHERRYUSB
bool "musb_sunxi"
config CHERRYUSB_DEVICE_MUSB_BK
bool "musb_bk"
+ config CHERRYUSB_DEVICE_MUSB_SIFLI
+ bool "musb_sifli"
config CHERRYUSB_DEVICE_MUSB_CUSTOM
bool "musb_custom"
config CHERRYUSB_DEVICE_CHIPIDEA_MCX
@@ -270,6 +272,8 @@ if CHERRYUSB
bool "musb_sunxi"
config CHERRYUSB_HOST_MUSB_BK
bool "musb_bk"
+ config CHERRYUSB_HOST_MUSB_SIFLI
+ bool "musb_sifli"
config CHERRYUSB_HOST_MUSB_CUSTOM
bool "musb_custom"
config CHERRYUSB_HOST_PUSB2
diff --git a/Kconfig.rtt b/Kconfig.rtt
index b33c465f..9e1d7a50 100644
--- a/Kconfig.rtt
+++ b/Kconfig.rtt
@@ -52,6 +52,8 @@ if RT_USING_CHERRYUSB
bool "musb_sunxi"
config RT_CHERRYUSB_DEVICE_MUSB_BK
bool "musb_bk"
+ config RT_CHERRYUSB_DEVICE_MUSB_SIFLI
+ bool "musb_sifli"
config RT_CHERRYUSB_DEVICE_MUSB_CUSTOM
bool "musb_custom"
config RT_CHERRYUSB_DEVICE_CHIPIDEA_MCX
@@ -295,6 +297,8 @@ if RT_USING_CHERRYUSB
bool "musb_sunxi"
config RT_CHERRYUSB_HOST_MUSB_BK
bool "musb_bk"
+ config RT_CHERRYUSB_HOST_MUSB_SIFLI
+ bool "musb_sifli"
config RT_CHERRYUSB_HOST_MUSB_CUSTOM
bool "musb_custom"
config RT_CHERRYUSB_HOST_PUSB2
diff --git a/Kconfig.rttpkg b/Kconfig.rttpkg
index 2a62ab7c..7f7862ba 100644
--- a/Kconfig.rttpkg
+++ b/Kconfig.rttpkg
@@ -53,6 +53,8 @@ if PKG_USING_CHERRYUSB
bool "musb_sunxi"
config PKG_CHERRYUSB_DEVICE_MUSB_BK
bool "musb_bk"
+ config PKG_CHERRYUSB_DEVICE_MUSB_SIFLI
+ bool "musb_sifli"
config PKG_CHERRYUSB_DEVICE_MUSB_CUSTOM
bool "musb_custom"
config PKG_CHERRYUSB_DEVICE_CHIPIDEA_MCX
@@ -294,6 +296,8 @@ if PKG_USING_CHERRYUSB
bool "musb_sunxi"
config PKG_CHERRYUSB_HOST_MUSB_BK
bool "musb_bk"
+ config PKG_CHERRYUSB_HOST_MUSB_SIFLI
+ bool "musb_sifli"
config PKG_CHERRYUSB_HOST_MUSB_CUSTOM
bool "musb_custom"
config PKG_CHERRYUSB_HOST_PUSB2
diff --git a/SConscript b/SConscript
index 6d81b57f..81bd3aaf 100644
--- a/SConscript
+++ b/SConscript
@@ -70,6 +70,9 @@ if GetDepend(['PKG_CHERRYUSB_DEVICE']):
if GetDepend(['PKG_CHERRYUSB_DEVICE_MUSB_BK']):
src += Glob('port/musb/usb_dc_musb.c')
src += Glob('port/musb/usb_glue_bk.c')
+ if GetDepend(['PKG_CHERRYUSB_DEVICE_MUSB_SIFLI']):
+ src += Glob('port/musb/usb_dc_musb.c')
+ src += Glob('port/musb/usb_glue_sifli.c')
if GetDepend(['PKG_CHERRYUSB_DEVICE_MUSB_CUSTOM']):
src += Glob('port/musb/usb_dc_musb.c')
if GetDepend(['PKG_CHERRYUSB_DEVICE_CHIPIDEA_MCX']):
@@ -230,6 +233,9 @@ if GetDepend(['PKG_CHERRYUSB_HOST']):
if GetDepend(['PKG_CHERRYUSB_HOST_MUSB_BK']):
src += Glob('port/musb/usb_hc_musb.c')
src += Glob('port/musb/usb_glue_bk.c')
+ if GetDepend(['PKG_CHERRYUSB_HOST_MUSB_SIFLI']):
+ src += Glob('port/musb/usb_hc_musb.c')
+ src += Glob('port/musb/usb_glue_sifli.c')
if GetDepend(['PKG_CHERRYUSB_HOST_MUSB_CUSTOM']):
src += Glob('port/musb/usb_hc_musb.c')
if GetDepend(['PKG_CHERRYUSB_HOST_KINETIS_MCX']):
diff --git a/cherryusb.cmake b/cherryusb.cmake
index ff15d861..3d7c28b3 100644
--- a/cherryusb.cmake
+++ b/cherryusb.cmake
@@ -120,6 +120,9 @@ if(CONFIG_CHERRYUSB_DEVICE)
elseif(CONFIG_CHERRYUSB_DEVICE_MUSB_BK)
list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c)
list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_bk.c)
+ elseif(CONFIG_CHERRYUSB_DEVICE_MUSB_SIFLI)
+ list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c)
+ list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_sifli.c)
elseif(CONFIG_CHERRYUSB_DEVICE_MUSB_CUSTOM)
list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c)
elseif(CONFIG_CHERRYUSB_DEVICE_CHIPIDEA_MCX)
@@ -316,6 +319,9 @@ if(CONFIG_CHERRYUSB_HOST)
elseif(CONFIG_CHERRYUSB_HOST_MUSB_BK)
list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c)
list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_bk.c)
+ elseif(CONFIG_CHERRYUSB_HOST_MUSB_SIFLI)
+ list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c)
+ list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_sifli.c)
elseif(CONFIG_CHERRYUSB_HOST_MUSB_CUSTOM)
list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c)
list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_bk.c)
diff --git a/docs/source/q&a.rst b/docs/source/q&a.rst
index 4692270f..b5c08462 100644
--- a/docs/source/q&a.rst
+++ b/docs/source/q&a.rst
@@ -15,7 +15,7 @@ Q & A
- 是否能进 USB 中断
- 芯片是否带有 cache功能,是否做了 no cache 处理,截图
- 硬件是否正常,是否使用杜邦线连接,如果正常,请说明正常原因
-- 打开 CONFIG_USBDEV_SETUP_LOG_PRINT,并提供 log
+- 配置 **#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG** 并提供 log,仅限商业 IP, 其余 IP 禁止开启 log,否则无法枚举
- 是否流片并销售
其余问题提问模板
diff --git a/port/musb/usb_dc_musb.c b/port/musb/usb_dc_musb.c
index 74234667..01d5cb3a 100644
--- a/port/musb/usb_dc_musb.c
+++ b/port/musb/usb_dc_musb.c
@@ -283,6 +283,13 @@ int usb_dc_init(uint8_t busid)
int usb_dc_deinit(uint8_t busid)
{
+ HWREGB(USB_BASE + MUSB_IE_OFFSET) = 0;
+ HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = 0;
+ HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0;
+
+ HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_SOFTCONN;
+
+ usb_dc_low_level_deinit();
return 0;
}
@@ -345,8 +352,10 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
g_musb_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
g_musb_udc.out_ep[ep_idx].ep_enable = true;
+#ifndef CONFIG_USB_MUSB_SIFLI
USB_ASSERT_MSG((8 << HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET)) >= g_musb_udc.out_ep[ep_idx].ep_mps,
"Ep %02x fifo is overflow", ep->bEndpointAddress);
+#endif
HWREGH(USB_BASE + MUSB_IND_RXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
@@ -394,8 +403,10 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
g_musb_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
g_musb_udc.in_ep[ep_idx].ep_enable = true;
+#ifndef CONFIG_USB_MUSB_SIFLI
USB_ASSERT_MSG((8 << HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET)) >= g_musb_udc.in_ep[ep_idx].ep_mps,
"Ep %02x fifo is overflow", ep->bEndpointAddress);
+#endif
HWREGH(USB_BASE + MUSB_IND_TXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
diff --git a/port/musb/usb_glue_sifli.c b/port/musb/usb_glue_sifli.c
new file mode 100644
index 00000000..106dc3a7
--- /dev/null
+++ b/port/musb/usb_glue_sifli.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2025, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "usbd_core.h"
+#include "usbh_core.h"
+#include "usb_musb_reg.h"
+
+#undef USB_POWER_SOFTCONN
+#undef USB_DEVCTL_FSDEV
+#undef USB_DEVCTL_LSDEV
+#undef USB_DEVCTL_SESSION
+#undef USB_POWER_HSENAB
+#undef USB_POWER_HSMODE
+#undef USB_POWER_RESET
+#undef USB_POWER_RESUME
+
+#ifndef CONFIG_USB_MUSB_SIFLI
+#error must define CONFIG_USB_MUSB_SIFLI when use sunxi chips
+#endif
+
+#include "bf0_hal.h"
+
+uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg)
+{
+ *cfg = NULL; // No FIFO configuration for this implementation, readonly
+ return 0;
+}
+
+uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg)
+{
+ *cfg = NULL; // No FIFO configuration for this implementation, readonly
+ return 0;
+}
+
+uint32_t usb_get_musb_ram_size(void)
+{
+ return 0xFFFF; // No specific RAM size for this implementation
+}
+
+void usbd_musb_delay_ms(uint8_t ms)
+{
+ /* implement later */
+}
+
+#ifdef PKG_CHERRYUSB_DEVICE
+void usb_dc_low_level_init(uint8_t busid)
+{
+ HAL_RCC_EnableModule(RCC_MOD_USBC);
+
+#ifdef SOC_SF32LB58X
+ //hwp_usbc->utmicfg12 = hwp_usbc->utmicfg12 | 0x3; //set xo_clk_sel
+ hwp_usbc->ldo25 = hwp_usbc->ldo25 | 0xa; //set psw_en and ldo25_en
+ HAL_Delay(1);
+ hwp_usbc->swcntl3 = 0x1; //set utmi_en for USB2.0
+ hwp_usbc->usbcfg = hwp_usbc->usbcfg | 0x40; //enable usb PLL.
+#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X)
+ hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN;
+#elif defined(SOC_SF32LB55X)
+ hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN;
+#endif
+#ifndef SOC_SF32LB55X
+ hwp_usbc->usbcfg |= (USB_USBCFG_AVALID | USB_USBCFG_AVALID_DR);
+ hwp_usbc->dpbrxdisl = 0xFE;
+ hwp_usbc->dpbtxdisl = 0xFE;
+#endif
+ NVIC_EnableIRQ(USBC_IRQn);
+ __HAL_SYSCFG_Enable_USB();
+}
+
+void usb_dc_low_level_deinit(uint8_t busid)
+{
+ NVIC_DisableIRQ(USBC_IRQn);
+#ifdef SOC_SF32LB58X
+ hwp_usbc->usbcfg &= ~0x40; // Disable usb PLL.
+ hwp_usbc->swcntl3 = 0x0;
+ hwp_usbc->ldo25 &= ~0xa; // Disable psw_en and ldo25_en
+#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X)
+ hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN);
+#elif defined(SOC_SF32LB55X)
+ hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN);
+#endif
+ /* reset USB to make DP change to PULLDOWN state */
+ hwp_hpsys_rcc->RSTR2 |= HPSYS_RCC_RSTR2_USBC;
+ HAL_Delay_us(100);
+ hwp_hpsys_rcc->RSTR2 &= ~HPSYS_RCC_RSTR2_USBC;
+ HAL_RCC_DisableModule(RCC_MOD_USBC);
+}
+#endif
+
+#ifdef PKG_CHERRYUSB_HOST
+void usb_hc_low_level_init(struct usbh_bus *bus)
+{
+ HAL_RCC_EnableModule(RCC_MOD_USBC);
+
+#ifdef SOC_SF32LB58X
+ //hwp_usbc->utmicfg12 = hwp_usbc->utmicfg12 | 0x3; //set xo_clk_sel
+ hwp_usbc->ldo25 = hwp_usbc->ldo25 | 0xa; //set psw_en and ldo25_en
+ HAL_Delay(1);
+ hwp_usbc->swcntl3 = 0x1; //set utmi_en for USB2.0
+ hwp_usbc->usbcfg = hwp_usbc->usbcfg | 0x40; //enable usb PLL.
+#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X)
+ hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN;
+#elif defined(SOC_SF32LB55X)
+ hwp_hpsys_cfg->USBCR |= HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN;
+#endif
+#ifndef SOC_SF32LB55X
+ hwp_usbc->usbcfg |= (USB_USBCFG_AVALID | USB_USBCFG_AVALID_DR);
+ hwp_usbc->dpbrxdisl = 0xFE;
+ hwp_usbc->dpbtxdisl = 0xFE;
+#endif
+ __HAL_SYSCFG_Enable_USB();
+ hwp_usbc->usbcfg &= 0xEF;
+ hwp_usbc->dbgl = 0x80;
+
+ NVIC_EnableIRQ(USBC_IRQn);
+}
+
+void usb_hc_low_level_deinit(struct usbh_bus *bus)
+{
+ NVIC_DisableIRQ(USBC_IRQn);
+#ifdef SOC_SF32LB58X
+ hwp_usbc->usbcfg &= ~0x40; // Disable usb PLL.
+ hwp_usbc->swcntl3 = 0x0;
+ hwp_usbc->ldo25 &= ~0xa; // Disable psw_en and ldo25_en
+#elif defined(SOC_SF32LB56X) || defined(SOC_SF32LB52X)
+ hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_DP_EN | HPSYS_CFG_USBCR_USB_EN);
+#elif defined(SOC_SF32LB55X)
+ hwp_hpsys_cfg->USBCR &= ~(HPSYS_CFG_USBCR_DM_PD | HPSYS_CFG_USBCR_USB_EN);
+#endif
+ /* reset USB to make DP change to PULLDOWN state */
+ hwp_hpsys_rcc->RSTR2 |= HPSYS_RCC_RSTR2_USBC;
+ HAL_Delay_us(100);
+ hwp_hpsys_rcc->RSTR2 &= ~HPSYS_RCC_RSTR2_USBC;
+ HAL_RCC_DisableModule(RCC_MOD_USBC);
+}
+
+void musb_reset_prev(void)
+{
+#if defined(SF32LB58X)
+ hwp_usbc->rsvd0 = 0xc; //58
+#endif
+}
+
+void musb_reset_post(void)
+{
+#if defined(SF32LB58X)
+ hwp_usbc->rsvd0 = 0x0; //58
+#endif
+}
+#endif
+
+void USBC_IRQHandler(void)
+{
+#ifdef PKG_CHERRYUSB_DEVICE
+ USBD_IRQHandler(0);
+#endif
+#ifdef PKG_CHERRYUSB_HOST
+ USBH_IRQHandler(0);
+#endif
+} \ No newline at end of file
diff --git a/port/musb/usb_hc_musb.c b/port/musb/usb_hc_musb.c
index 3de4ef36..9111177a 100644
--- a/port/musb/usb_hc_musb.c
+++ b/port/musb/usb_hc_musb.c
@@ -429,9 +429,18 @@ static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port)
{
g_musb_hcd[bus->hcd.hcd_id].port_pe = 0;
HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_RESET;
+
+#ifdef CONFIG_USB_MUSB_SIFLI
+ extern void musb_reset_prev(void);
+ musb_reset_prev();
+#endif
usb_osal_msleep(20);
HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~(USB_POWER_RESET);
usb_osal_msleep(20);
+#ifdef CONFIG_USB_MUSB_SIFLI
+ extern void musb_reset_post(void);
+ musb_reset_post();
+#endif
g_musb_hcd[bus->hcd.hcd_id].port_pe = 1;
return 0;
}