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authorsakumisu <[email protected]>2024-03-29 15:25:23 +0800
committersakumisu <[email protected]>2024-03-29 15:31:29 +0800
commite7616399b72f63226e657a815176d29b10a29d34 (patch)
tree4ab1cb6d032d7d97174be37168944e48d4ddca3d
parenta21947ff221bd133017204aa599de8aaf3ea65b1 (diff)
add hpm5000 macro
-rw-r--r--third_party/rt-thread-5.0/dfs_usbh_msc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/third_party/rt-thread-5.0/dfs_usbh_msc.c b/third_party/rt-thread-5.0/dfs_usbh_msc.c
index b3cedb36..145bf05d 100644
--- a/third_party/rt-thread-5.0/dfs_usbh_msc.c
+++ b/third_party/rt-thread-5.0/dfs_usbh_msc.c
@@ -11,7 +11,7 @@
#endif
#if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || \
- defined(SOC_HPM6000) || defined(BSP_USING_BL61X)
+ defined(SOC_HPM5000) || defined(SOC_HPM6000) || defined(BSP_USING_BL61X)
#ifndef RT_USING_CACHE
#error usbh msc must enable RT_USING_CACHE in this chip
#endif
@@ -31,7 +31,7 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
bflb_l1c_dcache_invalidate_range(addr, size);
}
}
-#elif defined(SOC_HPM6000)
+#elif defined(SOC_HPM5000) || defined(SOC_HPM6000)
#include "hpm_l1c_drv.h"
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)