feat(port/renesas): support renesas device

Signed-off-by: sakumisu <[email protected]>

15 files changed, 3756 insertions, 0 deletions

diff --git a/Kconfig b/Kconfig
index 272d5454..ad48c93e 100644
--- a/Kconfig
+++ b/Kconfig
@@ -76,6 +76,8 @@ if CHERRYUSB
                 bool "aic"
             config CHERRYUSB_DEVICE_RP2040
                 bool "rp2040"
+            config CHERRYUSB_DEVICE_RENESAS
+                bool "renesas"
             config CHERRYUSB_DEVICE_CH32
                 bool "ch32"
             config CHERRYUSB_DEVICE_PUSB2
diff --git a/Kconfig.rtt b/Kconfig.rtt
index 0cbb76d9..62da4e34 100644
--- a/Kconfig.rtt
+++ b/Kconfig.rtt
@@ -76,6 +76,8 @@ if RT_USING_CHERRYUSB
                 bool "aic"
             config RT_CHERRYUSB_DEVICE_RP2040
                 bool "rp2040"
+            config RT_CHERRYUSB_DEVICE_RENESAS
+                bool "renesas"
             config RT_CHERRYUSB_DEVICE_CH32
                 bool "ch32"
             config RT_CHERRYUSB_DEVICE_PUSB2
diff --git a/Kconfig.rttpkg b/Kconfig.rttpkg
index 12e3f2e0..0f534a9f 100644
--- a/Kconfig.rttpkg
+++ b/Kconfig.rttpkg
@@ -77,6 +77,8 @@ if PKG_USING_CHERRYUSB
                 bool "aic"
             config PKG_CHERRYUSB_DEVICE_RP2040
                 bool "rp2040"
+            config PKG_CHERRYUSB_DEVICE_RENESAS
+                bool "renesas"
             config PKG_CHERRYUSB_DEVICE_CH32
                 bool "ch32"
             config PKG_CHERRYUSB_DEVICE_PUSB2
diff --git a/SConscript b/SConscript
index ca0ac083..3d957e79 100644
--- a/SConscript
+++ b/SConscript
@@ -100,6 +100,9 @@ if GetDepend(['PKG_CHERRYUSB_DEVICE']):
     if GetDepend(['PKG_CHERRYUSB_DEVICE_AIC']):
         src += Glob('port/aic/usb_dc_aic.c')
         src += Glob('port/aic/usb_dc_aic_ll.c')
+    if GetDepend(['PKG_CHERRYUSB_DEVICE_RENESAS']):
+        src += Glob('port/renesas/device/r_usb_device.c')
+        src += Glob('port/renesas/device/usb_dc_rensas.c')
     if GetDepend(['PKG_CHERRYUSB_DEVICE_CH32']):
         if GetDepend(['PKG_CHERRYUSB_DEVICE_HS']):
             src += Glob('port/ch32/usb_dc_usbhs.c')
diff --git a/port/renesas/README.md b/port/renesas/README.md
new file mode 100644
index 00000000..709b2aa6
--- /dev/null
+++ b/port/renesas/README.md
@@ -0,0 +1,15 @@
+# Note
+
+Refer to https://github.com/zephyrproject-rtos/hal_renesas
+
+- Make sure usb interrupts exist in RASC.
+
+![rasc](rasc_config.png)
+
+- Remove all fsp usb source code. Otherwise you will build fail with multi function definitions.
+
+![usb_code](usb_code.png)
+
+## Support Chip List
+
+- RA
\ No newline at end of file
diff --git a/port/renesas/device/r_usb_api.h b/port/renesas/device/r_usb_api.h
new file mode 100644
index 00000000..74633611
--- /dev/null
+++ b/port/renesas/device/r_usb_api.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef R_USB_API_H
+#define R_USB_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Descriptor type  Define */
+#define USB_DT_DEVICE              (0x01U) /* Device Descriptor */
+#define USB_DT_CONFIGURATION       (0x02U) /* Configuration Descriptor */
+#define USB_DT_STRING              (0x03U) /* String Descriptor */
+#define USB_DT_INTERFACE           (0x04U) /* Interface Descriptor */
+#define USB_DT_ENDPOINT            (0x05U) /* Endpoint Descriptor */
+#define USB_DT_DEVICE_QUALIFIER    (0x06U) /* Device Qualifier Descriptor */
+#define USB_DT_OTHER_SPEED_CONF    (0x07U) /* Other Speed Configuration Descriptor */
+#define USB_DT_INTERFACE_POWER     (0x08U) /* Interface Power Descriptor */
+#define USB_DT_OTGDESCRIPTOR       (0x09U) /* OTG Descriptor */
+#define USB_DT_HUBDESCRIPTOR       (0x29U) /* HUB descriptor */
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** USB request type */
+typedef enum e_usb_request_type
+{
+    USB_REQ_TYPE_STANDARD = 0,
+    USB_REQ_TYPE_CLASS,
+    USB_REQ_TYPE_VENDOR,
+    USB_REQ_TYPE_INVALID
+} usb_request_type_t;
+
+/** USB request recipient */
+typedef enum e_usb_request_recipient
+{
+    USB_REQ_RCPT_DEVICE = 0,
+    USB_REQ_RCPT_INTERFACE,
+    USB_REQ_RCPT_ENDPOINT,
+    USB_REQ_RCPT_OTHER
+} usb_request_recipient_t;
+
+/** USB Endpoint Descriptor */
+typedef __PACKED_STRUCT st_usb_desc_endpoint
+{
+    uint8_t bLength;                   /*  Size of this descriptor in bytes */
+    uint8_t bDescriptorType;           /*  ENDPOINT Descriptor Type */
+    uint8_t bEndpointAddress;          /*  The address of the endpoint */
+
+    __PACKED_STRUCT
+    {
+        uint8_t xfer  : 2;             /*  Control, ISO, Bulk, Interrupt */
+        uint8_t sync  : 2;             /*  None, Asynchronous, Adaptive, Synchronous */
+        uint8_t usage : 2;             /*  Data, Feedback, Implicit feedback */
+        uint8_t       : 2;
+    } bmAttributes;
+
+    uint16_t wMaxPacketSize;           /*  Bit 10..0 : max packet size, bit 12..11 additional transaction per highspeed micro-frame */
+    uint8_t bInterval;                 /*  Polling interval, in frames or microframes depending on the operating speed */
+} usb_desc_endpoint_t;
+
+/** USB xfer type */
+typedef enum e_usb_xfer_type
+{
+    USB_XFER_CONTROL = 0,
+    USB_XFER_ISOCHRONOUS,
+    USB_XFER_BULK,
+    USB_XFER_INTERRUPT
+} usb_xfer_type_t;
+
+/** USB endpoint direction */
+typedef enum e_usb_dir
+{
+    USB_DIR_OUT     = 0,
+    USB_DIR_IN      = 1,
+    USB_DIR_IN_MASK = 0x80
+} usb_dir_t;
+
+/** USB speed */
+typedef enum e_usb_speed
+{
+    USB_SPEED_LS = 0,                  /* Low speed operation */
+    USB_SPEED_FS,                      /* Full speed operation */
+    USB_SPEED_HS,                      /* Hi speed operation */
+    USB_SPEED_INVALID,
+} usb_speed_t;
+
+/** USB xfer result */
+typedef enum e_usb_xfer_result
+{
+    USB_XFER_RESULT_SUCCESS = 0,
+    USB_XFER_RESULT_FAILED,
+    USB_XFER_RESULT_STALLED,
+    USB_XFER_RESULT_TIMEOUT,
+    USB_XFER_RESULT_INVALID
+} usb_xfer_result_t;
+
+#endif /* R_USB_API_H */
\ No newline at end of file
diff --git a/port/renesas/device/r_usb_device.c b/port/renesas/device/r_usb_device.c
new file mode 100644
index 00000000..c0c690e5
--- /dev/null
+++ b/port/renesas/device/r_usb_device.c
@@ -0,0 +1,2228 @@
+/*
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_usb_device.h"
+#include "r_usb_device_define.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define LITTLE_ENDIAN         0
+#define BIG_ENDIAN            1
+#define BYTE_ORDER           LITTLE_ENDIAN
+
+#define USBD_OPEN             (0x55534244) /* USBD in ASCII */
+
+#define USB_EP_DIR_Msk        (0x80UL)
+#define USB_EP_IN_DIR         (0x80UL)
+#define USB_EP_OUT_DIR        (0UL)
+
+#define USB_EP_IDX_Msk        (0x7FUL)
+#define USB_EP_CONTROL_IN     (0x80UL)
+#define USB_EP_CONTROL_OUT    (0UL)
+
+#define USB_GET_EP_DIR(ep_addr)      (ep_addr & USB_EP_DIR_Msk)
+#define USB_GET_EP_IDX(ep_addr)      (ep_addr & USB_EP_IDX_Msk)
+#define USB_GET_EP_ADDR(idx, dir)    ((idx & USB_EP_IDX_Msk) | (dir & USB_EP_DIR_Msk))
+
+#define USB_PIPECFG_DIR_IDX(dir)     ((dir == USB_EP_IN_DIR) ? 1 : 0)
+
+#define USB_HIGHSPEED_MPS_Msk           (0x7ffUL)
+#define USB_FULLSPEED_MPS_Msk           (0x1ffUL)
+
+#define USB_XFER_TYPE_CONTROL           (0)
+#define USB_XFER_TYPE_ISO               (1)
+#define USB_XFER_TYPE_BULK              (2)
+#define USB_XFER_TYPE_INT               (3)
+
+#define USB_REQUEST_TYPE_SET_ADDRESS    (0x0500)
+
+/* TODO: BUFNMB should be changed depending on the allocation scheme */
+#define R_USB_PIPEBUF_FIXED             (0x7C08) /* Fixed Pipe Buffer configurations */
+
+/***********************************************************************************************************************
+ * Private constants
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+typedef struct st_pipe_state
+{
+    void   * buf;                      /* the start address of a transfer data buffer */
+    uint16_t length;                   /* the number of bytes in the buffer */
+    uint16_t remaining;                /* the number of bytes remaining in the buffer */
+    uint8_t  ep;                       /* an assigned endpoint address */
+} pipe_state_t;
+
+typedef struct st_usb_pipe_cfg
+{
+    pipe_state_t pipe[10];
+    uint8_t      ep[2][16];            /* a lookup table for a pipe index from an endpoint address */
+} usb_pipe_cfg_t;
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static inline uint16_t min16 (uint16_t x, uint16_t y) {
+    return (x < y) ? x : y;
+}
+
+static inline uint32_t get_first_bit1_offset (uint32_t s) {
+    return __builtin_ctz(s);
+}
+
+static void            process_control_status(usbd_instance_ctrl_t * p_ctrl);
+static inline uint16_t get_edpt_packet_size(usbd_instance_ctrl_t * const p_ctrl,
+                                            usbd_desc_endpoint_t const * p_desc_ep);
+static uint32_t                   find_pipe(usbd_instance_ctrl_t * const p_ctrl, uint32_t xfer_type);
+static inline volatile uint16_t * get_pipectr(usbd_instance_ctrl_t * const p_ctrl, uint32_t num);
+static volatile void *            get_pipetre(usbd_instance_ctrl_t * const p_ctrl, uint32_t num);
+static inline uint16_t            edpt0_max_packet_size(usbd_instance_ctrl_t * const p_ctrl);
+static inline uint16_t            edpt_max_packet_size(usbd_instance_ctrl_t * const p_ctrl, uint32_t num);
+static inline void                pipe_wait_for_ready(usbd_instance_ctrl_t * const p_ctrl, uint32_t num);
+static inline void                pipe_write_packet(usbd_instance_ctrl_t * const p_ctrl,
+                                                    void                       * buf,
+                                                    volatile void              * fifo,
+                                                    unsigned int                 len);
+static inline void pipe_read_packet(usbd_instance_ctrl_t * const p_ctrl,
+                                    void                       * buf,
+                                    volatile void              * fifo,
+                                    unsigned int                 len);
+static inline bool      pipe0_xfer_in(usbd_instance_ctrl_t * const p_ctrl);
+static inline bool      pipe0_xfer_out(usbd_instance_ctrl_t * const p_ctrl);
+static inline bool      pipe_xfer_in(usbd_instance_ctrl_t * const p_ctrl, uint8_t num);
+static inline bool      pipe_xfer_out(usbd_instance_ctrl_t * const p_ctrl, uint8_t num);
+static void             r_usb_device_call_callback(usbd_instance_ctrl_t * const p_ctrl, usbd_event_t * event);
+static inline void      process_setup_packet(usbd_instance_ctrl_t * const p_ctrl);
+static inline fsp_err_t process_pipe0_xfer(usbd_instance_ctrl_t * const p_ctrl,
+                                           uint8_t                      ep_addr,
+                                           void                       * buffer,
+                                           uint16_t                     total_bytes);
+static inline fsp_err_t process_pipe_xfer(usbd_instance_ctrl_t * const p_ctrl,
+                                          uint8_t                      ep_addr,
+                                          void                       * buffer,
+                                          uint16_t                     total_bytes);
+static inline void process_pipe_forced_termination(usbd_instance_ctrl_t * const p_ctrl, uint8_t ep);
+static inline void process_pipe0_bemp(usbd_instance_ctrl_t * const p_ctrl);
+static inline void process_pipe_brdy(usbd_instance_ctrl_t * const p_ctrl, uint32_t num);
+static inline void process_bus_reset(usbd_instance_ctrl_t * const p_ctrl);
+static inline void process_set_address(usbd_instance_ctrl_t * const p_ctrl);
+static inline void physical_init(usbd_instance_ctrl_t * const p_ctrl, usbd_cfg_t const * const p_cfg);
+static inline void control_pipe_setup(usbd_instance_ctrl_t * const p_ctrl);
+static inline void usb_interrupt_configure(usbd_instance_ctrl_t * p_ctrl, usbd_cfg_t const * p_cfg);
+static inline void usb_module_start(usbd_instance_ctrl_t * p_ctrl);
+static inline void usb_module_stop(usbd_instance_ctrl_t * p_ctrl);
+static inline void usb_disable_interrupt(usbd_instance_ctrl_t * p_ctrl);
+static inline void usb_enable_interrupt(usbd_instance_ctrl_t * p_ctrl);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+static usb_pipe_cfg_t g_pipe_cfg[USB_NUM_USBIP];
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/**
+ * @brief Start USB module, configure correct operate mode and default pipe0
+ *
+ * @param p_api_ctrl
+ * @param p_cfg
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_Open (usbd_ctrl_t * const p_api_ctrl, usbd_cfg_t const * const p_cfg)
+{
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ASSERT(p_cfg);
+    FSP_ERROR_RETURN(0 == p_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
+    /* Make sure this channel exists. */
+    FSP_ERROR_RETURN(USB_NUM_USBIP > p_cfg->module_number, FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+
+    /* USBFS module only support FS operation */
+    if (USB_IP0_MODULE == p_cfg->module_number)
+    {
+        FSP_ERROR_RETURN((USBD_SPEED_FS == p_cfg->usb_speed), FSP_ERR_INVALID_ARGUMENT);
+    }
+
+    /* USBHS module only support FS/HS operation */
+    if (USB_IP1_MODULE == p_cfg->module_number)
+    {
+        FSP_ERROR_RETURN((USBD_SPEED_FS == p_cfg->usb_speed) || (USBD_SPEED_HS == p_cfg->usb_speed),
+                         FSP_ERR_INVALID_ARGUMENT);
+    }
+#endif
+
+#ifdef USB_HIGH_SPEED_MODULE
+    p_ctrl->p_reg = (void *) (USB_IS_USBHS(p_cfg->module_number) ? R_USB_HS0_BASE : R_USB_FS0_BASE);
+#else
+    p_ctrl->p_reg = (void *) R_USB_FS0_BASE;
+#endif
+    p_ctrl->p_cfg             = p_cfg;
+    p_ctrl->p_callback        = p_cfg->p_callback;
+    p_ctrl->p_context         = p_cfg->p_context;
+    p_ctrl->p_callback_memory = NULL;
+
+    /* clear pipe config */
+    memset(&g_pipe_cfg[p_cfg->module_number], 0, sizeof(usb_pipe_cfg_t));
+
+    /* module start */
+    usb_module_start(p_ctrl);
+
+    /* physical layer init */
+    physical_init(p_ctrl, p_cfg);
+
+    /* setup default control pipe */
+    control_pipe_setup(p_ctrl);
+
+    /* enable interrupt */
+    usb_interrupt_configure(p_ctrl, p_cfg);
+
+    p_ctrl->open = USBD_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Shutdown USB device
+ *
+ * @param p_api_ctrl
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_Close (usbd_ctrl_t * const p_api_ctrl)
+{
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* disable interrupt */
+    usb_disable_interrupt(p_ctrl);
+
+    /* module stop */
+    usb_module_stop(p_ctrl);
+
+    p_ctrl->open = 0;
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Connect USB D+/D- pin to the USB data bus
+ *
+ * @param p_api_ctrl
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_Connect (usbd_ctrl_t * const p_api_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+#else
+    FSP_PARAMETER_NOT_USED(p_api_ctrl);
+#endif
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->SYSCFG_b.CNEN  = 1;
+        R_USB_HS0->SYSCFG_b.DPRPU = 1;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->SYSCFG_b.DPRPU = 1;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Disconnect pin D+/D- to USB data bus
+ *
+ * @param p_api_ctrl
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_Disconnect (usbd_ctrl_t * const p_api_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+#else
+    FSP_PARAMETER_NOT_USED(p_api_ctrl);
+#endif
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->SYSCFG_b.DPRPU = 0;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->SYSCFG_b.DPRPU = 0;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Configure an endpoint to make it ready to transfer
+ *
+ * @param p_api_ctrl
+ * @param p_ep_desc
+ *
+ * @retval FSP_SUCCESS          on success
+ * @retval FSP_ERR_USB_BUSY     if these is no available pipe can be used with this endpoint
+ */
+fsp_err_t R_USBD_EdptOpen (usbd_ctrl_t * const p_api_ctrl, usbd_desc_endpoint_t const * p_ep_desc)
+{
+    usbd_instance_ctrl_t * const p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ASSERT(p_ep_desc);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    const uint8_t  ep_addr = p_ep_desc->bEndpointAddress;
+    const uint8_t  epn     = USB_GET_EP_IDX(ep_addr);
+    const uint8_t  dir     = USB_GET_EP_DIR(ep_addr);
+    const uint8_t  xfer    = p_ep_desc->Attributes.xfer;
+    const uint32_t num     = find_pipe(p_ctrl, xfer);
+
+    /* There are no available pipes that can be configured for this endpoint. */
+    FSP_ERROR_RETURN(0 != num, FSP_ERR_USB_BUSY);
+
+    g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[num].ep = ep_addr;
+    g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][epn] = num;
+
+    /* setup pipe */
+    usb_disable_interrupt(p_ctrl);
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->PIPEBUF  = R_USB_PIPEBUF_FIXED;
+        R_USB_HS0->PIPESEL  = num;
+        R_USB_HS0->PIPEMAXP = get_edpt_packet_size(p_ctrl, p_ep_desc);
+    }
+    else
+#endif
+    {
+        R_USB_FS0->PIPESEL  = num;
+        R_USB_FS0->PIPEMAXP = get_edpt_packet_size(p_ctrl, p_ep_desc);
+    }
+
+    volatile uint16_t * ctr = get_pipectr(p_api_ctrl, num);
+    *ctr = R_USB_PIPE_CTR_ACLRM_Msk | R_USB_PIPE_CTR_SQCLR_Msk;
+    *ctr = 0;
+
+    uint16_t cfg = (USB_PIPECFG_DIR_IDX(dir) << R_USB_PIPECFG_DIR_Pos) | epn;
+
+    if (xfer == USB_XFER_TYPE_BULK)
+    {
+        cfg |= (R_USB_PIPECFG_TYPE_BULK | R_USB_PIPECFG_SHTNAK_Msk | R_USB_PIPECFG_DBLB_Msk);
+    }
+    else if (xfer == USB_XFER_TYPE_INT)
+    {
+        cfg |= R_USB_PIPECFG_TYPE_INT;
+    }
+    else
+    {
+        cfg |= (R_USB_PIPECFG_TYPE_ISO | R_USB_PIPECFG_DBLB_Msk);
+    }
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->PIPECFG  = cfg;
+        R_USB_HS0->BRDYSTS  = R_USB_BRDYSTS_PIPEBRDY_Msk ^ (1 << num);
+        R_USB_HS0->BRDYENB |= (1 << num);
+    }
+    else
+#endif
+    {
+        R_USB_FS0->PIPECFG  = cfg;
+        R_USB_FS0->BRDYSTS  = R_USB_BRDYSTS_PIPEBRDY_Msk ^ (1 << num);
+        R_USB_FS0->BRDYENB |= (1 << num);
+    }
+
+    if ((USB_EP_IN_DIR == dir) || (USB_XFER_TYPE_BULK != xfer))
+    {
+        *ctr = R_USB_PIPE_CTR_PID_BUF;
+    }
+
+    usb_enable_interrupt(p_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Remove configuration for an endpoint
+ *
+ * @param p_api_ctrl
+ * @param ep_addr
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_EdptClose (usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr)
+{
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    const uint8_t epn = USB_GET_EP_IDX(ep_addr);
+    const uint8_t dir = USB_GET_EP_DIR(ep_addr);
+    const uint8_t num = g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][epn];
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        volatile uint16_t * ctr = get_pipectr(p_ctrl, num);
+
+        R_USB_HS0->BRDYENB &= ~(1 << num);
+        *ctr                = 0;
+        R_USB_HS0->PIPESEL  = num;
+        R_USB_HS0->PIPECFG  = 0;
+    }
+    else
+#endif
+    {
+        volatile uint16_t * ctr = get_pipectr(p_ctrl, num);
+
+        R_USB_FS0->BRDYENB &= ~(1 << num);
+        *ctr                = 0;
+        R_USB_FS0->PIPESEL  = num;
+        R_USB_FS0->PIPECFG  = 0;
+    }
+
+    g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[num].ep = 0;
+    g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][epn] = 0;
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Wake up host
+ *
+ * @param p_api_ctrl
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_RemoteWakeup (usbd_ctrl_t * const p_api_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+#else
+    FSP_PARAMETER_NOT_USED(p_api_ctrl);
+#endif
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->DVSTCTR0_b.WKUP = 1;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->DVSTCTR0_b.WKUP = 1;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Trigger an endpoint transfer
+ *
+ * @param p_api_ctrl
+ * @param ep_addr
+ * @param buffer
+ * @param total_bytes
+ *
+ * @retval FSP_SUCCESS              on success
+ * @retval FSP_ERR_USB_NOT_OPEN     if input endpoint has not opened yet
+ */
+fsp_err_t R_USBD_XferStart (usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+    fsp_err_t              err    = FSP_SUCCESS;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    usb_disable_interrupt(p_ctrl);
+
+    if (USB_GET_EP_IDX(ep_addr) > 0)
+    {
+        err = process_pipe_xfer(p_api_ctrl, ep_addr, buffer, total_bytes);
+    }
+    else
+    {
+        err = process_pipe0_xfer(p_api_ctrl, ep_addr, buffer, total_bytes);
+    }
+
+    usb_enable_interrupt(p_ctrl);
+
+    return err;
+}
+
+/**
+ * @brief Abort on-going transfer
+ *
+ * @param p_api_ctrl
+ * @param ep_addr
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_XferAbort (usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr)
+{
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    usb_disable_interrupt(p_ctrl);
+
+    process_pipe_forced_termination(p_ctrl, ep_addr);
+
+    usb_enable_interrupt(p_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Set a endpoint to halt and send a stall packet
+ *
+ * @param p_api_ctrl
+ * @param ep_addr
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_EdptStall (usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr)
+{
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    usb_disable_interrupt(p_ctrl);
+
+    const uint8_t       epn     = USB_GET_EP_IDX(ep_addr);
+    const uint8_t       dir     = USB_GET_EP_DIR(ep_addr);
+    const uint8_t       num     = g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][epn];
+    volatile uint16_t * pipectr = get_pipectr(p_api_ctrl, num);
+    const uint16_t      pid     = *pipectr & R_USB_PIPE_CTR_PID_Msk;
+
+    *pipectr = pid | R_USB_PIPE_CTR_PID_STALL;
+    *pipectr = R_USB_PIPE_CTR_PID_STALL;
+
+    usb_enable_interrupt(p_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/**
+ * @brief Reset halt state of an endpoint
+ *
+ * @param p_api_ctrl
+ * @param ep_addr
+ *
+ * @retval FSP_SUCCESS on success
+ */
+fsp_err_t R_USBD_EdptClearStall (usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr)
+{
+    usbd_instance_ctrl_t * p_ctrl = (usbd_instance_ctrl_t *) p_api_ctrl;
+
+#if USBD_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ctrl);
+    FSP_ERROR_RETURN(0 != p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    usb_disable_interrupt(p_ctrl);
+
+    const uint8_t       epn     = USB_GET_EP_IDX(ep_addr);
+    const uint8_t       dir     = USB_GET_EP_DIR(ep_addr);
+    const uint8_t       num     = g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][epn];
+    volatile uint16_t * pipectr = get_pipectr(p_api_ctrl, num);
+
+    *pipectr = R_USB_PIPE_CTR_SQCLR_Msk;
+    if (USB_EP_IN_DIR == dir)
+    {
+        *pipectr = R_USB_PIPE_CTR_PID_BUF;
+    }
+    else
+    {
+#ifdef USB_HIGH_SPEED_MODULE
+        if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+        {
+            R_USB_HS0->PIPESEL = num;
+            if (R_USB_HS0->PIPECFG_b.TYPE != 1)
+            {
+                *pipectr = R_USB_PIPE_CTR_PID_BUF;
+            }
+        }
+        else
+#endif
+        {
+            R_USB_FS0->PIPESEL = num;
+            if (R_USB_FS0->PIPECFG_b.TYPE != 1)
+            {
+                *pipectr = R_USB_PIPE_CTR_PID_BUF;
+            }
+        }
+    }
+
+    usb_enable_interrupt(p_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/**********************************************************************************************************************
+ * Private functions
+ **********************************************************************************************************************/
+
+/* get the mps from an EP descriptor */
+static inline uint16_t get_edpt_packet_size (usbd_instance_ctrl_t * const p_ctrl,
+                                             usbd_desc_endpoint_t const * p_desc_ep)
+{
+    uint16_t mps = 0;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (p_ctrl->p_cfg->usb_speed == USBD_SPEED_HS)
+    {
+        mps = p_desc_ep->wMaxPacketSize & USB_HIGHSPEED_MPS_Msk;
+    }
+    else
+#endif
+    {
+        mps = p_desc_ep->wMaxPacketSize & USB_FULLSPEED_MPS_Msk;
+    }
+
+    return mps;
+}
+
+/* get the available pipe can be used to configure for new endpoint */
+static uint32_t find_pipe (usbd_instance_ctrl_t * const p_ctrl, uint32_t xfer_type)
+{
+    const uint8_t pipe_idx_arr[4][2] =
+    {
+        {0, 0},                        // Control
+        {1, 2},                        // Isochronous
+        {1, 5},                        // Bulk
+        {6, 9},                        // Interrupt
+    };
+
+    /* find backward since only pipe 1, 2 support ISO */
+    const uint8_t idx_first = pipe_idx_arr[xfer_type][0];
+    const uint8_t idx_last  = pipe_idx_arr[xfer_type][1];
+
+    for (int i = idx_last; i >= idx_first; i--)
+    {
+        if (0 == g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[i].ep)
+        {
+            return i;
+        }
+    }
+
+    return 0;
+}
+
+/* get the correct PIPE_CTR register by the pipe number */
+static inline volatile uint16_t * get_pipectr (usbd_instance_ctrl_t * const p_ctrl, uint32_t num)
+{
+    volatile uint16_t * pipectr = NULL;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        if (0 != num)
+        {
+            pipectr = &R_USB_HS0->PIPE_CTR[num - 1];
+        }
+        else
+        {
+            pipectr = &R_USB_HS0->DCPCTR;
+        }
+    }
+    else
+#endif
+    {
+        if (0 != num)
+        {
+            pipectr = &R_USB_FS0->PIPE_CTR[num - 1];
+        }
+        else
+        {
+            pipectr = &R_USB_FS0->DCPCTR;
+        }
+    }
+
+    return pipectr;
+}
+
+/* get the correct PIPE_TR by the pipe number */
+static volatile void * get_pipetre (usbd_instance_ctrl_t * const p_ctrl, uint32_t num)
+{
+    volatile void * pipetre = NULL;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        pipetre = (1 <= num) && (num <= 5) ? &(R_USB_HS0->PIPE_TR[num - 1].E) : NULL;
+    }
+    else
+#endif
+    {
+        pipetre = (1 <= num) && (num <= 5) ? &(R_USB_FS0->PIPE_TR[num - 1].E) : NULL;
+    }
+
+    return pipetre;
+}
+
+/* get the mps of pipe0 */
+static inline uint16_t edpt0_max_packet_size (usbd_instance_ctrl_t * const p_ctrl)
+{
+    uint16_t mps = 0;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        mps = R_USB_HS0->DCPMAXP_b.MXPS;
+    }
+    else
+#endif
+    {
+        mps = R_USB_FS0->DCPMAXP_b.MXPS;
+    }
+
+    return mps;
+}
+
+/* get the mps of common endpoint */
+static inline uint16_t edpt_max_packet_size (usbd_instance_ctrl_t * const p_ctrl, uint32_t num)
+{
+    uint16_t mps = 0;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->PIPESEL = num;
+
+        mps = R_USB_HS0->PIPEMAXP;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->PIPESEL = num;
+
+        mps = R_USB_FS0->PIPEMAXP;
+    }
+
+    return mps;
+}
+
+/* wait for pipe to be ready */
+static inline void pipe_wait_for_ready (usbd_instance_ctrl_t * const p_ctrl, uint32_t num)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        FSP_HARDWARE_REGISTER_WAIT(R_USB_HS0->D0FIFOSEL_b.CURPIPE, num);
+        FSP_HARDWARE_REGISTER_WAIT(R_USB_HS0->D0FIFOCTR_b.FRDY, 1);
+    }
+    else
+#endif
+    {
+        FSP_HARDWARE_REGISTER_WAIT(R_USB_FS0->D0FIFOSEL_b.CURPIPE, num);
+        FSP_HARDWARE_REGISTER_WAIT(R_USB_FS0->D0FIFOCTR_b.FRDY, 1);
+    }
+}
+
+/* write data buffer --> hw fifo */
+static inline void pipe_write_packet (usbd_instance_ctrl_t * const p_ctrl,
+                                      void                       * buf,
+                                      volatile void              * fifo,
+                                      unsigned int                 len)
+{
+    volatile uint16_t * ff16;
+    volatile uint8_t  * ff8;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        /* Highspeed FIFO is 32-bit */
+        ff16 = (volatile uint16_t *) ((uintptr_t) fifo + 2);
+        ff8  = (volatile uint8_t *) ((uintptr_t) fifo + 3);
+    }
+    else
+#endif
+    {
+        ff16 = (volatile uint16_t *) fifo;
+        ff8  = ((volatile uint8_t *) fifo);
+    }
+
+    uint8_t const * buf8 = (uint8_t const *) buf;
+
+    while (len >= 2)
+    {
+        *ff16 = *(uint16_t *) (buf8);
+        buf8 += 2;
+        len  -= 2;
+    }
+
+    if (len > 0)
+    {
+        *ff8 = *buf8;
+        ++buf8;
+    }
+}
+
+/* read data buffer <-- hw fifo */
+static inline void pipe_read_packet (usbd_instance_ctrl_t * const p_ctrl,
+                                     void                       * buf,
+                                     volatile void              * fifo,
+                                     unsigned int                 len)
+{
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    uint8_t          * p_buf = (uint8_t *) buf;
+    volatile uint8_t * reg   = (volatile uint8_t *) fifo; /* byte access is always at base register address */
+
+    while (len--)
+    {
+        *p_buf++ = *reg;
+    }
+}
+
+/* process IN direction transfer through pipe0 */
+static inline bool pipe0_xfer_in (usbd_instance_ctrl_t * const p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    bool                hs_module = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile void     * cfifo     = hs_module ? &R_USB_HS0->CFIFO : &R_USB_FS0->CFIFO;
+    volatile uint16_t * cfifoctr  = hs_module ? &R_USB_HS0->CFIFOCTR : &R_USB_FS0->CFIFOCTR;
+#else
+    volatile void     * cfifo    = &R_USB_FS0->CFIFO;
+    volatile uint16_t * cfifoctr = &R_USB_FS0->CFIFOCTR;
+#endif
+
+    pipe_state_t * pipe = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[0];
+    const uint16_t rem  = pipe->remaining;
+
+    if (0 == rem)
+    {
+        pipe->buf = NULL;
+
+        return true;
+    }
+
+    const uint16_t mps = edpt0_max_packet_size(p_ctrl);
+    const uint16_t len = min16(mps, rem);
+    void         * buf = pipe->buf;
+
+    if (len)
+    {
+        pipe_write_packet(p_ctrl, buf, cfifo, len);
+        pipe->buf = (uint8_t *) buf + len;
+    }
+
+    if (len < mps)
+    {
+        *cfifoctr = R_USB_CFIFOCTR_BVAL_Msk;
+    }
+
+    pipe->remaining = rem - len;
+
+    return false;
+}
+
+/* process OUT direction transfer through pipe0 */
+static inline bool pipe0_xfer_out (usbd_instance_ctrl_t * const p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    bool                hs_module = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile void     * cfifo     = hs_module ? &R_USB_HS0->CFIFO : &R_USB_FS0->CFIFO;
+    volatile uint16_t * cfifoctr  = hs_module ? &R_USB_HS0->CFIFOCTR : &R_USB_FS0->CFIFOCTR;
+#else
+    volatile void     * cfifo    = &R_USB_FS0->CFIFO;
+    volatile uint16_t * cfifoctr = &R_USB_FS0->CFIFOCTR;
+#endif
+
+    pipe_state_t * pipe = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[0];
+    const uint16_t rem  = pipe->remaining;
+    const uint16_t mps  = edpt0_max_packet_size(p_ctrl);
+#ifdef USB_HIGH_SPEED_MODULE
+    const uint16_t vld = hs_module ? R_USB_HS0->CFIFOCTR_b.DTLN : R_USB_FS0->CFIFOCTR_b.DTLN;
+#else
+    const uint16_t vld = R_USB_FS0->CFIFOCTR_b.DTLN;
+#endif
+    const uint16_t len = min16(min16(rem, mps), vld);
+    void         * buf = pipe->buf;
+
+    if (len)
+    {
+        pipe_read_packet(p_ctrl, buf, cfifo, len);
+        pipe->buf = (uint8_t *) buf + len;
+    }
+
+    if (len < mps)
+    {
+        *cfifoctr = R_USB_CFIFOCTR_BCLR_Msk;
+    }
+
+    pipe->remaining = rem - len;
+    if ((len < mps) || (rem == len))
+    {
+        pipe->buf = NULL;
+
+        return true;
+    }
+
+    return false;
+}
+
+/* process IN direction transfer for common pipe */
+static inline bool pipe_xfer_in (usbd_instance_ctrl_t * const p_ctrl, uint8_t num)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    bool                hs_module = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile uint16_t * d0fifosel = hs_module ? &R_USB_HS0->D0FIFOSEL : &R_USB_FS0->D0FIFOSEL;
+    volatile void     * d0fifo    = hs_module ? &R_USB_HS0->D0FIFO : &R_USB_FS0->D0FIFO;
+    volatile uint16_t * d0fifoctr = hs_module ? &R_USB_HS0->D0FIFOCTR : &R_USB_FS0->D0FIFOCTR;
+#else
+    volatile uint16_t * d0fifosel = &R_USB_FS0->D0FIFOSEL;
+    volatile void     * d0fifo    = &R_USB_FS0->D0FIFO;
+    volatile uint16_t * d0fifoctr = &R_USB_FS0->D0FIFOCTR;
+#endif
+
+    pipe_state_t * pipe = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[num];
+    const uint16_t rem  = pipe->remaining;
+
+    if (!rem)
+    {
+        pipe->buf = NULL;
+
+        return true;
+    }
+
+    *d0fifosel = num | R_USB_FIFOSEL_MBW_16BIT | (BYTE_ORDER == BIG_ENDIAN ? R_USB_FIFOSEL_BIGEND : 0);
+
+    const uint16_t mps = edpt_max_packet_size(p_ctrl, num);
+    pipe_wait_for_ready(p_ctrl, num);
+    const uint16_t len = min16(rem, mps);
+    void         * buf = pipe->buf;
+
+    if (len)
+    {
+        pipe_write_packet(p_ctrl, buf, d0fifo, len);
+        pipe->buf = (uint8_t *) buf + len;
+    }
+
+    if (len < mps)
+    {
+        *d0fifoctr = R_USB_D0FIFOCTR_BVAL_Msk;
+    }
+
+    *d0fifosel = 0;
+
+    /* if CURPIPE bits changes, check written value */
+    FSP_HARDWARE_REGISTER_WAIT((*d0fifosel & R_USB_D0FIFOSEL_CURPIPE_Msk), 0);
+
+    pipe->remaining = rem - len;
+
+    return false;
+}
+
+/* process OUT direction transfer for common pipe */
+static inline bool pipe_xfer_out (usbd_instance_ctrl_t * const p_ctrl, uint8_t num)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    bool                hs_module = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile uint16_t * d0fifosel = hs_module ? &R_USB_HS0->D0FIFOSEL : &R_USB_FS0->D0FIFOSEL;
+    volatile uint32_t * d0fifo    = hs_module ? &R_USB_HS0->D0FIFO : &R_USB_FS0->D0FIFO;
+    volatile uint16_t * d0fifoctr = hs_module ? &R_USB_HS0->D0FIFOCTR : &R_USB_FS0->D0FIFOCTR;
+#else
+    volatile uint16_t * d0fifosel = &R_USB_FS0->D0FIFOSEL;
+    volatile uint32_t * d0fifo    = &R_USB_FS0->D0FIFO;
+    volatile uint16_t * d0fifoctr = &R_USB_FS0->D0FIFOCTR;
+#endif
+
+    pipe_state_t * pipe = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[num];
+    const uint16_t rem  = pipe->remaining;
+
+    *d0fifosel = num | R_USB_FIFOSEL_MBW_8BIT;
+
+    const uint16_t mps = edpt_max_packet_size(p_ctrl, num);
+    pipe_wait_for_ready(p_ctrl, num);
+
+#ifdef USB_HIGH_SPEED_MODULE
+    const uint16_t vld = hs_module ? R_USB_HS0->D0FIFOCTR_b.DTLN : R_USB_FS0->D0FIFOCTR_b.DTLN;
+#else
+    const uint16_t vld = R_USB_FS0->D0FIFOCTR_b.DTLN;
+#endif
+    const uint16_t len = min16(min16(rem, mps), vld);
+    void         * buf = pipe->buf;
+
+    if (len > 0)
+    {
+        pipe_read_packet(p_ctrl, buf, d0fifo, len);
+        pipe->buf = (uint8_t *) buf + len;
+    }
+
+    if (len < mps)
+    {
+        *d0fifoctr = R_USB_D0FIFOCTR_BCLR_Msk;
+    }
+
+    *d0fifosel = 0;
+
+    /* if CURPIPE bits changes, check written value */
+    FSP_HARDWARE_REGISTER_WAIT((*d0fifosel & R_USB_D0FIFOSEL_CURPIPE_Msk), 0);
+
+    pipe->remaining = rem - len;
+    if ((len < mps) || (rem == len))
+    {
+        pipe->buf = NULL;
+
+        return NULL != buf;
+    }
+
+    return false;
+}
+
+/* setup packet received event handler */
+static inline void process_setup_packet (usbd_instance_ctrl_t * const p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    bool                hs_module = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile uint16_t * intsts0   = hs_module ? &R_USB_HS0->INTSTS0 : &R_USB_FS0->INTSTS0;
+    volatile uint16_t * cfifoctr  = hs_module ? &R_USB_HS0->CFIFOCTR : &R_USB_FS0->CFIFOCTR;
+#else
+    volatile uint16_t * intsts0  = &R_USB_FS0->INTSTS0;
+    volatile uint16_t * cfifoctr = &R_USB_FS0->CFIFOCTR;
+#endif
+
+    if (0 == (*intsts0 & R_USB_INTSTS0_VALID_Msk))
+    {
+        return;
+    }
+
+    *cfifoctr = R_USB_CFIFOCTR_BCLR_Msk;
+	*intsts0 = ~((uint16_t) R_USB_INTSTS0_VALID_Msk);
+
+#ifdef USB_HIGH_SPEED_MODULE
+    usbd_event_t event =
+    {
+        .event_id       = R_USBD_EVENT_SETUP_RECEIVED,
+        .setup_received =
+        {
+            hs_module ? R_USB_HS0->USBREQ : R_USB_FS0->USBREQ,
+            hs_module ? R_USB_HS0->USBVAL : R_USB_FS0->USBVAL,
+            hs_module ? R_USB_HS0->USBINDX : R_USB_FS0->USBINDX,
+            hs_module ? R_USB_HS0->USBLENG : R_USB_FS0->USBLENG
+        }
+    };
+#else
+    usbd_event_t event =
+    {
+        .event_id       = R_USBD_EVENT_SETUP_RECEIVED,
+        .setup_received =
+        {
+            R_USB_FS0->USBREQ,
+            R_USB_FS0->USBVAL,
+            R_USB_FS0->USBINDX,
+            R_USB_FS0->USBLENG
+        }
+    };
+#endif
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+#if USBD_CFG_CONTROL_EP_AUTO_STATUS_ENABLE == 0
+
+/* status packet transfer complete event handler */
+static inline void process_status_completion (usbd_instance_ctrl_t * const p_ctrl)
+{
+ #ifdef USB_HIGH_SPEED_MODULE
+    volatile uint16_t * cfifosel =
+        USB_IS_USBHS(p_ctrl->p_cfg->module_number) ? &R_USB_HS0->CFIFOSEL : &R_USB_FS0->CFIFOSEL;
+ #else
+    volatile uint16_t * cfifosel = &R_USB_FS0->CFIFOSEL;
+ #endif
+    uint8_t ep_addr;
+
+    /* Check the data stage direction */
+    if (*cfifosel & R_USB_CFIFOSEL_ISEL_WRITE)
+    {
+        /* IN transfer. */
+        ep_addr = USB_EP_CONTROL_IN;
+    }
+    else
+    {
+        /* OUT transfer. */
+        ep_addr = USB_EP_CONTROL_OUT;
+    }
+
+    usbd_event_t event =
+    {
+        .event_id      = R_USBD_EVENT_XFER_COMPLETE,
+        .xfer_complete =
+        {
+            .result  = USBD_XFER_RESULT_SUCCESS,
+            .ep_addr = ep_addr,
+            .len     = 0,
+        },
+    };
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+#endif
+
+/* pipe0 transfer */
+static inline fsp_err_t process_pipe0_xfer (usbd_instance_ctrl_t * const p_ctrl,
+                                            uint8_t                      ep_addr,
+                                            void                       * buffer,
+                                            uint16_t                     total_bytes)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    bool                hs_module = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile uint16_t * cfifosel  = hs_module ? &R_USB_HS0->CFIFOSEL : &R_USB_FS0->CFIFOSEL;
+    volatile uint16_t * dcpctr    = hs_module ? &R_USB_HS0->DCPCTR : &R_USB_FS0->DCPCTR;
+    volatile uint16_t * cfifoctr  = hs_module ? &R_USB_HS0->CFIFOCTR : &R_USB_FS0->CFIFOCTR;
+#else
+    volatile uint16_t * cfifosel = &R_USB_FS0->CFIFOSEL;
+    volatile uint16_t * dcpctr   = &R_USB_FS0->DCPCTR;
+    volatile uint16_t * cfifoctr = &R_USB_FS0->CFIFOCTR;
+#endif
+
+    const uint8_t dir = USB_GET_EP_DIR(ep_addr);
+    const uint8_t num = g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][0];
+
+    /* configure fifo direction and access unit settings */
+    if (USB_EP_CONTROL_IN == ep_addr)
+    {
+        /* IN, 2 bytes */
+        *cfifosel = R_USB_CFIFOSEL_ISEL_WRITE | R_USB_FIFOSEL_MBW_16BIT |
+                    (BYTE_ORDER == BIG_ENDIAN ? R_USB_FIFOSEL_BIGEND : 0);
+        FSP_HARDWARE_REGISTER_WAIT((*cfifosel & R_USB_CFIFOSEL_ISEL_Msk), R_USB_CFIFOSEL_ISEL_WRITE);
+    }
+    else
+    {
+        /* OUT, a byte */
+        *cfifosel = R_USB_FIFOSEL_MBW_8BIT;
+        FSP_HARDWARE_REGISTER_WAIT((*cfifosel & R_USB_CFIFOSEL_ISEL_Msk), 0);
+    }
+
+    pipe_state_t * pipe = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[num];
+    pipe->length    = total_bytes;
+    pipe->remaining = total_bytes;
+
+    if (total_bytes > 0)
+    {
+        pipe->buf = buffer;
+        if (USB_EP_CONTROL_IN == ep_addr)
+        {
+            pipe0_xfer_in(p_ctrl);
+        }
+
+        *dcpctr = R_USB_PIPE_CTR_PID_BUF;
+    }
+    else
+    {
+        /* ZLP */
+        pipe->buf = NULL;
+
+        switch (p_ctrl->dcp_stage)
+        {
+            case USB_CONTROL_STAGE_WRITE_NODATA_STATUS:
+#if USBD_CFG_CONTROL_EP_AUTO_STATUS_ENABLE == 0
+            case USB_CONTROL_STAGE_READ_STATUS:
+            case USB_CONTROL_STAGE_WRITE_STATUS:
+#endif
+            {
+                /* perform status stage */
+                process_control_status(p_ctrl);
+                break;
+            }
+
+            case USB_CONTROL_STAGE_READ_DATA:
+            case USB_CONTROL_STAGE_WRITE_DATA:
+            {
+                /* notice that this is the end of data stage */
+                *cfifoctr = R_USB_CFIFOCTR_BVAL_Msk;
+                break;
+            }
+
+            default:
+            {
+                return FSP_ERR_INVALID_CALL;
+            }
+        }
+    }
+
+    return FSP_SUCCESS;
+}
+
+/* common pipe transfer */
+static inline fsp_err_t process_pipe_xfer (usbd_instance_ctrl_t * const p_ctrl,
+                                           uint8_t                      ep_addr,
+                                           void                       * buffer,
+                                           uint16_t                     total_bytes)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    bool                hs_module = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile uint16_t * d0fifosel = hs_module ? &R_USB_HS0->D0FIFOSEL : &R_USB_FS0->D0FIFOSEL;
+    volatile uint16_t * d0fifoctr = hs_module ? &R_USB_HS0->D0FIFOCTR : &R_USB_FS0->D0FIFOCTR;
+#else
+    volatile uint16_t * d0fifosel = &R_USB_FS0->D0FIFOSEL;
+    volatile uint16_t * d0fifoctr = &R_USB_FS0->D0FIFOCTR;
+#endif
+    const uint8_t epn = USB_GET_EP_IDX(ep_addr);
+    const uint8_t dir = USB_GET_EP_DIR(ep_addr);
+    const uint8_t num = g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][epn];
+
+    if (0 == num)
+    {
+        return FSP_ERR_USB_NOT_OPEN;
+    }
+
+    pipe_state_t * pipe = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[num];
+    pipe->buf       = buffer;
+    pipe->length    = total_bytes;
+    pipe->remaining = total_bytes;
+
+    if (USB_EP_IN_DIR == dir)
+    {
+        /* IN */
+        if (total_bytes > 0)
+        {
+            pipe_xfer_in(p_ctrl, num);
+        }
+        else
+        {
+            /* ZLP */
+            *d0fifosel = num;
+            pipe_wait_for_ready(p_ctrl, num);
+            *d0fifoctr = R_USB_D0FIFOCTR_BVAL_Msk;
+            *d0fifosel = 0;
+
+            /* if CURPIPE bits changes, check written value */
+            FSP_HARDWARE_REGISTER_WAIT((*d0fifosel & R_USB_D0FIFOSEL_CURPIPE_Msk), 0);
+        }
+    }
+    else
+    {
+        /* OUT */
+        volatile R_USB_PIPE_TR_t * pt = get_pipetre(p_ctrl, num);
+
+        if (NULL != pt)
+        {
+            const uint16_t      mps     = edpt_max_packet_size(p_ctrl, num);
+            volatile uint16_t * pipectr = get_pipectr(p_ctrl, num);
+
+            if (*pipectr & R_USB_PIPE_CTR_PID_Msk)
+            {
+                *pipectr = R_USB_PIPE_CTR_PID_NAK;
+            }
+
+            pt->E_b.TRCLR = 1;
+            pt->N         = (total_bytes + mps - 1) / mps;
+            pt->E_b.TRENB = 1;
+            *pipectr      = R_USB_PIPE_CTR_PID_BUF;
+        }
+    }
+
+    return FSP_SUCCESS;
+}
+
+/* pipe0 BEMP event handler */
+static inline void process_pipe0_bemp (usbd_instance_ctrl_t * const p_ctrl)
+{
+    bool completed = pipe0_xfer_in(p_ctrl);
+
+    if (!completed)
+    {
+        return;
+    }
+
+    pipe_state_t * pipe  = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[0];
+    usbd_event_t   event =
+    {
+        .event_id      = R_USBD_EVENT_XFER_COMPLETE,
+        .xfer_complete =
+        {
+            .result  = USBD_XFER_RESULT_SUCCESS,
+            .ep_addr = USB_EP_CONTROL_IN,
+            .len     = pipe->length,
+        },
+    };
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+/* BRDY event hanlder  */
+static inline void process_pipe_brdy (usbd_instance_ctrl_t * const p_ctrl, uint32_t num)
+{
+    pipe_state_t * pipe = &g_pipe_cfg[p_ctrl->p_cfg->module_number].pipe[num];
+    const uint32_t dir  = USB_GET_EP_DIR(pipe->ep);
+    bool           completed;
+
+    if (USB_EP_IN_DIR == dir)
+    {
+        completed = pipe_xfer_in(p_ctrl, num);
+    }
+    else
+    {
+        /* OUT */
+        if (num)
+        {
+            completed = pipe_xfer_out(p_ctrl, num);
+        }
+        else
+        {
+            completed = pipe0_xfer_out(p_ctrl);
+        }
+    }
+
+    if (completed)
+    {
+        usbd_event_t event =
+        {
+            .event_id      = R_USBD_EVENT_XFER_COMPLETE,
+            .xfer_complete =
+            {
+                .result  = USBD_XFER_RESULT_SUCCESS,
+                .ep_addr = pipe->ep,
+                .len     = pipe->length - pipe->remaining,
+            },
+        };
+        r_usb_device_call_callback(p_ctrl, &event);
+    }
+}
+
+static inline usbd_speed_t usbfs_module_bus_reset (void)
+{
+    usbd_speed_t speed;
+
+    R_USB_FS0->BEMPENB  = 1;
+    R_USB_FS0->BRDYENB  = 1;
+    R_USB_FS0->CFIFOCTR = R_USB_CFIFOCTR_BCLR_Msk;
+
+    R_USB_FS0->D0FIFOSEL = 0;
+
+    /* if CURPIPE bits changes, check written value */
+    FSP_HARDWARE_REGISTER_WAIT(R_USB_FS0->D0FIFOSEL_b.CURPIPE, 0);
+
+    R_USB_FS0->D1FIFOSEL = 0;
+
+    /* if CURPIPE bits changes, check written value */
+    FSP_HARDWARE_REGISTER_WAIT(R_USB_FS0->D0FIFOSEL_b.CURPIPE, 0);
+
+    volatile uint16_t * pipectr = (volatile uint16_t *) &R_USB_FS0->PIPE_CTR[0];
+    volatile uint16_t * pipetre = (volatile uint16_t *) &R_USB_FS0->PIPE_TR[0].E;
+
+    for (int i = 1; i <= 5; ++i)
+    {
+        R_USB_FS0->PIPESEL = i;
+        R_USB_FS0->PIPECFG = 0;
+        *pipectr           = R_USB_PIPE_CTR_ACLRM_Msk;
+        *pipectr           = 0;
+        ++pipectr;
+        *pipetre = (1 << 8);
+        pipetre += 2;
+    }
+
+    for (int i = 6; i <= 9; ++i)
+    {
+        R_USB_FS0->PIPESEL = i;
+        R_USB_FS0->PIPECFG = 0;
+        *pipectr           = R_USB_PIPE_CTR_ACLRM_Msk;
+        *pipectr           = 0;
+        ++pipectr;
+    }
+
+    switch (R_USB_FS0->DVSTCTR0 & R_USB_DVSTCTR0_RHST_Msk)
+    {
+        case (1 << R_USB_DVSTCTR0_RHST_Pos):
+        {
+            speed = USBD_SPEED_LS;
+            break;
+        }
+
+        case (2 << R_USB_DVSTCTR0_RHST_Pos):
+        {
+            speed = USBD_SPEED_FS;
+            break;
+        }
+
+        case (3 << R_USB_DVSTCTR0_RHST_Pos):
+        {
+            speed = USBD_SPEED_HS;
+            break;
+        }
+
+        default:
+        {
+            speed = USBD_SPEED_INVALID;
+            break;
+        }
+    }
+
+    return speed;
+}
+
+#ifdef USB_HIGH_SPEED_MODULE
+static inline usbd_speed_t usbhs_module_bus_reset (void)
+{
+    usbd_speed_t speed;
+
+    R_USB_HS0->BEMPENB  = 1;
+    R_USB_HS0->BRDYENB  = 1;
+    R_USB_HS0->CFIFOCTR = R_USB_CFIFOCTR_BCLR_Msk;
+
+    R_USB_HS0->D0FIFOSEL = 0;
+
+    /* if CURPIPE bits changes, check written value */
+    FSP_HARDWARE_REGISTER_WAIT(R_USB_HS0->D0FIFOSEL_b.CURPIPE, 0);
+
+    R_USB_HS0->D1FIFOSEL = 0;
+
+    /* if CURPIPE bits changes, check written value */
+    FSP_HARDWARE_REGISTER_WAIT(R_USB_HS0->D0FIFOSEL_b.CURPIPE, 0);
+
+    volatile uint16_t * pipectr = (volatile uint16_t *) ((uintptr_t) (&R_USB_HS0->PIPE_CTR[0]));
+    volatile uint16_t * pipetre = (volatile uint16_t *) ((uintptr_t) (&R_USB_HS0->PIPE_TR[0].E));
+
+    for (int i = 1; i <= 5; ++i)
+    {
+        R_USB_HS0->PIPESEL = i;
+        R_USB_HS0->PIPECFG = 0;
+        *pipectr           = R_USB_PIPE_CTR_ACLRM_Msk;
+        *pipectr           = 0;
+        ++pipectr;
+        *pipetre = (1 << 8);
+        pipetre += 2;
+    }
+
+    for (int i = 6; i <= 9; ++i)
+    {
+        R_USB_HS0->PIPESEL = i;
+        R_USB_HS0->PIPECFG = 0;
+        *pipectr           = R_USB_PIPE_CTR_ACLRM_Msk;
+        *pipectr           = 0;
+        ++pipectr;
+    }
+
+    switch (R_USB_HS0->DVSTCTR0 & R_USB_DVSTCTR0_RHST_Msk)
+    {
+        case (1 << R_USB_DVSTCTR0_RHST_Pos):
+        {
+            speed = USBD_SPEED_LS;
+            break;
+        }
+
+        case (2 << R_USB_DVSTCTR0_RHST_Pos):
+        {
+            speed = USBD_SPEED_FS;
+            break;
+        }
+
+        case (3 << R_USB_DVSTCTR0_RHST_Pos):
+        {
+            speed = USBD_SPEED_HS;
+            break;
+        }
+
+        default:
+        {
+            speed = USBD_SPEED_INVALID;
+            break;
+        }
+    }
+
+    return speed;
+}
+
+#endif
+
+/* BUS_RESET event handler */
+static inline void process_bus_reset (usbd_instance_ctrl_t * const p_ctrl)
+{
+    usbd_speed_t speed = USBD_SPEED_INVALID;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        speed = usbhs_module_bus_reset();
+    }
+    else
+#endif
+    {
+        speed = usbfs_module_bus_reset();
+    }
+
+    usbd_event_t event =
+    {
+        .event_id        = R_USBD_EVENT_BUS_RESET,
+        .bus_reset.speed = speed,
+    };
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+/* SET_ADDRESS request packet received event handler */
+static inline void process_set_address (usbd_instance_ctrl_t * const p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    const bool     is_usbhs = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    const uint16_t addr     = (is_usbhs ? R_USB_HS0->USBADDR : R_USB_FS0->USBADDR) & 0x7fUL;
+#else
+    const uint16_t addr = R_USB_FS0->USBADDR & 0x7fUL;
+#endif
+
+    if (0 == addr)
+    {
+        return;
+    }
+
+    usbd_event_t event =
+    {
+        .event_id       = R_USBD_EVENT_SETUP_RECEIVED,
+        .setup_received =
+        {
+            .request_type   = USB_REQUEST_TYPE_SET_ADDRESS,
+            .request_value  = addr,
+            .request_index  = 0,
+            .request_length = 0,
+        },
+    };
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+/* configure for usb physical layer */
+static inline void physical_init (usbd_instance_ctrl_t * const p_ctrl, usbd_cfg_t const * const p_cfg)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_cfg->module_number))
+    {
+        /* High-speed selection */
+        R_USB_HS0->SYSCFG_b.HSE = (p_cfg->usb_speed == USBD_SPEED_HS) ? 1 : 0;
+
+        /* Power and reset UTMI PHY */
+        uint16_t physet = (R_USB_HS0->PHYSET | R_USB_PHYSET_PLLRESET_Msk) & ~R_USB_PHYSET_DIRPD_Msk;
+
+        physet           |= (USBHS_PHY_CLOCK_SOURCE_IS_XTAL == 0) ? R_USB_PHYSET_HSEB_Msk : 0;
+        R_USB_HS0->PHYSET = physet;
+
+        /* Setting the PHY clock */
+ #if USBHS_PHY_CLOCK_SOURCE_IS_XTAL
+        R_USB_HS0->PHYSET_b.CLKSEL = USBD_CFG_PHYSET_CLKSEL;
+ #endif
+        R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
+
+        /* PHY power down selection */
+        R_USB_HS0->SYSCFG_b.DRPD = 0;
+        R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS);
+
+        /* PHY return */
+        R_USB_HS0->PHYSET_b.PLLRESET = 0;
+
+        /* Set UTMI to operating mode and wait for PLL lock confirmation */
+        R_USB_HS0->LPSTS_b.SUSPENDM = 1;
+        FSP_HARDWARE_REGISTER_WAIT(R_USB_HS0->PLLSTA_b.PLLLOCK, 1);
+
+        /* Enable USB operation */
+        R_USB_HS0->SYSCFG_b.USBE = 1;
+
+        /* Set CPU bus wait time */
+        R_USB_HS0->BUSWAIT |= USBD_CFG_BUS_WAIT_TIME;
+
+        /* Adjust terminating resistance at 16-second intervals */
+        R_USB_HS0->PHYSET_b.REPSEL = 1;
+    }
+    else
+#endif
+    {
+        /* Enable clock supply to USBFS */
+        R_USB_FS0->SYSCFG_b.SCKE = 1;
+        FSP_HARDWARE_REGISTER_WAIT(R_USB_FS0->SYSCFG_b.SCKE, 1);
+
+        /* Disable line pull-down */
+        R_USB_FS0->SYSCFG_b.DRPD = 0;
+
+        /* Select controller as device controller */
+        R_USB_FS0->SYSCFG_b.DCFM = 0;
+
+        /* Enable module operation */
+        R_USB_FS0->SYSCFG_b.USBE = 1;
+
+        /* Adjust PHY cross point */
+        R_USB_FS0->PHYSLEW = 0x5;      /* TODO: tunning it */
+
+        /* USB_BASE Transceiver Output fixed */
+        R_USB_FS0->DPUSR0R_FS_b.FIXPHY0 = 0;
+    }
+}
+
+/* setting default pipe0 to ready for enumerations */
+static inline void control_pipe_setup (usbd_instance_ctrl_t * const p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->DCPMAXP_b.MXPS = 64;
+        R_USB_HS0->BEMPENB        = 1;
+        R_USB_HS0->BRDYENB        = 1;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->DCPMAXP_b.MXPS = 64;
+        R_USB_FS0->BEMPENB        = 1;
+        R_USB_FS0->BRDYENB        = 1;
+    }
+}
+
+static inline void usb_interrupt_configure (usbd_instance_ctrl_t * p_ctrl, usbd_cfg_t const * p_cfg)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_cfg->module_number))
+    {
+        R_USB_HS0->INTSTS0 = 0;
+        R_USB_HS0->INTENB0 = R_USB_INTSTS0_VBINT_Msk | R_USB_INTSTS0_BRDY_Msk | R_USB_INTSTS0_BEMP_Msk |
+                             R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_CTRT_Msk |
+                             R_USB_INTSTS0_RESM_Msk;
+
+        R_BSP_IrqCfgEnable(p_cfg->hs_irq, p_cfg->hsipl, p_ctrl);
+    }
+    else
+#endif
+    {
+        R_USB_FS0->INTSTS0 = 0;
+        R_USB_FS0->INTENB0 = R_USB_INTSTS0_VBINT_Msk | R_USB_INTSTS0_BRDY_Msk | R_USB_INTSTS0_BEMP_Msk |
+                             R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_CTRT_Msk |
+                             R_USB_INTSTS0_RESM_Msk;
+
+        R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_ctrl);
+        R_BSP_IrqCfgEnable(p_cfg->irq_r, p_cfg->ipl_r, p_ctrl);
+    }
+}
+
+static void r_usb_device_call_callback (usbd_instance_ctrl_t * p_ctrl, usbd_event_t * event)
+{
+    usbd_callback_arg_t   args;
+    usbd_callback_arg_t * p_args = p_ctrl->p_callback_memory;
+
+    if (NULL == p_ctrl->p_callback)
+    {
+        return;
+    }
+
+    if (NULL == p_args)
+    {
+        /* Store on stack */
+        p_args = &args;
+    }
+    else
+    {
+        /* Save current arguments on the stack in case this is a nested interrupt. */
+        args = *p_args;
+    }
+
+    p_args->module_number = p_ctrl->p_cfg->module_number;
+    p_args->p_context     = p_ctrl->p_context;
+    memcpy(&p_args->event, event, sizeof(usbd_event_t));
+
+    p_ctrl->p_callback(p_args);
+
+    if (NULL != p_ctrl->p_callback_memory)
+    {
+        /* Restore callback memory in case this is a nested interrupt. */
+        *p_ctrl->p_callback_memory = args;
+    }
+}
+
+static inline void usb_module_register_clear (uint8_t usb_ip)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(usb_ip))
+    {
+        R_USB_HS0->DVSTCTR0    = 0;
+        R_USB_HS0->DCPCTR      = R_USB_PIPE_CTR_SQSET_Msk;
+        R_USB_HS0->PIPE_CTR[0] = 0;
+        R_USB_HS0->PIPE_CTR[1] = 0;
+        R_USB_HS0->PIPE_CTR[2] = 0;
+        R_USB_HS0->PIPE_CTR[3] = 0;
+        R_USB_HS0->PIPE_CTR[4] = 0;
+        R_USB_HS0->PIPE_CTR[5] = 0;
+        R_USB_HS0->PIPE_CTR[6] = 0;
+        R_USB_HS0->PIPE_CTR[7] = 0;
+        R_USB_HS0->PIPE_CTR[8] = 0;
+        R_USB_HS0->BRDYENB     = 0;
+        R_USB_HS0->NRDYENB     = 0;
+        R_USB_HS0->BEMPENB     = 0;
+        R_USB_HS0->INTENB0     = 0;
+        R_USB_HS0->INTENB1     = 0;
+        R_USB_HS0->BRDYSTS     = 0;
+        R_USB_HS0->NRDYSTS     = 0;
+        R_USB_HS0->BEMPSTS     = 0;
+        R_USB_HS0->SYSCFG     &= (~R_USB_SYSCFG_DPRPU_Msk);
+        R_USB_HS0->SYSCFG     &= (~R_USB_SYSCFG_USBE_Msk);
+        R_USB_HS0->SYSCFG     &= (~R_USB_SYSCFG_DRPD_Msk);
+        R_USB_HS0->SYSCFG     &= (~R_USB_SYSCFG_DCFM_Msk);
+        R_USB_HS0->LPSTS       = 0;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->DVSTCTR0    = 0;
+        R_USB_FS0->DCPCTR      = R_USB_PIPE_CTR_SQSET_Msk;
+        R_USB_FS0->PIPE_CTR[0] = 0;
+        R_USB_FS0->PIPE_CTR[1] = 0;
+        R_USB_FS0->PIPE_CTR[2] = 0;
+        R_USB_FS0->PIPE_CTR[3] = 0;
+        R_USB_FS0->PIPE_CTR[4] = 0;
+        R_USB_FS0->PIPE_CTR[5] = 0;
+        R_USB_FS0->PIPE_CTR[6] = 0;
+        R_USB_FS0->PIPE_CTR[7] = 0;
+        R_USB_FS0->PIPE_CTR[8] = 0;
+        R_USB_FS0->BRDYENB     = 0;
+        R_USB_FS0->NRDYENB     = 0;
+        R_USB_FS0->BEMPENB     = 0;
+        R_USB_FS0->INTENB0     = 0;
+        R_USB_FS0->INTENB1     = 0;
+        R_USB_FS0->BRDYSTS     = 0;
+        R_USB_FS0->NRDYSTS     = 0;
+        R_USB_FS0->BEMPSTS     = 0;
+        R_USB_FS0->SYSCFG     &= (~R_USB_SYSCFG_DPRPU_Msk);
+        R_USB_FS0->SYSCFG     &= (~R_USB_SYSCFG_DRPD_Msk);
+        R_USB_FS0->SYSCFG     &= (~R_USB_SYSCFG_DCFM_Msk);
+        R_USB_FS0->SYSCFG     &= (~R_USB_SYSCFG_USBE_Msk);
+    }
+
+    R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
+}
+
+static inline void usb_module_start (usbd_instance_ctrl_t * p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_BSP_MODULE_START(FSP_IP_USBHS, 0);
+    }
+    else
+#endif
+    {
+        R_BSP_MODULE_START(FSP_IP_USBFS, 0);
+    }
+}
+
+static inline void usb_module_stop (usbd_instance_ctrl_t * p_ctrl)
+{
+    usb_module_register_clear(p_ctrl->p_cfg->module_number);
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_BSP_MODULE_STOP(FSP_IP_USBHS, 0);
+    }
+    else
+#endif
+    {
+        R_BSP_MODULE_STOP(FSP_IP_USBFS, 0);
+    }
+}
+
+static inline void usb_disable_interrupt (usbd_instance_ctrl_t * p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->INTENB0 &= ~(R_USB_INTSTS0_VBINT_Msk | R_USB_INTSTS0_BRDY_Msk | R_USB_INTSTS0_BEMP_Msk |
+                                R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_CTRT_Msk |
+                                R_USB_INTSTS0_RESM_Msk);
+
+        R_BSP_IrqDisable(p_ctrl->p_cfg->hs_irq);
+    }
+    else
+#endif
+    {
+        R_USB_FS0->INTENB0 &= ~(R_USB_INTSTS0_VBINT_Msk | R_USB_INTSTS0_BRDY_Msk | R_USB_INTSTS0_BEMP_Msk |
+                                R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_CTRT_Msk |
+                                R_USB_INTSTS0_RESM_Msk);
+
+        R_BSP_IrqDisable(p_ctrl->p_cfg->irq);
+        R_BSP_IrqDisable(p_ctrl->p_cfg->irq_r);
+    }
+}
+
+static inline void usb_enable_interrupt (usbd_instance_ctrl_t * p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_BSP_IrqEnable(p_ctrl->p_cfg->hs_irq);
+
+        R_USB_HS0->INTENB0 = R_USB_INTSTS0_VBINT_Msk | R_USB_INTSTS0_BRDY_Msk | R_USB_INTSTS0_BEMP_Msk |
+                             R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_CTRT_Msk |
+                             R_USB_INTSTS0_RESM_Msk;
+    }
+    else
+#endif
+    {
+        R_BSP_IrqEnable(p_ctrl->p_cfg->irq);
+        R_BSP_IrqEnable(p_ctrl->p_cfg->irq_r);
+
+        R_USB_FS0->INTENB0 = R_USB_INTSTS0_VBINT_Msk | R_USB_INTSTS0_BRDY_Msk | R_USB_INTSTS0_BEMP_Msk |
+                             R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_CTRT_Msk |
+                             R_USB_INTSTS0_RESM_Msk;
+    }
+}
+
+static inline void process_pipe_forced_termination (usbd_instance_ctrl_t * const p_ctrl, uint8_t ep)
+{
+    const uint8_t epn = USB_GET_EP_IDX(ep);
+    const uint8_t dir = USB_GET_EP_DIR(ep);
+    const uint8_t num = g_pipe_cfg[p_ctrl->p_cfg->module_number].ep[USB_PIPECFG_DIR_IDX(dir)][epn];
+
+    if (0 == num)
+    {
+        /* This endpoint is not yet opened */
+        return;
+    }
+
+    volatile uint16_t * pt      = get_pipetre(p_ctrl, num);
+    volatile uint16_t * pipectr = get_pipectr(p_ctrl, num);
+
+    /* Set NAK */
+    if (0 != (*pipectr & R_USB_PIPE_CTR_PID_Msk))
+    {
+        *pipectr = R_USB_PIPE_CTR_PID_NAK;
+    }
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        /* Disable pipe interrupt */
+        R_USB_HS0->BRDYENB &= (uint16_t) ~(1 << num);
+        R_USB_HS0->NRDYENB &= (uint16_t) ~(1 << num);
+        R_USB_HS0->BEMPENB &= (uint16_t) ~(1 << num);
+
+        /* Clear transaction counter */
+        *pt &= ~R_USB_PIPE_TR_E_TRENB_Msk;
+        *pt |= R_USB_PIPE_TR_E_TRCLR_Msk;
+
+        /* Clear FIFO port */
+        if (num == R_USB_HS0->D0FIFOSEL_b.CURPIPE)
+        {
+            R_USB_HS0->D0FIFOSEL_b.CURPIPE = 0;
+        }
+    }
+    else
+#endif
+    {
+        R_USB_FS0->BRDYENB &= (uint16_t) ~(1 << num);
+        R_USB_FS0->NRDYENB &= (uint16_t) ~(1 << num);
+        R_USB_FS0->BEMPENB &= (uint16_t) ~(1 << num);
+
+        /* Clear transaction counter */
+        *pt &= ~R_USB_PIPE_TR_E_TRENB_Msk;
+        *pt |= R_USB_PIPE_TR_E_TRCLR_Msk;
+
+        /* Clear FIFO port */
+        if (num == R_USB_FS0->D0FIFOSEL_b.CURPIPE)
+        {
+            R_USB_FS0->D0FIFOSEL_b.CURPIPE = 0;
+        }
+    }
+
+    /* Buffer clear */
+    *pipectr |= R_USB_PIPE_CTR_ACLRM_Msk;
+    *pipectr &= ~R_USB_PIPE_CTR_ACLRM_Msk;
+
+    /* SPLIT Buffer clear */
+    *pipectr &= R_USB_PIPE_CTR_CSCLR_Msk;
+}
+
+static inline uint16_t get_active_bit_intsts0 (usbd_instance_ctrl_t * p_ctrl)
+{
+    uint16_t intsts0;
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        intsts0 = R_USB_HS0->INTSTS0;
+
+        /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
+        R_USB_HS0->INTSTS0 = ~((R_USB_INTSTS0_CTRT_Msk | R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_SOFR_Msk |
+                                R_USB_INTSTS0_RESM_Msk | R_USB_INTSTS0_VBINT_Msk) & intsts0) | R_USB_INTSTS0_VALID_Msk;
+    }
+    else
+#endif
+    {
+        intsts0 = R_USB_FS0->INTSTS0;
+
+        /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
+        R_USB_FS0->INTSTS0 = ~((R_USB_INTSTS0_CTRT_Msk | R_USB_INTSTS0_DVST_Msk | R_USB_INTSTS0_SOFR_Msk |
+                                R_USB_INTSTS0_RESM_Msk | R_USB_INTSTS0_VBINT_Msk) & intsts0) | R_USB_INTSTS0_VALID_Msk;
+    }
+
+    return intsts0;
+}
+
+static inline void process_vbus_changed (usbd_instance_ctrl_t * p_ctrl, uint16_t intsts0)
+{
+    usbd_event_t event;
+
+    if (intsts0 & R_USB_INTSTS0_VBSTS_Msk)
+    {
+        event.event_id = R_USBD_EVENT_VBUS_RDY;
+    }
+    else
+    {
+        event.event_id = R_USBD_EVENT_VBUS_REMOVED;
+    }
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+static inline void process_resumed_event (usbd_instance_ctrl_t * p_ctrl)
+{
+    usbd_event_t event =
+    {
+        .event_id = R_USBD_EVENT_RESUME,
+    };
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->INTENB0_b.SOFE = 0;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->INTENB0_b.SOFE = 0;
+    }
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+static inline void process_sof_event (usbd_instance_ctrl_t * p_ctrl)
+{
+    usbd_event_t event =
+    {
+        .event_id = R_USBD_EVENT_SOF,
+    };
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        if (R_USB_HS0->INTENB0_b.SOFE)
+        {
+            R_USB_HS0->INTENB0_b.SOFE = 0;
+        }
+        else
+        {
+            return;
+        }
+    }
+    else
+#endif
+    {
+        if (R_USB_FS0->INTENB0_b.SOFE)
+        {
+            R_USB_FS0->INTENB0_b.SOFE = 0;
+        }
+        else
+        {
+            return;
+        }
+    }
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+static inline void process_suppend_event (usbd_instance_ctrl_t * p_ctrl)
+{
+    usbd_event_t event =
+    {
+        .event_id = R_USBD_EVENT_SUSPEND,
+    };
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->INTENB0_b.SOFE = 1;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->INTENB0_b.SOFE = 1;
+    }
+
+    r_usb_device_call_callback(p_ctrl, &event);
+}
+
+static inline void process_nrdy_event (usbd_instance_ctrl_t * p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    if (USB_IS_USBHS(p_ctrl->p_cfg->module_number))
+    {
+        R_USB_HS0->NRDYSTS = 0;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->NRDYSTS = 0;
+    }
+}
+
+static inline void process_bemp_event (usbd_instance_ctrl_t * p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    const bool     is_usbhs = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    const uint16_t bempsts  = is_usbhs ? R_USB_HS0->BEMPSTS : R_USB_FS0->BEMPSTS;
+#else
+    const uint16_t bempsts = R_USB_FS0->BEMPSTS;
+#endif
+
+#ifdef USB_HIGH_SPEED_MODULE
+    if (is_usbhs)
+    {
+        R_USB_HS0->BEMPSTS = 0;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->BEMPSTS = 0;
+    }
+
+    if ((bempsts & 0x1U) != 0)
+    {
+        process_pipe0_bemp(p_ctrl);
+    }
+}
+
+static inline void process_brdy_event (usbd_instance_ctrl_t * p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    const bool     is_usbhs = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    const uint16_t brdyenb  = is_usbhs ? R_USB_HS0->BRDYENB : R_USB_FS0->BRDYENB;
+    uint16_t       brdysts  = (is_usbhs ? R_USB_HS0->BRDYSTS : R_USB_FS0->BRDYSTS) & brdyenb;
+#else
+    const uint16_t brdyenb = R_USB_FS0->BRDYENB;
+    uint16_t       brdysts = R_USB_FS0->BRDYSTS & brdyenb;
+#endif
+
+    /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
+#ifdef USB_HIGH_SPEED_MODULE
+    if (is_usbhs)
+    {
+        R_USB_HS0->BRDYSTS = ~brdysts;
+    }
+    else
+#endif
+    {
+        R_USB_FS0->BRDYSTS = ~brdysts;
+    }
+
+    while (brdysts)
+    {
+        const uint32_t num = get_first_bit1_offset(brdysts);
+        process_pipe_brdy(p_ctrl, num);
+        brdysts &= ~(1 << num);
+    }
+}
+
+static void process_control_status (usbd_instance_ctrl_t * p_ctrl)
+{
+#ifdef USB_HIGH_SPEED_MODULE
+    const bool          is_usbhs = USB_IS_USBHS(p_ctrl->p_cfg->module_number);
+    volatile uint16_t * dcpctr   = is_usbhs ? &R_USB_HS0->DCPCTR : &R_USB_FS0->DCPCTR;
+#else
+    volatile uint16_t * dcpctr = &R_USB_FS0->DCPCTR;
+#endif
+
+    if (p_ctrl->dcp_stage == USB_CONTROL_STAGE_WRITE_NODATA_STATUS)
+    {
+        *dcpctr = R_USB_PIPE_CTR_PID_BUF;
+    }
+
+    *dcpctr |= R_USB_DCPCTR_CCPL_Msk;
+}
+
+/***********************************************************************************************************************
+ * USB device isr
+ **********************************************************************************************************************/
+void usb_device_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    usbd_instance_ctrl_t * p_ctrl = R_FSP_IsrContextGet(irq);
+
+    uint16_t intsts0 = get_active_bit_intsts0(p_ctrl);
+
+    /*
+     * Clear pending IRQ to make sure it doesn't fire again after exiting
+     *
+     * The flag clearing should be done immediately after reading the interrupt status registers.
+     * This will prevent missing interrupts that occur during ISR execution which should be handled
+     * right after exiting the current ISR.
+     */
+    R_BSP_IrqStatusClear(irq);
+
+    /* VBUS changes */
+    if (intsts0 & R_USB_INTSTS0_VBINT_Msk)
+    {
+        process_vbus_changed(p_ctrl, intsts0);
+    }
+
+    /* Resumed */
+    if (intsts0 & R_USB_INTSTS0_RESM_Msk)
+    {
+        process_resumed_event(p_ctrl);
+    }
+
+    /* SOF received */
+    if (intsts0 & R_USB_INTSTS0_SOFR_Msk)
+    {
+        process_sof_event(p_ctrl);
+    }
+
+    /* Device state changes */
+    if (intsts0 & R_USB_INTSTS0_DVST_Msk)
+    {
+        switch (intsts0 & R_USB_INTSTS0_DVSQ_Msk)
+        {
+            case R_USB_INTSTS0_DVSQ_STATE_DEF:
+            {
+                process_bus_reset(p_ctrl);
+                break;
+            }
+
+            case R_USB_INTSTS0_DVSQ_STATE_ADDR:
+            {
+                process_set_address(p_ctrl);
+                break;
+            }
+
+            case R_USB_INTSTS0_DVSQ_STATE_SUSP0:
+            case R_USB_INTSTS0_DVSQ_STATE_SUSP1:
+            case R_USB_INTSTS0_DVSQ_STATE_SUSP2:
+            case R_USB_INTSTS0_DVSQ_STATE_SUSP3:
+            {
+                process_suppend_event(p_ctrl);
+                break;
+            }
+
+            default:
+            {
+                break;
+            }
+        }
+    }
+
+    if (intsts0 & R_USB_INTSTS0_NRDY_Msk)
+    {
+        process_nrdy_event(p_ctrl);
+    }
+
+    /* Control transfer stage changes */
+    if (intsts0 & R_USB_INTSTS0_CTRT_Msk)
+    {
+        p_ctrl->dcp_stage = (intsts0 & R_USB_INTSTS0_CTSQ_Msk) >> R_USB_INTSTS0_CTSQ_Pos;
+
+        switch (p_ctrl->dcp_stage)
+        {
+            case USB_CONTROL_STAGE_READ_DATA:
+            case USB_CONTROL_STAGE_WRITE_DATA:
+            case USB_CONTROL_STAGE_WRITE_NODATA_STATUS:
+            {
+                process_setup_packet(p_ctrl);
+                break;
+            }
+
+#if USBD_CFG_CONTROL_EP_AUTO_STATUS_ENABLE
+            case USB_CONTROL_STAGE_READ_STATUS:
+            case USB_CONTROL_STAGE_WRITE_STATUS:
+            {
+                process_control_status(p_ctrl);
+                break;
+            }
+#else
+            case USB_CONTROL_STAGE_IDLE:
+            {
+                /* A ZLP has been sent/received. */
+                process_status_completion(p_ctrl);
+                break;
+            }
+#endif
+
+            default:
+            {
+                break;
+            }
+        }
+    }
+
+    /* Buffer empty */
+    if (intsts0 & R_USB_INTSTS0_BEMP_Msk)
+    {
+        process_bemp_event(p_ctrl);
+    }
+
+    /* Buffer ready */
+    if (intsts0 & R_USB_INTSTS0_BRDY_Msk)
+    {
+        process_brdy_event(p_ctrl);
+    }
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
diff --git a/port/renesas/device/r_usb_device.h b/port/renesas/device/r_usb_device.h
new file mode 100644
index 00000000..49298bdb
--- /dev/null
+++ b/port/renesas/device/r_usb_device.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef R_USB_DEVICE_H
+#define R_USB_DEVICE_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_usb_device_api.h"
+#include "r_usb_device_cfg.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+typedef enum e_usbd_control_stage
+{
+    USB_CONTROL_STAGE_IDLE                = 0x0,
+    USB_CONTROL_STAGE_SETUP               = 0x0,
+    USB_CONTROL_STAGE_READ_DATA           = 0x1,
+    USB_CONTROL_STAGE_READ_STATUS         = 0x2,
+    USB_CONTROL_STAGE_WRITE_DATA          = 0x3,
+    USB_CONTROL_STAGE_WRITE_STATUS        = 0x4,
+    USB_CONTROL_STAGE_WRITE_NODATA_STATUS = 0x5,
+    USB_CONTROL_STAGE_ERROR               = 0x6,
+} usbd_control_stage_t;
+
+typedef struct st_usbd_instance_ctrl
+{
+    uint32_t           open;
+    void             * p_reg;
+    usbd_cfg_t const * p_cfg;
+    void (* p_callback)(usbd_callback_arg_t * p_args);
+    usbd_callback_arg_t         * p_callback_memory;
+    void const                  * p_context;
+    volatile usbd_control_stage_t dcp_stage;
+} usbd_instance_ctrl_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+fsp_err_t R_USBD_Open(usbd_ctrl_t * const p_api_ctrl, usbd_cfg_t const * const p_cfg);
+fsp_err_t R_USBD_RemoteWakeup(usbd_ctrl_t * const p_api_ctrl);
+fsp_err_t R_USBD_Connect(usbd_ctrl_t * const p_api_ctrl);
+fsp_err_t R_USBD_Disconnect(usbd_ctrl_t * const p_api_ctrl);
+fsp_err_t R_USBD_EdptOpen(usbd_ctrl_t * const p_api_ctrl, usbd_desc_endpoint_t const * p_ep_desc);
+fsp_err_t R_USBD_EdptClose(usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr);
+fsp_err_t R_USBD_XferStart(usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+fsp_err_t R_USBD_XferAbort(usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr);
+fsp_err_t R_USBD_EdptStall(usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr);
+fsp_err_t R_USBD_EdptClearStall(usbd_ctrl_t * const p_api_ctrl, uint8_t ep_addr);
+fsp_err_t R_USBD_Close(usbd_ctrl_t * const p_api_ctrl);
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif /* R_USB_DEVICE_H */
\ No newline at end of file
diff --git a/port/renesas/device/r_usb_device_api.h b/port/renesas/device/r_usb_device_api.h
new file mode 100644
index 00000000..cfa74a26
--- /dev/null
+++ b/port/renesas/device/r_usb_device_api.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef R_USB_DEVICE_API_H
+#define R_USB_DEVICE_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** USB setup packet */
+typedef struct __PACKED st_usbd_setup
+{
+    uint16_t request_type;
+    uint16_t request_value;
+    uint16_t request_index;
+    uint16_t request_length;
+} usbd_setup_t;
+
+/** USB Endpoint Descriptor */
+typedef struct __PACKED st_usbd_desc_endpoint
+{
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bEndpointAddress;
+    union
+    {
+        uint8_t bmAttributes;
+        struct
+        {
+            uint8_t xfer  : 2;
+            uint8_t sync  : 2;
+            uint8_t usage : 2;
+            uint8_t       : 2;
+        } Attributes;
+    };
+
+    uint16_t wMaxPacketSize;
+    uint8_t bInterval;
+} usbd_desc_endpoint_t;
+
+/** USB speed */
+typedef enum e_usbd_speed
+{
+    USBD_SPEED_LS = 0,
+    USBD_SPEED_FS,
+    USBD_SPEED_HS,
+    USBD_SPEED_INVALID,
+} usbd_speed_t;
+
+/** USB event code */
+typedef enum e_usbd_event_id
+{
+    R_USBD_EVENT_INVALID = 0,
+    R_USBD_EVENT_BUS_RESET,
+    R_USBD_EVENT_VBUS_RDY,
+    R_USBD_EVENT_VBUS_REMOVED,
+    R_USBD_EVENT_SOF,
+    R_USBD_EVENT_SUSPEND,
+    R_USBD_EVENT_RESUME,
+    R_USBD_EVENT_SETUP_RECEIVED,
+    R_USBD_EVENT_XFER_COMPLETE,
+} usbd_event_id_t;
+
+/** USB transfer result code */
+typedef enum e_usbd_xfer_result
+{
+    USBD_XFER_RESULT_SUCCESS = 0,
+    USBD_XFER_RESULT_FAILED,
+    USBD_XFER_RESULT_STALLED,
+    USBD_XFER_RESULT_TIMEOUT,
+    USBD_XFER_RESULT_INVALID
+} usbd_xfer_result_t;
+
+/** USB bus reset event input argument */
+typedef struct st_usbd_bus_reset_evt
+{
+    usbd_speed_t speed;
+} usbd_bus_reset_evt_t;
+
+/** USB SOF detection event input argument */
+typedef struct st_usbd_sof_evt
+{
+    uint32_t frame_count;
+} usbd_sof_evt_t;
+
+/** USB transfer complete event input argument */
+typedef struct st_usbd_xfer_complete
+{
+    usbd_xfer_result_t result;
+    uint8_t            ep_addr;
+    uint32_t           len;
+} usbd_xfer_complete_t;
+
+typedef struct st_usb_event
+{
+    usbd_event_id_t event_id;
+    union
+    {
+        usbd_bus_reset_evt_t bus_reset;
+        usbd_sof_evt_t       sof;
+        usbd_setup_t         setup_received;
+        usbd_xfer_complete_t xfer_complete;
+    };
+} usbd_event_t;
+
+typedef struct st_usbd_callback_arg
+{
+    uint32_t     module_number;
+    usbd_event_t event;
+    void const * p_context;
+} usbd_callback_arg_t;
+
+/** USB configuration */
+typedef struct st_usbd_cfg
+{
+    uint32_t     module_number;
+    usbd_speed_t usb_speed;
+    IRQn_Type    irq;
+    IRQn_Type    irq_r;
+    IRQn_Type    irq_d0;
+    IRQn_Type    irq_d1;
+    IRQn_Type    hs_irq;
+    IRQn_Type    hsirq_d0;
+    IRQn_Type    hsirq_d1;
+    uint8_t      ipl;
+    uint8_t      ipl_r;
+    uint8_t      ipl_d0;
+    uint8_t      ipl_d1;
+    uint8_t      hsipl;
+    uint8_t      hsipl_d0;
+    uint8_t      hsipl_d1;
+    void (* p_callback)(usbd_callback_arg_t * p_args);
+    void const * p_context;
+    void const * p_extend;
+} usbd_cfg_t;
+
+typedef void usbd_ctrl_t;
+
+#endif /* R_USB_DEVICE_API_H */
\ No newline at end of file
diff --git a/port/renesas/device/r_usb_device_cfg.h b/port/renesas/device/r_usb_device_cfg.h
new file mode 100644
index 00000000..f33b2381
--- /dev/null
+++ b/port/renesas/device/r_usb_device_cfg.h
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef R_USB_DEVICE_CFG_H_
+#define R_USB_DEVICE_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USBHS_PHY_CLOCK_SOURCE_IS_XTAL    1
+
+#define USBD_CFG_PARAM_CHECKING_ENABLE    (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define USBD_CFG_BUS_WAIT_TIME            (0x000FU) /* 17 access cycles */
+
+#if USBHS_PHY_CLOCK_SOURCE_IS_XTAL
+#if BSP_CFG_XTAL_HZ == 12000000
+#define USBD_CFG_PHYSET_CLKSEL            (0U)
+#elif BSP_CFG_XTAL_HZ == 48000000
+#define USBD_CFG_PHYSET_CLKSEL            (0x1U)
+#elif BSP_CFG_XTAL_HZ == 20000000
+#define USBD_CFG_PHYSET_CLKSEL            (0x2U)
+#elif BSP_CFG_XTAL_HZ == 24000000
+#define USBD_CFG_PHYSET_CLKSEL            (0x3U)
+#else
+#error "Available XTAL clocks are 12-20-24-48Mhz"
+#endif
+#else   /* Use 48Mhz UCK as clock source for PHY clock */
+#define USBD_CFG_PHYSET_CLKSEL            (-1)
+#endif
+
+/* Enable auto status for control write/read endpoint */
+#define USBD_CFG_CONTROL_EP_AUTO_STATUS_ENABLE (1U)
+
+#ifdef __cplusplus
+}
+#endif
+#endif                                 /* R_USB_DEVICE_CFG_H_ */
diff --git a/port/renesas/device/r_usb_device_define.h b/port/renesas/device/r_usb_device_define.h
new file mode 100644
index 00000000..de2c664a
--- /dev/null
+++ b/port/renesas/device/r_usb_device_define.h
@@ -0,0 +1,779 @@
+/*
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef R_USB_DEVICE_DEFINE_H
+#define R_USB_DEVICE_DEFINE_H
+
+#include "r_usb_device.h"
+
+#define USB_NOT_SUPPORT    (-1)
+#define USB_FS_MODULE      (0U)
+#define USB_HS_MODULE      (1U)
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#if BSP_FEATURE_USB_HAS_USBHS == 1U
+
+ #define USB_HIGH_SPEED_MODULE
+ #define USB_IP0_MODULE    USB_FS_MODULE
+ #define USB_IP1_MODULE    USB_HS_MODULE
+ #define USB_NUM_USBIP     2
+
+ #define USB_IS_USBHS(usbip)    ((usbip) == USB_HS_MODULE)
+
+#else
+
+ #define USB_IP0_MODULE    USB_FS_MODULE
+ #define USB_IP1_MODULE    USB_NOT_SUPPORT
+ #define USB_NUM_USBIP     1
+
+#endif
+
+/* USBFS & USBHS Register definition */
+
+/* PIPE_TR E */
+#define R_USB_PIPE_TR_E_TRENB_Pos                 (9UL)        /* TRENB (Bit 9) */
+#define R_USB_PIPE_TR_E_TRENB_Msk                 (0x200UL)    /* TRENB (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_TR_E_TRCLR_Pos                 (8UL)        /* TRCLR (Bit 8) */
+#define R_USB_PIPE_TR_E_TRCLR_Msk                 (0x100UL)    /* TRCLR (Bitfield-Mask: 0x01) */
+
+/* PIPE_TR N */
+#define R_USB_PIPE_TR_N_TRNCNT_Pos                (0UL)        /* TRNCNT (Bit 0) */
+#define R_USB_PIPE_TR_N_TRNCNT_Msk                (0xffffUL)   /* TRNCNT (Bitfield-Mask: 0xffff) */
+
+/* SYSCFG */
+#define R_USB_SYSCFG_SCKE_Pos                     (10UL)       /* SCKE (Bit 10) */
+#define R_USB_SYSCFG_SCKE_Msk                     (0x400UL)    /* SCKE (Bitfield-Mask: 0x01) */
+#define R_USB_SYSCFG_CNEN_Pos                     (8UL)        /* CNEN (Bit 8) */
+#define R_USB_SYSCFG_CNEN_Msk                     (0x100UL)    /* CNEN (Bitfield-Mask: 0x01) */
+#define R_USB_SYSCFG_HSE_Pos                      (7UL)        /* HSE (Bit 7) */
+#define R_USB_SYSCFG_HSE_Msk                      (0x80UL)     /* HSE (Bitfield-Mask: 0x01) */
+#define R_USB_SYSCFG_DCFM_Pos                     (6UL)        /* DCFM (Bit 6) */
+#define R_USB_SYSCFG_DCFM_Msk                     (0x40UL)     /* DCFM (Bitfield-Mask: 0x01) */
+#define R_USB_SYSCFG_DRPD_Pos                     (5UL)        /* DRPD (Bit 5) */
+#define R_USB_SYSCFG_DRPD_Msk                     (0x20UL)     /* DRPD (Bitfield-Mask: 0x01) */
+#define R_USB_SYSCFG_DPRPU_Pos                    (4UL)        /* DPRPU (Bit 4) */
+#define R_USB_SYSCFG_DPRPU_Msk                    (0x10UL)     /* DPRPU (Bitfield-Mask: 0x01) */
+#define R_USB_SYSCFG_DMRPU_Pos                    (3UL)        /* DMRPU (Bit 3) */
+#define R_USB_SYSCFG_DMRPU_Msk                    (0x8UL)      /* DMRPU (Bitfield-Mask: 0x01) */
+#define R_USB_SYSCFG_USBE_Pos                     (0UL)        /* USBE (Bit 0) */
+#define R_USB_SYSCFG_USBE_Msk                     (0x1UL)      /* USBE (Bitfield-Mask: 0x01) */
+
+/* BUSWAIT */
+#define R_USB_BUSWAIT_BWAIT_Pos                   (0UL)        /* BWAIT (Bit 0) */
+#define R_USB_BUSWAIT_BWAIT_Msk                   (0xfUL)      /* BWAIT (Bitfield-Mask: 0x0f) */
+
+/* SYSSTS0 */
+#define R_USB_SYSSTS0_OVCMON_Pos                  (14UL)       /* OVCMON (Bit 14) */
+#define R_USB_SYSSTS0_OVCMON_Msk                  (0xc000UL)   /* OVCMON (Bitfield-Mask: 0x03) */
+#define R_USB_SYSSTS0_HTACT_Pos                   (6UL)        /* HTACT (Bit 6) */
+#define R_USB_SYSSTS0_HTACT_Msk                   (0x40UL)     /* HTACT (Bitfield-Mask: 0x01) */
+#define R_USB_SYSSTS0_SOFEA_Pos                   (5UL)        /* SOFEA (Bit 5) */
+#define R_USB_SYSSTS0_SOFEA_Msk                   (0x20UL)     /* SOFEA (Bitfield-Mask: 0x01) */
+#define R_USB_SYSSTS0_IDMON_Pos                   (2UL)        /* IDMON (Bit 2) */
+#define R_USB_SYSSTS0_IDMON_Msk                   (0x4UL)      /* IDMON (Bitfield-Mask: 0x01) */
+#define R_USB_SYSSTS0_LNST_Pos                    (0UL)        /* LNST (Bit 0) */
+#define R_USB_SYSSTS0_LNST_Msk                    (0x3UL)      /* LNST (Bitfield-Mask: 0x03) */
+
+/* PLLSTA */
+#define R_USB_PLLSTA_PLLLOCK_Pos                  (0UL)        /* PLLLOCK (Bit 0) */
+#define R_USB_PLLSTA_PLLLOCK_Msk                  (0x1UL)      /* PLLLOCK (Bitfield-Mask: 0x01) */
+
+/* DVSTCTR0 */
+#define R_USB_DVSTCTR0_HNPBTOA_Pos                (11UL)       /* HNPBTOA (Bit 11) */
+#define R_USB_DVSTCTR0_HNPBTOA_Msk                (0x800UL)    /* HNPBTOA (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_EXICEN_Pos                 (10UL)       /* EXICEN (Bit 10) */
+#define R_USB_DVSTCTR0_EXICEN_Msk                 (0x400UL)    /* EXICEN (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_VBUSEN_Pos                 (9UL)        /* VBUSEN (Bit 9) */
+#define R_USB_DVSTCTR0_VBUSEN_Msk                 (0x200UL)    /* VBUSEN (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_WKUP_Pos                   (8UL)        /* WKUP (Bit 8) */
+#define R_USB_DVSTCTR0_WKUP_Msk                   (0x100UL)    /* WKUP (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_RWUPE_Pos                  (7UL)        /* RWUPE (Bit 7) */
+#define R_USB_DVSTCTR0_RWUPE_Msk                  (0x80UL)     /* RWUPE (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_USBRST_Pos                 (6UL)        /* USBRST (Bit 6) */
+#define R_USB_DVSTCTR0_USBRST_Msk                 (0x40UL)     /* USBRST (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_RESUME_Pos                 (5UL)        /* RESUME (Bit 5) */
+#define R_USB_DVSTCTR0_RESUME_Msk                 (0x20UL)     /* RESUME (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_UACT_Pos                   (4UL)        /* UACT (Bit 4) */
+#define R_USB_DVSTCTR0_UACT_Msk                   (0x10UL)     /* UACT (Bitfield-Mask: 0x01) */
+#define R_USB_DVSTCTR0_RHST_Pos                   (0UL)        /* RHST (Bit 0) */
+#define R_USB_DVSTCTR0_RHST_Msk                   (0x7UL)      /* RHST (Bitfield-Mask: 0x07) */
+
+/* TESTMODE */
+#define R_USB_TESTMODE_UTST_Pos                   (0UL)        /* UTST (Bit 0) */
+#define R_USB_TESTMODE_UTST_Msk                   (0xfUL)      /* UTST (Bitfield-Mask: 0x0f) */
+
+/* CFIFOSEL */
+#define R_USB_CFIFOSEL_RCNT_Pos                   (15UL)       /* RCNT (Bit 15) */
+#define R_USB_CFIFOSEL_RCNT_Msk                   (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define R_USB_CFIFOSEL_REW_Pos                    (14UL)       /* REW (Bit 14) */
+#define R_USB_CFIFOSEL_REW_Msk                    (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define R_USB_CFIFOSEL_MBW_Pos                    (10UL)       /* MBW (Bit 10) */
+#define R_USB_CFIFOSEL_MBW_Msk                    (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define R_USB_CFIFOSEL_BIGEND_Pos                 (8UL)        /* BIGEND (Bit 8) */
+#define R_USB_CFIFOSEL_BIGEND_Msk                 (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define R_USB_CFIFOSEL_ISEL_Pos                   (5UL)        /* ISEL (Bit 5) */
+#define R_USB_CFIFOSEL_ISEL_Msk                   (0x20UL)     /* ISEL (Bitfield-Mask: 0x01) */
+#define R_USB_CFIFOSEL_CURPIPE_Pos                (0UL)        /* CURPIPE (Bit 0) */
+#define R_USB_CFIFOSEL_CURPIPE_Msk                (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+/* CFIFOCTR */
+#define R_USB_CFIFOCTR_BVAL_Pos                   (15UL)       /* BVAL (Bit 15) */
+#define R_USB_CFIFOCTR_BVAL_Msk                   (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define R_USB_CFIFOCTR_BCLR_Pos                   (14UL)       /* BCLR (Bit 14) */
+#define R_USB_CFIFOCTR_BCLR_Msk                   (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define R_USB_CFIFOCTR_FRDY_Pos                   (13UL)       /* FRDY (Bit 13) */
+#define R_USB_CFIFOCTR_FRDY_Msk                   (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define R_USB_CFIFOCTR_DTLN_Pos                   (0UL)        /* DTLN (Bit 0) */
+#define R_USB_CFIFOCTR_DTLN_Msk                   (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+/* D0FIFOSEL */
+#define R_USB_D0FIFOSEL_RCNT_Pos                  (15UL)       /* RCNT (Bit 15) */
+#define R_USB_D0FIFOSEL_RCNT_Msk                  (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOSEL_REW_Pos                   (14UL)       /* REW (Bit 14) */
+#define R_USB_D0FIFOSEL_REW_Msk                   (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOSEL_DCLRM_Pos                 (13UL)       /* DCLRM (Bit 13) */
+#define R_USB_D0FIFOSEL_DCLRM_Msk                 (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOSEL_DREQE_Pos                 (12UL)       /* DREQE (Bit 12) */
+#define R_USB_D0FIFOSEL_DREQE_Msk                 (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOSEL_MBW_Pos                   (10UL)       /* MBW (Bit 10) */
+#define R_USB_D0FIFOSEL_MBW_Msk                   (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define R_USB_D0FIFOSEL_BIGEND_Pos                (8UL)        /* BIGEND (Bit 8) */
+#define R_USB_D0FIFOSEL_BIGEND_Msk                (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOSEL_CURPIPE_Pos               (0UL)        /* CURPIPE (Bit 0) */
+#define R_USB_D0FIFOSEL_CURPIPE_Msk               (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+/* D0FIFOCTR */
+#define R_USB_D0FIFOCTR_BVAL_Pos                  (15UL)       /* BVAL (Bit 15) */
+#define R_USB_D0FIFOCTR_BVAL_Msk                  (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOCTR_BCLR_Pos                  (14UL)       /* BCLR (Bit 14) */
+#define R_USB_D0FIFOCTR_BCLR_Msk                  (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOCTR_FRDY_Pos                  (13UL)       /* FRDY (Bit 13) */
+#define R_USB_D0FIFOCTR_FRDY_Msk                  (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define R_USB_D0FIFOCTR_DTLN_Pos                  (0UL)        /* DTLN (Bit 0) */
+#define R_USB_D0FIFOCTR_DTLN_Msk                  (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+/* D1FIFOSEL */
+#define R_USB_D1FIFOSEL_RCNT_Pos                  (15UL)       /* RCNT (Bit 15) */
+#define R_USB_D1FIFOSEL_RCNT_Msk                  (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOSEL_REW_Pos                   (14UL)       /* REW (Bit 14) */
+#define R_USB_D1FIFOSEL_REW_Msk                   (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOSEL_DCLRM_Pos                 (13UL)       /* DCLRM (Bit 13) */
+#define R_USB_D1FIFOSEL_DCLRM_Msk                 (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOSEL_DREQE_Pos                 (12UL)       /* DREQE (Bit 12) */
+#define R_USB_D1FIFOSEL_DREQE_Msk                 (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOSEL_MBW_Pos                   (10UL)       /* MBW (Bit 10) */
+#define R_USB_D1FIFOSEL_MBW_Msk                   (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define R_USB_D1FIFOSEL_BIGEND_Pos                (8UL)        /* BIGEND (Bit 8) */
+#define R_USB_D1FIFOSEL_BIGEND_Msk                (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOSEL_CURPIPE_Pos               (0UL)        /* CURPIPE (Bit 0) */
+#define R_USB_D1FIFOSEL_CURPIPE_Msk               (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+/* D1FIFOCTR */
+#define R_USB_D1FIFOCTR_BVAL_Pos                  (15UL)       /* BVAL (Bit 15) */
+#define R_USB_D1FIFOCTR_BVAL_Msk                  (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOCTR_BCLR_Pos                  (14UL)       /* BCLR (Bit 14) */
+#define R_USB_D1FIFOCTR_BCLR_Msk                  (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOCTR_FRDY_Pos                  (13UL)       /* FRDY (Bit 13) */
+#define R_USB_D1FIFOCTR_FRDY_Msk                  (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define R_USB_D1FIFOCTR_DTLN_Pos                  (0UL)        /* DTLN (Bit 0) */
+#define R_USB_D1FIFOCTR_DTLN_Msk                  (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+/* INTENB0 */
+#define R_USB_INTENB0_VBSE_Pos                    (15UL)       /* VBSE (Bit 15) */
+#define R_USB_INTENB0_VBSE_Msk                    (0x8000UL)   /* VBSE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB0_RSME_Pos                    (14UL)       /* RSME (Bit 14) */
+#define R_USB_INTENB0_RSME_Msk                    (0x4000UL)   /* RSME (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB0_SOFE_Pos                    (13UL)       /* SOFE (Bit 13) */
+#define R_USB_INTENB0_SOFE_Msk                    (0x2000UL)   /* SOFE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB0_DVSE_Pos                    (12UL)       /* DVSE (Bit 12) */
+#define R_USB_INTENB0_DVSE_Msk                    (0x1000UL)   /* DVSE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB0_CTRE_Pos                    (11UL)       /* CTRE (Bit 11) */
+#define R_USB_INTENB0_CTRE_Msk                    (0x800UL)    /* CTRE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB0_BEMPE_Pos                   (10UL)       /* BEMPE (Bit 10) */
+#define R_USB_INTENB0_BEMPE_Msk                   (0x400UL)    /* BEMPE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB0_NRDYE_Pos                   (9UL)        /* NRDYE (Bit 9) */
+#define R_USB_INTENB0_NRDYE_Msk                   (0x200UL)    /* NRDYE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB0_BRDYE_Pos                   (8UL)        /* BRDYE (Bit 8) */
+#define R_USB_INTENB0_BRDYE_Msk                   (0x100UL)    /* BRDYE (Bitfield-Mask: 0x01) */
+
+/* INTENB1 */
+#define R_USB_INTENB1_OVRCRE_Pos                  (15UL)       /* OVRCRE (Bit 15) */
+#define R_USB_INTENB1_OVRCRE_Msk                  (0x8000UL)   /* OVRCRE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB1_BCHGE_Pos                   (14UL)       /* BCHGE (Bit 14) */
+#define R_USB_INTENB1_BCHGE_Msk                   (0x4000UL)   /* BCHGE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB1_DTCHE_Pos                   (12UL)       /* DTCHE (Bit 12) */
+#define R_USB_INTENB1_DTCHE_Msk                   (0x1000UL)   /* DTCHE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB1_ATTCHE_Pos                  (11UL)       /* ATTCHE (Bit 11) */
+#define R_USB_INTENB1_ATTCHE_Msk                  (0x800UL)    /* ATTCHE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB1_L1RSMENDE_Pos               (9UL)        /*!< L1RSMENDE (Bit 9)                                     */
+#define R_USB_INTENB1_L1RSMENDE_Msk               (0x200UL)    /*!< L1RSMENDE (Bitfield-Mask: 0x01)                       */
+#define R_USB_INTENB1_LPMENDE_Pos                 (8UL)        /*!< LPMENDE (Bit 8)                                       */
+#define R_USB_INTENB1_LPMENDE_Msk                 (0x100UL)    /*!< LPMENDE (Bitfield-Mask: 0x01)                         */
+#define R_USB_INTENB1_EOFERRE_Pos                 (6UL)        /* EOFERRE (Bit 6) */
+#define R_USB_INTENB1_EOFERRE_Msk                 (0x40UL)     /* EOFERRE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB1_SIGNE_Pos                   (5UL)        /* SIGNE (Bit 5) */
+#define R_USB_INTENB1_SIGNE_Msk                   (0x20UL)     /* SIGNE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB1_SACKE_Pos                   (4UL)        /* SACKE (Bit 4) */
+#define R_USB_INTENB1_SACKE_Msk                   (0x10UL)     /* SACKE (Bitfield-Mask: 0x01) */
+#define R_USB_INTENB1_PDDETINTE0_Pos              (0UL)        /* PDDETINTE0 (Bit 0) */
+#define R_USB_INTENB1_PDDETINTE0_Msk              (0x1UL)      /* PDDETINTE0 (Bitfield-Mask: 0x01) */
+
+/* BRDYENB */
+#define R_USB_BRDYENB_PIPEBRDYE_Pos               (0UL)        /* PIPEBRDYE (Bit 0) */
+#define R_USB_BRDYENB_PIPEBRDYE_Msk               (0x1UL)      /* PIPEBRDYE (Bitfield-Mask: 0x01) */
+
+/* NRDYENB */
+#define R_USB_NRDYENB_PIPENRDYE_Pos               (0UL)        /* PIPENRDYE (Bit 0) */
+#define R_USB_NRDYENB_PIPENRDYE_Msk               (0x1UL)      /* PIPENRDYE (Bitfield-Mask: 0x01) */
+
+/* BEMPENB */
+#define R_USB_BEMPENB_PIPEBEMPE_Pos               (0UL)        /* PIPEBEMPE (Bit 0) */
+#define R_USB_BEMPENB_PIPEBEMPE_Msk               (0x1UL)      /* PIPEBEMPE (Bitfield-Mask: 0x01) */
+
+/* SOFCFG */
+#define R_USB_SOFCFG_TRNENSEL_Pos                 (8UL)        /* TRNENSEL (Bit 8) */
+#define R_USB_SOFCFG_TRNENSEL_Msk                 (0x100UL)    /* TRNENSEL (Bitfield-Mask: 0x01) */
+#define R_USB_SOFCFG_BRDYM_Pos                    (6UL)        /* BRDYM (Bit 6) */
+#define R_USB_SOFCFG_BRDYM_Msk                    (0x40UL)     /* BRDYM (Bitfield-Mask: 0x01) */
+#define R_USB_SOFCFG_INTL_Pos                     (5UL)        /* INTL (Bit 5) */
+#define R_USB_SOFCFG_INTL_Msk                     (0x20UL)     /* INTL (Bitfield-Mask: 0x01) */
+#define R_USB_SOFCFG_EDGESTS_Pos                  (4UL)        /* EDGESTS (Bit 4) */
+#define R_USB_SOFCFG_EDGESTS_Msk                  (0x10UL)     /* EDGESTS (Bitfield-Mask: 0x01) */
+
+/* PHYSET */
+#define R_USB_PHYSET_HSEB_Pos                     (15UL)       /* HSEB (Bit 15) */
+#define R_USB_PHYSET_HSEB_Msk                     (0x8000UL)   /* HSEB (Bitfield-Mask: 0x01) */
+#define R_USB_PHYSET_REPSTART_Pos                 (11UL)       /* REPSTART (Bit 11) */
+#define R_USB_PHYSET_REPSTART_Msk                 (0x800UL)    /* REPSTART (Bitfield-Mask: 0x01) */
+#define R_USB_PHYSET_REPSEL_Pos                   (8UL)        /* REPSEL (Bit 8) */
+#define R_USB_PHYSET_REPSEL_Msk                   (0x300UL)    /* REPSEL (Bitfield-Mask: 0x03) */
+#define R_USB_PHYSET_CLKSEL_Pos                   (4UL)        /* CLKSEL (Bit 4) */
+#define R_USB_PHYSET_CLKSEL_Msk                   (0x30UL)     /* CLKSEL (Bitfield-Mask: 0x03) */
+#define R_USB_PHYSET_CDPEN_Pos                    (3UL)        /* CDPEN (Bit 3) */
+#define R_USB_PHYSET_CDPEN_Msk                    (0x8UL)      /* CDPEN (Bitfield-Mask: 0x01) */
+#define R_USB_PHYSET_PLLRESET_Pos                 (1UL)        /* PLLRESET (Bit 1) */
+#define R_USB_PHYSET_PLLRESET_Msk                 (0x2UL)      /* PLLRESET (Bitfield-Mask: 0x01) */
+#define R_USB_PHYSET_DIRPD_Pos                    (0UL)        /* DIRPD (Bit 0) */
+#define R_USB_PHYSET_DIRPD_Msk                    (0x1UL)      /* DIRPD (Bitfield-Mask: 0x01) */
+
+/* INTSTS0 */
+#define R_USB_INTSTS0_VBINT_Pos                   (15UL)       /* VBINT (Bit 15) */
+#define R_USB_INTSTS0_VBINT_Msk                   (0x8000UL)   /* VBINT (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_RESM_Pos                    (14UL)       /* RESM (Bit 14) */
+#define R_USB_INTSTS0_RESM_Msk                    (0x4000UL)   /* RESM (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_SOFR_Pos                    (13UL)       /* SOFR (Bit 13) */
+#define R_USB_INTSTS0_SOFR_Msk                    (0x2000UL)   /* SOFR (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_DVST_Pos                    (12UL)       /* DVST (Bit 12) */
+#define R_USB_INTSTS0_DVST_Msk                    (0x1000UL)   /* DVST (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_CTRT_Pos                    (11UL)       /* CTRT (Bit 11) */
+#define R_USB_INTSTS0_CTRT_Msk                    (0x800UL)    /* CTRT (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_BEMP_Pos                    (10UL)       /* BEMP (Bit 10) */
+#define R_USB_INTSTS0_BEMP_Msk                    (0x400UL)    /* BEMP (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_NRDY_Pos                    (9UL)        /* NRDY (Bit 9) */
+#define R_USB_INTSTS0_NRDY_Msk                    (0x200UL)    /* NRDY (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_BRDY_Pos                    (8UL)        /* BRDY (Bit 8) */
+#define R_USB_INTSTS0_BRDY_Msk                    (0x100UL)    /* BRDY (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_VBSTS_Pos                   (7UL)        /* VBSTS (Bit 7) */
+#define R_USB_INTSTS0_VBSTS_Msk                   (0x80UL)     /* VBSTS (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_DVSQ_Pos                    (4UL)        /* DVSQ (Bit 4) */
+#define R_USB_INTSTS0_DVSQ_Msk                    (0x70UL)     /* DVSQ (Bitfield-Mask: 0x07) */
+#define R_USB_INTSTS0_VALID_Pos                   (3UL)        /* VALID (Bit 3) */
+#define R_USB_INTSTS0_VALID_Msk                   (0x8UL)      /* VALID (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS0_CTSQ_Pos                    (0UL)        /* CTSQ (Bit 0) */
+#define R_USB_INTSTS0_CTSQ_Msk                    (0x7UL)      /* CTSQ (Bitfield-Mask: 0x07) */
+
+/* INTSTS1 */
+#define R_USB_INTSTS1_OVRCR_Pos                   (15UL)       /* OVRCR (Bit 15) */
+#define R_USB_INTSTS1_OVRCR_Msk                   (0x8000UL)   /* OVRCR (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_BCHG_Pos                    (14UL)       /* BCHG (Bit 14) */
+#define R_USB_INTSTS1_BCHG_Msk                    (0x4000UL)   /* BCHG (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_DTCH_Pos                    (12UL)       /* DTCH (Bit 12) */
+#define R_USB_INTSTS1_DTCH_Msk                    (0x1000UL)   /* DTCH (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_ATTCH_Pos                   (11UL)       /* ATTCH (Bit 11) */
+#define R_USB_INTSTS1_ATTCH_Msk                   (0x800UL)    /* ATTCH (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_L1RSMEND_Pos                (9UL)        /* L1RSMEND (Bit 9) */
+#define R_USB_INTSTS1_L1RSMEND_Msk                (0x200UL)    /* L1RSMEND (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_LPMEND_Pos                  (8UL)        /* LPMEND (Bit 8) */
+#define R_USB_INTSTS1_LPMEND_Msk                  (0x100UL)    /* LPMEND (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_EOFERR_Pos                  (6UL)        /* EOFERR (Bit 6) */
+#define R_USB_INTSTS1_EOFERR_Msk                  (0x40UL)     /* EOFERR (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_SIGN_Pos                    (5UL)        /* SIGN (Bit 5) */
+#define R_USB_INTSTS1_SIGN_Msk                    (0x20UL)     /* SIGN (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_SACK_Pos                    (4UL)        /* SACK (Bit 4) */
+#define R_USB_INTSTS1_SACK_Msk                    (0x10UL)     /* SACK (Bitfield-Mask: 0x01) */
+#define R_USB_INTSTS1_PDDETINT0_Pos               (0UL)        /* PDDETINT0 (Bit 0) */
+#define R_USB_INTSTS1_PDDETINT0_Msk               (0x1UL)      /* PDDETINT0 (Bitfield-Mask: 0x01) */
+
+/* BRDYSTS */
+#define R_USB_BRDYSTS_PIPEBRDY_Pos                (0UL)        /* PIPEBRDY (Bit 0) */
+#define R_USB_BRDYSTS_PIPEBRDY_Msk                (0x3ffUL)    /* PIPEBRDY (Bitfield-Mask: 0x01) */
+
+/* NRDYSTS */
+#define R_USB_NRDYSTS_PIPENRDY_Pos                (0UL)        /* PIPENRDY (Bit 0) */
+#define R_USB_NRDYSTS_PIPENRDY_Msk                (0x1UL)      /* PIPENRDY (Bitfield-Mask: 0x01) */
+
+/* BEMPSTS */
+#define R_USB_BEMPSTS_PIPEBEMP_Pos                (0UL)        /* PIPEBEMP (Bit 0) */
+#define R_USB_BEMPSTS_PIPEBEMP_Msk                (0x1UL)      /* PIPEBEMP (Bitfield-Mask: 0x01) */
+
+/* FRMNUM */
+#define R_USB_FRMNUM_OVRN_Pos                     (15UL)       /* OVRN (Bit 15) */
+#define R_USB_FRMNUM_OVRN_Msk                     (0x8000UL)   /* OVRN (Bitfield-Mask: 0x01) */
+#define R_USB_FRMNUM_CRCE_Pos                     (14UL)       /* CRCE (Bit 14) */
+#define R_USB_FRMNUM_CRCE_Msk                     (0x4000UL)   /* CRCE (Bitfield-Mask: 0x01) */
+#define R_USB_FRMNUM_FRNM_Pos                     (0UL)        /* FRNM (Bit 0) */
+#define R_USB_FRMNUM_FRNM_Msk                     (0x7ffUL)    /* FRNM (Bitfield-Mask: 0x7ff) */
+
+/* UFRMNUM */
+#define R_USB_UFRMNUM_DVCHG_Pos                   (15UL)       /* DVCHG (Bit 15) */
+#define R_USB_UFRMNUM_DVCHG_Msk                   (0x8000UL)   /* DVCHG (Bitfield-Mask: 0x01) */
+#define R_USB_UFRMNUM_UFRNM_Pos                   (0UL)        /* UFRNM (Bit 0) */
+#define R_USB_UFRMNUM_UFRNM_Msk                   (0x7UL)      /* UFRNM (Bitfield-Mask: 0x07) */
+
+/* USBADDR */
+#define R_USB_USBADDR_STSRECOV0_Pos               (8UL)        /* STSRECOV0 (Bit 8) */
+#define R_USB_USBADDR_STSRECOV0_Msk               (0x700UL)    /* STSRECOV0 (Bitfield-Mask: 0x07) */
+#define R_USB_USBADDR_USBADDR_Pos                 (0UL)        /* USBADDR (Bit 0) */
+#define R_USB_USBADDR_USBADDR_Msk                 (0x7fUL)     /* USBADDR (Bitfield-Mask: 0x7f) */
+
+/* USBREQ */
+#define R_USB_USBREQ_BREQUEST_Pos                 (8UL)        /* BREQUEST (Bit 8) */
+#define R_USB_USBREQ_BREQUEST_Msk                 (0xff00UL)   /* BREQUEST (Bitfield-Mask: 0xff) */
+#define R_USB_USBREQ_BMREQUESTTYPE_Pos            (0UL)        /* BMREQUESTTYPE (Bit 0) */
+#define R_USB_USBREQ_BMREQUESTTYPE_Msk            (0xffUL)     /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
+
+/* USBVAL */
+#define R_USB_USBVAL_WVALUE_Pos                   (0UL)        /* WVALUE (Bit 0) */
+#define R_USB_USBVAL_WVALUE_Msk                   (0xffffUL)   /* WVALUE (Bitfield-Mask: 0xffff) */
+
+/* USBINDX */
+#define R_USB_USBINDX_WINDEX_Pos                  (0UL)        /* WINDEX (Bit 0) */
+#define R_USB_USBINDX_WINDEX_Msk                  (0xffffUL)   /* WINDEX (Bitfield-Mask: 0xffff) */
+
+/* USBLENG */
+#define R_USB_USBLENG_WLENGTH_Pos                 (0UL)        /* WLENGTH (Bit 0) */
+#define R_USB_USBLENG_WLENGTH_Msk                 (0xffffUL)   /* WLENGTH (Bitfield-Mask: 0xffff) */
+
+/* DCPCFG */
+#define R_USB_DCPCFG_CNTMD_Pos                    (8UL)        /* CNTMD (Bit 8) */
+#define R_USB_DCPCFG_CNTMD_Msk                    (0x100UL)    /* CNTMD (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCFG_SHTNAK_Pos                   (7UL)        /* SHTNAK (Bit 7) */
+#define R_USB_DCPCFG_SHTNAK_Msk                   (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCFG_DIR_Pos                      (4UL)        /* DIR (Bit 4) */
+#define R_USB_DCPCFG_DIR_Msk                      (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+
+/* DCPMAXP */
+#define R_USB_DCPMAXP_DEVSEL_Pos                  (12UL)       /* DEVSEL (Bit 12) */
+#define R_USB_DCPMAXP_DEVSEL_Msk                  (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define R_USB_DCPMAXP_MXPS_Pos                    (0UL)        /* MXPS (Bit 0) */
+#define R_USB_DCPMAXP_MXPS_Msk                    (0x7fUL)     /* MXPS (Bitfield-Mask: 0x7f) */
+
+/* DCPCTR */
+#define R_USB_DCPCTR_BSTS_Pos                     (15UL)       /* BSTS (Bit 15) */
+#define R_USB_DCPCTR_BSTS_Msk                     (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCTR_SUREQ_Pos                    (14UL)       /* SUREQ (Bit 14) */
+#define R_USB_DCPCTR_SUREQ_Msk                    (0x4000UL)   /* SUREQ (Bitfield-Mask: 0x01) */
+#define R_USB_HS0_DCPCTR_CSCLR_Pos                (13UL)       /*!< CSCLR (Bit 13)                                        */
+#define R_USB_DCPCTR_CSCLR_Msk                    (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
+#define R_USB_DCPCTR_CSSTS_Pos                    (12UL)       /*!< CSSTS (Bit 12)                                        */
+#define R_USB_DCPCTR_CSSTS_Msk                    (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
+#define R_USB_DCPCTR_SUREQCLR_Pos                 (11UL)       /* SUREQCLR (Bit 11) */
+#define R_USB_DCPCTR_SUREQCLR_Msk                 (0x800UL)    /* SUREQCLR (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCTR_SQCLR_Pos                    (8UL)        /* SQCLR (Bit 8) */
+#define R_USB_DCPCTR_SQCLR_Msk                    (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCTR_SQSET_Pos                    (7UL)        /* SQSET (Bit 7) */
+#define R_USB_DCPCTR_SQSET_Msk                    (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCTR_SQMON_Pos                    (6UL)        /* SQMON (Bit 6) */
+#define R_USB_DCPCTR_SQMON_Msk                    (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCTR_PBUSY_Pos                    (5UL)        /* PBUSY (Bit 5) */
+#define R_USB_DCPCTR_PBUSY_Msk                    (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCTR_CCPL_Pos                     (2UL)        /* CCPL (Bit 2) */
+#define R_USB_DCPCTR_CCPL_Msk                     (0x4UL)      /* CCPL (Bitfield-Mask: 0x01) */
+#define R_USB_DCPCTR_PID_Pos                      (0UL)        /* PID (Bit 0) */
+#define R_USB_DCPCTR_PID_Msk                      (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+
+/* PIPESEL */
+#define R_USB_PIPESEL_PIPESEL_Pos                 (0UL)        /* PIPESEL (Bit 0) */
+#define R_USB_PIPESEL_PIPESEL_Msk                 (0xfUL)      /* PIPESEL (Bitfield-Mask: 0x0f) */
+
+/* PIPECFG */
+#define R_USB_PIPECFG_TYPE_Pos                    (14UL)       /* TYPE (Bit 14) */
+#define R_USB_PIPECFG_TYPE_Msk                    (0xc000UL)   /* TYPE (Bitfield-Mask: 0x03) */
+#define R_USB_PIPECFG_BFRE_Pos                    (10UL)       /* BFRE (Bit 10) */
+#define R_USB_PIPECFG_BFRE_Msk                    (0x400UL)    /* BFRE (Bitfield-Mask: 0x01) */
+#define R_USB_PIPECFG_DBLB_Pos                    (9UL)        /* DBLB (Bit 9) */
+#define R_USB_PIPECFG_DBLB_Msk                    (0x200UL)    /* DBLB (Bitfield-Mask: 0x01) */
+#define R_USB_PIPECFG_CNTMD_Pos                   (8UL)        /*!< CNTMD (Bit 8)                                         */
+#define R_USB_PIPECFG_CNTMD_Msk                   (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+#define R_USB_PIPECFG_SHTNAK_Pos                  (7UL)        /* SHTNAK (Bit 7) */
+#define R_USB_PIPECFG_SHTNAK_Msk                  (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define R_USB_PIPECFG_DIR_Pos                     (4UL)        /* DIR (Bit 4) */
+#define R_USB_PIPECFG_DIR_Msk                     (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+#define R_USB_PIPECFG_EPNUM_Pos                   (0UL)        /* EPNUM (Bit 0) */
+#define R_USB_PIPECFG_EPNUM_Msk                   (0xfUL)      /* EPNUM (Bitfield-Mask: 0x0f) */
+
+/* PIPEBUF */
+#define R_USB_PIPEBUF_BUFSIZE_Pos                 (10UL)       /*!< BUFSIZE (Bit 10)                                      */
+#define R_USB_PIPEBUF_BUFSIZE_Msk                 (0x7c00UL)   /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
+#define R_USB_PIPEBUF_BUFNMB_Pos                  (0UL)        /*!< BUFNMB (Bit 0)                                        */
+#define R_USB_PIPEBUF_BUFNMB_Msk                  (0xffUL)     /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
+
+/* PIPEMAXP */
+#define R_USB_PIPEMAXP_DEVSEL_Pos                 (12UL)       /* DEVSEL (Bit 12) */
+#define R_USB_PIPEMAXP_DEVSEL_Msk                 (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define R_USB_PIPEMAXP_MXPS_Pos                   (0UL)        /* MXPS (Bit 0) */
+#define R_USB_PIPEMAXP_MXPS_Msk                   (0x1ffUL)    /* MXPS (Bitfield-Mask: 0x1ff) */
+
+/* PIPEPERI */
+#define R_USB_PIPEPERI_IFIS_Pos                   (12UL)       /* IFIS (Bit 12) */
+#define R_USB_PIPEPERI_IFIS_Msk                   (0x1000UL)   /* IFIS (Bitfield-Mask: 0x01) */
+#define R_USB_PIPEPERI_IITV_Pos                   (0UL)        /* IITV (Bit 0) */
+#define R_USB_PIPEPERI_IITV_Msk                   (0x7UL)      /* IITV (Bitfield-Mask: 0x07) */
+
+/* PIPE_CTR */
+#define R_USB_PIPE_CTR_BSTS_Pos                   (15UL)       /* BSTS (Bit 15) */
+#define R_USB_PIPE_CTR_BSTS_Msk                   (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_INBUFM_Pos                 (14UL)       /* INBUFM (Bit 14) */
+#define R_USB_PIPE_CTR_INBUFM_Msk                 (0x4000UL)   /* INBUFM (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_CSCLR_Pos                  (13UL)       /* CSCLR (Bit 13) */
+#define R_USB_PIPE_CTR_CSCLR_Msk                  (0x2000UL)   /* CSCLR (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_CSSTS_Pos                  (12UL)       /* CSSTS (Bit 12) */
+#define R_USB_PIPE_CTR_CSSTS_Msk                  (0x1000UL)   /* CSSTS (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_ATREPM_Pos                 (10UL)       /* ATREPM (Bit 10) */
+#define R_USB_PIPE_CTR_ATREPM_Msk                 (0x400UL)    /* ATREPM (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_ACLRM_Pos                  (9UL)        /* ACLRM (Bit 9) */
+#define R_USB_PIPE_CTR_ACLRM_Msk                  (0x200UL)    /* ACLRM (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_SQCLR_Pos                  (8UL)        /* SQCLR (Bit 8) */
+#define R_USB_PIPE_CTR_SQCLR_Msk                  (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_SQSET_Pos                  (7UL)        /* SQSET (Bit 7) */
+#define R_USB_PIPE_CTR_SQSET_Msk                  (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_SQMON_Pos                  (6UL)        /* SQMON (Bit 6) */
+#define R_USB_PIPE_CTR_SQMON_Msk                  (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_PBUSY_Pos                  (5UL)        /* PBUSY (Bit 5) */
+#define R_USB_PIPE_CTR_PBUSY_Msk                  (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define R_USB_PIPE_CTR_PID_Pos                    (0UL)        /* PID (Bit 0) */
+#define R_USB_PIPE_CTR_PID_Msk                    (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+
+/* DEVADD */
+#define R_USB_DEVADD_UPPHUB_Pos                   (11UL)       /* UPPHUB (Bit 11) */
+#define R_USB_DEVADD_UPPHUB_Msk                   (0x7800UL)   /* UPPHUB (Bitfield-Mask: 0x0f) */
+#define R_USB_DEVADD_HUBPORT_Pos                  (8UL)        /* HUBPORT (Bit 8) */
+#define R_USB_DEVADD_HUBPORT_Msk                  (0x700UL)    /* HUBPORT (Bitfield-Mask: 0x07) */
+#define R_USB_DEVADD_USBSPD_Pos                   (6UL)        /* USBSPD (Bit 6) */
+#define R_USB_DEVADD_USBSPD_Msk                   (0xc0UL)     /* USBSPD (Bitfield-Mask: 0x03) */
+
+/* USBBCCTRL0 */
+#define R_USB_USBBCCTRL0_PDDETSTS0_Pos            (9UL)        /* PDDETSTS0 (Bit 9) */
+#define R_USB_USBBCCTRL0_PDDETSTS0_Msk            (0x200UL)    /* PDDETSTS0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_CHGDETSTS0_Pos           (8UL)        /* CHGDETSTS0 (Bit 8) */
+#define R_USB_USBBCCTRL0_CHGDETSTS0_Msk           (0x100UL)    /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_BATCHGE0_Pos             (7UL)        /* BATCHGE0 (Bit 7) */
+#define R_USB_USBBCCTRL0_BATCHGE0_Msk             (0x80UL)     /* BATCHGE0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_VDMSRCE0_Pos             (5UL)        /* VDMSRCE0 (Bit 5) */
+#define R_USB_USBBCCTRL0_VDMSRCE0_Msk             (0x20UL)     /* VDMSRCE0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_IDPSINKE0_Pos            (4UL)        /* IDPSINKE0 (Bit 4) */
+#define R_USB_USBBCCTRL0_IDPSINKE0_Msk            (0x10UL)     /* IDPSINKE0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_VDPSRCE0_Pos             (3UL)        /* VDPSRCE0 (Bit 3) */
+#define R_USB_USBBCCTRL0_VDPSRCE0_Msk             (0x8UL)      /* VDPSRCE0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_IDMSINKE0_Pos            (2UL)        /* IDMSINKE0 (Bit 2) */
+#define R_USB_USBBCCTRL0_IDMSINKE0_Msk            (0x4UL)      /* IDMSINKE0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_IDPSRCE0_Pos             (1UL)        /* IDPSRCE0 (Bit 1) */
+#define R_USB_USBBCCTRL0_IDPSRCE0_Msk             (0x2UL)      /* IDPSRCE0 (Bitfield-Mask: 0x01) */
+#define R_USB_USBBCCTRL0_RPDME0_Pos               (0UL)        /* RPDME0 (Bit 0) */
+#define R_USB_USBBCCTRL0_RPDME0_Msk               (0x1UL)      /* RPDME0 (Bitfield-Mask: 0x01) */
+
+/* UCKSEL */
+#define R_USB_UCKSEL_UCKSELC_Pos                  (0UL)        /* UCKSELC (Bit 0) */
+#define R_USB_UCKSEL_UCKSELC_Msk                  (0x1UL)      /* UCKSELC (Bitfield-Mask: 0x01) */
+
+/* USBMC */
+#define R_USB_USBMC_VDCEN_Pos                     (7UL)        /* VDCEN (Bit 7) */
+#define R_USB_USBMC_VDCEN_Msk                     (0x80UL)     /* VDCEN (Bitfield-Mask: 0x01) */
+#define R_USB_USBMC_VDDUSBE_Pos                   (0UL)        /* VDDUSBE (Bit 0) */
+#define R_USB_USBMC_VDDUSBE_Msk                   (0x1UL)      /* VDDUSBE (Bitfield-Mask: 0x01) */
+
+/* PHYSLEW */
+#define R_USB_PHYSLEW_SLEWF01_Pos                 (3UL)        /* SLEWF01 (Bit 3) */
+#define R_USB_PHYSLEW_SLEWF01_Msk                 (0x8UL)      /* SLEWF01 (Bitfield-Mask: 0x01) */
+#define R_USB_PHYSLEW_SLEWF00_Pos                 (2UL)        /* SLEWF00 (Bit 2) */
+#define R_USB_PHYSLEW_SLEWF00_Msk                 (0x4UL)      /* SLEWF00 (Bitfield-Mask: 0x01) */
+#define R_USB_PHYSLEW_SLEWR01_Pos                 (1UL)        /* SLEWR01 (Bit 1) */
+#define R_USB_PHYSLEW_SLEWR01_Msk                 (0x2UL)      /* SLEWR01 (Bitfield-Mask: 0x01) */
+#define R_USB_PHYSLEW_SLEWR00_Pos                 (0UL)        /* SLEWR00 (Bit 0) */
+#define R_USB_PHYSLEW_SLEWR00_Msk                 (0x1UL)      /* SLEWR00 (Bitfield-Mask: 0x01) */
+
+/* LPCTRL */
+#define R_USB_LPCTRL_HWUPM_Pos                    (7UL)        /* HWUPM (Bit 7) */
+#define R_USB_LPCTRL_HWUPM_Msk                    (0x80UL)     /* HWUPM (Bitfield-Mask: 0x01) */
+
+/* LPSTS */
+#define R_USB_LPSTS_SUSPENDM_Pos                  (14UL)       /* SUSPENDM (Bit 14) */
+#define R_USB_LPSTS_SUSPENDM_Msk                  (0x4000UL)   /* SUSPENDM (Bitfield-Mask: 0x01) */
+
+/* BCCTRL */
+#define R_USB_BCCTRL_PDDETSTS_Pos                 (9UL)        /* PDDETSTS (Bit 9) */
+#define R_USB_BCCTRL_PDDETSTS_Msk                 (0x200UL)    /* PDDETSTS (Bitfield-Mask: 0x01) */
+#define R_USB_BCCTRL_CHGDETSTS_Pos                (8UL)        /* CHGDETSTS (Bit 8) */
+#define R_USB_BCCTRL_CHGDETSTS_Msk                (0x100UL)    /* CHGDETSTS (Bitfield-Mask: 0x01) */
+#define R_USB_BCCTRL_DCPMODE_Pos                  (5UL)        /* DCPMODE (Bit 5) */
+#define R_USB_BCCTRL_DCPMODE_Msk                  (0x20UL)     /* DCPMODE (Bitfield-Mask: 0x01) */
+#define R_USB_BCCTRL_VDMSRCE_Pos                  (4UL)        /* VDMSRCE (Bit 4) */
+#define R_USB_BCCTRL_VDMSRCE_Msk                  (0x10UL)     /* VDMSRCE (Bitfield-Mask: 0x01) */
+#define R_USB_BCCTRL_IDPSINKE_Pos                 (3UL)        /* IDPSINKE (Bit 3) */
+#define R_USB_BCCTRL_IDPSINKE_Msk                 (0x8UL)      /* IDPSINKE (Bitfield-Mask: 0x01) */
+#define R_USB_BCCTRL_VDPSRCE_Pos                  (2UL)        /* VDPSRCE (Bit 2) */
+#define R_USB_BCCTRL_VDPSRCE_Msk                  (0x4UL)      /* VDPSRCE (Bitfield-Mask: 0x01) */
+#define R_USB_BCCTRL_IDMSINKE_Pos                 (1UL)        /* IDMSINKE (Bit 1) */
+#define R_USB_BCCTRL_IDMSINKE_Msk                 (0x2UL)      /* IDMSINKE (Bitfield-Mask: 0x01) */
+#define R_USB_BCCTRL_IDPSRCE_Pos                  (0UL)        /* IDPSRCE (Bit 0) */
+#define R_USB_BCCTRL_IDPSRCE_Msk                  (0x1UL)      /* IDPSRCE (Bitfield-Mask: 0x01) */
+
+/* PL1CTRL1 */
+#define R_USB_PL1CTRL1_L1EXTMD_Pos                (14UL)       /* L1EXTMD (Bit 14) */
+#define R_USB_PL1CTRL1_L1EXTMD_Msk                (0x4000UL)   /* L1EXTMD (Bitfield-Mask: 0x01) */
+#define R_USB_PL1CTRL1_HIRDTHR_Pos                (8UL)        /* HIRDTHR (Bit 8) */
+#define R_USB_PL1CTRL1_HIRDTHR_Msk                (0xf00UL)    /* HIRDTHR (Bitfield-Mask: 0x0f) */
+#define R_USB_PL1CTRL1_DVSQ_Pos                   (4UL)        /* DVSQ (Bit 4) */
+#define R_USB_PL1CTRL1_DVSQ_Msk                   (0xf0UL)     /* DVSQ (Bitfield-Mask: 0x0f) */
+#define R_USB_PL1CTRL1_L1NEGOMD_Pos               (3UL)        /* L1NEGOMD (Bit 3) */
+#define R_USB_PL1CTRL1_L1NEGOMD_Msk               (0x8UL)      /* L1NEGOMD (Bitfield-Mask: 0x01) */
+#define R_USB_PL1CTRL1_L1RESPMD_Pos               (1UL)        /* L1RESPMD (Bit 1) */
+#define R_USB_PL1CTRL1_L1RESPMD_Msk               (0x6UL)      /* L1RESPMD (Bitfield-Mask: 0x03) */
+#define R_USB_PL1CTRL1_L1RESPEN_Pos               (0UL)        /* L1RESPEN (Bit 0) */
+#define R_USB_PL1CTRL1_L1RESPEN_Msk               (0x1UL)      /* L1RESPEN (Bitfield-Mask: 0x01) */
+
+/* PL1CTRL2 */
+#define R_USB_PL1CTRL2_RWEMON_Pos                 (12UL)       /* RWEMON (Bit 12) */
+#define R_USB_PL1CTRL2_RWEMON_Msk                 (0x1000UL)   /* RWEMON (Bitfield-Mask: 0x01) */
+#define R_USB_PL1CTRL2_HIRDMON_Pos                (8UL)        /* HIRDMON (Bit 8) */
+#define R_USB_PL1CTRL2_HIRDMON_Msk                (0xf00UL)    /* HIRDMON (Bitfield-Mask: 0x0f) */
+
+/* HL1CTRL1 */
+#define R_USB_HL1CTRL1_L1STATUS_Pos               (1UL)        /* L1STATUS (Bit 1) */
+#define R_USB_HL1CTRL1_L1STATUS_Msk               (0x6UL)      /* L1STATUS (Bitfield-Mask: 0x03) */
+#define R_USB_HL1CTRL1_L1REQ_Pos                  (0UL)        /* L1REQ (Bit 0) */
+#define R_USB_HL1CTRL1_L1REQ_Msk                  (0x1UL)      /* L1REQ (Bitfield-Mask: 0x01) */
+
+/* HL1CTRL2 */
+#define R_USB_HL1CTRL2_BESL_Pos                   (15UL)       /* BESL (Bit 15) */
+#define R_USB_HL1CTRL2_BESL_Msk                   (0x8000UL)   /* BESL (Bitfield-Mask: 0x01) */
+#define R_USB_HL1CTRL2_L1RWE_Pos                  (12UL)       /* L1RWE (Bit 12) */
+#define R_USB_HL1CTRL2_L1RWE_Msk                  (0x1000UL)   /* L1RWE (Bitfield-Mask: 0x01) */
+#define R_USB_HL1CTRL2_HIRD_Pos                   (8UL)        /* HIRD (Bit 8) */
+#define R_USB_HL1CTRL2_HIRD_Msk                   (0xf00UL)    /* HIRD (Bitfield-Mask: 0x0f) */
+#define R_USB_HL1CTRL2_L1ADDR_Pos                 (0UL)        /* L1ADDR (Bit 0) */
+#define R_USB_HL1CTRL2_L1ADDR_Msk                 (0xfUL)      /* L1ADDR (Bitfield-Mask: 0x0f) */
+
+/* PHYTRIM1 */
+#define R_USB_PHYTRIM1_IMPOFFSET_Pos              (12UL)       /*!< IMPOFFSET (Bit 12)                                    */
+#define R_USB_PHYTRIM1_IMPOFFSET_Msk              (0x7000UL)   /*!< IMPOFFSET (Bitfield-Mask: 0x07)                       */
+#define R_USB_PHYTRIM1_HSIUP_Pos                  (8UL)        /*!< HSIUP (Bit 8)                                         */
+#define R_USB_PHYTRIM1_HSIUP_Msk                  (0xf00UL)    /*!< HSIUP (Bitfield-Mask: 0x0f)                           */
+#define R_USB_PHYTRIM1_PCOMPENB_Pos               (7UL)        /*!< PCOMPENB (Bit 7)                                      */
+#define R_USB_PHYTRIM1_PCOMPENB_Msk               (0x80UL)     /*!< PCOMPENB (Bitfield-Mask: 0x01)                        */
+#define R_USB_PHYTRIM1_DFALL_Pos                  (2UL)        /*!< DFALL (Bit 2)                                         */
+#define R_USB_PHYTRIM1_DFALL_Msk                  (0xcUL)      /*!< DFALL (Bitfield-Mask: 0x03)                           */
+#define R_USB_PHYTRIM1_DRISE_Pos                  (0UL)        /*!< DRISE (Bit 0)                                         */
+#define R_USB_PHYTRIM1_DRISE_Msk                  (0x3UL)      /*!< DRISE (Bitfield-Mask: 0x03)                           */
+
+/* PHYTRIM2 */
+#define R_USB_PHYTRIM2_DIS_Pos                    (12UL)       /*!< DIS (Bit 12)                                          */
+#define R_USB_PHYTRIM2_DIS_Msk                    (0x7000UL)   /*!< DIS (Bitfield-Mask: 0x07)                             */
+#define R_USB_PHYTRIM2_PDR_Pos                    (8UL)        /*!< PDR (Bit 8)                                           */
+#define R_USB_PHYTRIM2_PDR_Msk                    (0x300UL)    /*!< PDR (Bitfield-Mask: 0x03)                             */
+#define R_USB_PHYTRIM2_HSRXENMO_Pos               (7UL)        /*!< HSRXENMO (Bit 7)                                      */
+#define R_USB_PHYTRIM2_HSRXENMO_Msk               (0x80UL)     /*!< HSRXENMO (Bitfield-Mask: 0x01)                        */
+#define R_USB_PHYTRIM2_SQU_Pos                    (0UL)        /*!< SQU (Bit 0)                                           */
+#define R_USB_PHYTRIM2_SQU_Msk                    (0xfUL)      /*!< SQU (Bitfield-Mask: 0x0f)                             */
+
+/* DPUSR0R */
+#define R_USB_DPUSR0R_DVBSTSHM_Pos                (23UL)       /* DVBSTSHM (Bit 23) */
+#define R_USB_DPUSR0R_DVBSTSHM_Msk                (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_DOVCBHM_Pos                 (21UL)       /* DOVCBHM (Bit 21) */
+#define R_USB_DPUSR0R_DOVCBHM_Msk                 (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_DOVCAHM_Pos                 (20UL)       /* DOVCAHM (Bit 20) */
+#define R_USB_DPUSR0R_DOVCAHM_Msk                 (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
+
+/* DPUSR1R */
+#define R_USB_DPUSR1R_DVBSTSH_Pos                 (23UL)       /* DVBSTSH (Bit 23) */
+#define R_USB_DPUSR1R_DVBSTSH_Msk                 (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_DOVCBH_Pos                  (21UL)       /* DOVCBH (Bit 21) */
+#define R_USB_DPUSR1R_DOVCBH_Msk                  (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_DOVCAH_Pos                  (20UL)       /* DOVCAH (Bit 20) */
+#define R_USB_DPUSR1R_DOVCAH_Msk                  (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_DVBSTSHE_Pos                (7UL)        /* DVBSTSHE (Bit 7) */
+#define R_USB_DPUSR1R_DVBSTSHE_Msk                (0x80UL)     /* DVBSTSHE (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_DOVCBHE_Pos                 (5UL)        /* DOVCBHE (Bit 5) */
+#define R_USB_DPUSR1R_DOVCBHE_Msk                 (0x20UL)     /* DOVCBHE (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_DOVCAHE_Pos                 (4UL)        /* DOVCAHE (Bit 4) */
+#define R_USB_DPUSR1R_DOVCAHE_Msk                 (0x10UL)     /* DOVCAHE (Bitfield-Mask: 0x01) */
+
+/* DPUSR2R */
+#define R_USB_DPUSR2R_DMINTE_Pos                  (9UL)        /* DMINTE (Bit 9) */
+#define R_USB_DPUSR2R_DMINTE_Msk                  (0x200UL)    /* DMINTE (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR2R_DPINTE_Pos                  (8UL)        /* DPINTE (Bit 8) */
+#define R_USB_DPUSR2R_DPINTE_Msk                  (0x100UL)    /* DPINTE (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR2R_DMVAL_Pos                   (5UL)        /* DMVAL (Bit 5) */
+#define R_USB_DPUSR2R_DMVAL_Msk                   (0x20UL)     /* DMVAL (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR2R_DPVAL_Pos                   (4UL)        /* DPVAL (Bit 4) */
+#define R_USB_DPUSR2R_DPVAL_Msk                   (0x10UL)     /* DPVAL (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR2R_DMINT_Pos                   (1UL)        /* DMINT (Bit 1) */
+#define R_USB_DPUSR2R_DMINT_Msk                   (0x2UL)      /* DMINT (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR2R_DPINT_Pos                   (0UL)        /* DPINT (Bit 0) */
+#define R_USB_DPUSR2R_DPINT_Msk                   (0x1UL)      /* DPINT (Bitfield-Mask: 0x01) */
+
+/* DPUSRCR */
+#define R_USB_DPUSRCR_FIXPHYPD_Pos                (1UL)        /* FIXPHYPD (Bit 1) */
+#define R_USB_DPUSRCR_FIXPHYPD_Msk                (0x2UL)      /* FIXPHYPD (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSRCR_FIXPHY_Pos                  (0UL)        /* FIXPHY (Bit 0) */
+#define R_USB_DPUSRCR_FIXPHY_Msk                  (0x1UL)      /* FIXPHY (Bitfield-Mask: 0x01) */
+
+/* DPUSR0R_FS */
+#define R_USB_DPUSR0R_FS_DVBSTS0_Pos              (23UL)       /* DVBSTS0 (Bit 23) */
+#define R_USB_DPUSR0R_FS_DVBSTS0_Msk              (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_DOVCB0_Pos               (21UL)       /* DOVCB0 (Bit 21) */
+#define R_USB_DPUSR0R_FS_DOVCB0_Msk               (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_DOVCA0_Pos               (20UL)       /* DOVCA0 (Bit 20) */
+#define R_USB_DPUSR0R_FS_DOVCA0_Msk               (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_DM0_Pos                  (17UL)       /* DM0 (Bit 17) */
+#define R_USB_DPUSR0R_FS_DM0_Msk                  (0x20000UL)  /* DM0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_DP0_Pos                  (16UL)       /* DP0 (Bit 16) */
+#define R_USB_DPUSR0R_FS_DP0_Msk                  (0x10000UL)  /* DP0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_FIXPHY0_Pos              (4UL)        /* FIXPHY0 (Bit 4) */
+#define R_USB_DPUSR0R_FS_FIXPHY0_Msk              (0x10UL)     /* FIXPHY0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_DRPD0_Pos                (3UL)        /* DRPD0 (Bit 3) */
+#define R_USB_DPUSR0R_FS_DRPD0_Msk                (0x8UL)      /* DRPD0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_RPUE0_Pos                (1UL)        /* RPUE0 (Bit 1) */
+#define R_USB_DPUSR0R_FS_RPUE0_Msk                (0x2UL)      /* RPUE0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR0R_FS_SRPC0_Pos                (0UL)        /* SRPC0 (Bit 0) */
+#define R_USB_DPUSR0R_FS_SRPC0_Msk                (0x1UL)      /* SRPC0 (Bitfield-Mask: 0x01) */
+
+/* DPUSR1R_FS */
+#define R_USB_DPUSR1R_FS_DVBINT0_Pos              (23UL)       /* DVBINT0 (Bit 23) */
+#define R_USB_DPUSR1R_FS_DVBINT0_Msk              (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DOVRCRB0_Pos             (21UL)       /* DOVRCRB0 (Bit 21) */
+#define R_USB_DPUSR1R_FS_DOVRCRB0_Msk             (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DOVRCRA0_Pos             (20UL)       /* DOVRCRA0 (Bit 20) */
+#define R_USB_DPUSR1R_FS_DOVRCRA0_Msk             (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DMINT0_Pos               (17UL)       /* DMINT0 (Bit 17) */
+#define R_USB_DPUSR1R_FS_DMINT0_Msk               (0x20000UL)  /* DMINT0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DPINT0_Pos               (16UL)       /* DPINT0 (Bit 16) */
+#define R_USB_DPUSR1R_FS_DPINT0_Msk               (0x10000UL)  /* DPINT0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DVBSE0_Pos               (7UL)        /* DVBSE0 (Bit 7) */
+#define R_USB_DPUSR1R_FS_DVBSE0_Msk               (0x80UL)     /* DVBSE0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DOVRCRBE0_Pos            (5UL)        /* DOVRCRBE0 (Bit 5) */
+#define R_USB_DPUSR1R_FS_DOVRCRBE0_Msk            (0x20UL)     /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DOVRCRAE0_Pos            (4UL)        /* DOVRCRAE0 (Bit 4) */
+#define R_USB_DPUSR1R_FS_DOVRCRAE0_Msk            (0x10UL)     /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DMINTE0_Pos              (1UL)        /* DMINTE0 (Bit 1) */
+#define R_USB_DPUSR1R_FS_DMINTE0_Msk              (0x2UL)      /* DMINTE0 (Bitfield-Mask: 0x01) */
+#define R_USB_DPUSR1R_FS_DPINTE0_Pos              (0UL)        /* DPINTE0 (Bit 0) */
+#define R_USB_DPUSR1R_FS_DPINTE0_Msk              (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
+
+/*--------------------------------------------------------------------*/
+/* Register Bit Utils                                           */
+/*--------------------------------------------------------------------*/
+#define R_USB_PIPE_CTR_PID_NAK                    (0U << R_USB_PIPE_CTR_PID_Pos)    /* NAK response */
+#define R_USB_PIPE_CTR_PID_BUF                    (1U << R_USB_PIPE_CTR_PID_Pos)    /* BUF response (depends buffer state) */
+#define R_USB_PIPE_CTR_PID_STALL                  (2U << R_USB_PIPE_CTR_PID_Pos)    /* STALL response */
+#define R_USB_PIPE_CTR_PID_STALL2                 (3U << R_USB_PIPE_CTR_PID_Pos)    /* Also STALL response */
+
+#define R_USB_DVSTCTR0_RHST_LS                    (1U << R_USB_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
+#define R_USB_DVSTCTR0_RHST_FS                    (2U << R_USB_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+#define R_USB_DVSTCTR0_RHST_HS                    (3U << R_USB_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+
+#define R_USB_DEVADD_USBSPD_LS                    (1U << R_USB_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
+#define R_USB_DEVADD_USBSPD_FS                    (2U << R_USB_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */
+
+#define R_USB_CFIFOSEL_ISEL_WRITE                 (1U << R_USB_CFIFOSEL_ISEL_Pos)   /* FIFO write AKA TX*/
+
+#define R_USB_FIFOSEL_BIGEND                      (1U << R_USB_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
+#define R_USB_FIFOSEL_MBW_8BIT                    (0U << R_USB_CFIFOSEL_MBW_Pos)    /* 8-bit width */
+#define R_USB_FIFOSEL_MBW_16BIT                   (1U << R_USB_CFIFOSEL_MBW_Pos)    /* 16-bit width */
+#define R_USB_FIFOSEL_MBW_32BIT                   (2U << R_USB_CFIFOSEL_MBW_Pos)    /* 32-bit width */
+
+#define R_USB_INTSTS0_CTSQ_CTRL_IDLE              (0U << R_USB_INTSTS0_CTSQ_Pos)    /* Control setup/idle stage */
+#define R_USB_INTSTS0_CTSQ_CTRL_RDATA             (1U << R_USB_INTSTS0_CTSQ_Pos)    /* Control read data stage */
+#define R_USB_INTSTS0_CTSQ_CTRL_RSTATUS           (2U << R_USB_INTSTS0_CTSQ_Pos)    /* Control read status stage */
+#define R_USB_INTSTS0_CTSQ_CTRL_WDATA             (3U << R_USB_INTSTS0_CTSQ_Pos)    /* Control write data stage */
+#define R_USB_INTSTS0_CTSQ_CTRL_WSTATUS           (4U << R_USB_INTSTS0_CTSQ_Pos)    /* Control write status stage */
+#define R_USB_INTSTS0_CTSQ_CTRL_WSTATUS_NODATA    (5U << R_USB_INTSTS0_CTSQ_Pos)    /* Control write status no data stage */
+#define R_USB_INTSTS0_CTSQ_CTRL_ERROR             (6U << R_USB_INTSTS0_CTSQ_Pos)    /* Control error stage */
+
+#define R_USB_INTSTS0_DVSQ_STATE_DEF              (1U << R_USB_INTSTS0_DVSQ_Pos)    /* Default state */
+#define R_USB_INTSTS0_DVSQ_STATE_ADDR             (2U << R_USB_INTSTS0_DVSQ_Pos)    /* Address state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP0            (4U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP1            (5U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP2            (6U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP3            (7U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+
+#define R_USB_PIPECFG_TYPE_BULK                   (1U << R_USB_PIPECFG_TYPE_Pos)
+#define R_USB_PIPECFG_TYPE_INT                    (2U << R_USB_PIPECFG_TYPE_Pos)
+#define R_USB_PIPECFG_TYPE_ISO                    (3U << R_USB_PIPECFG_TYPE_Pos)
+
+typedef struct
+{
+    union
+    {
+        volatile uint16_t E;           /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
+
+        struct __PACKED
+        {
+            uint16_t                : 8;
+            volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
+            volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
+            uint16_t                : 6;
+        } E_b;
+    };
+
+    union
+    {
+        volatile uint16_t N;               /* (@ 0x00000002) Pipe Transaction Counter Register */
+
+        struct __PACKED
+        {
+            volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
+        } N_b;
+    };
+} R_USB_PIPE_TR_t;                         /* Size = 4 (0x4) */
+
+/*--------------------------------------------------------------------*/
+/* Register Bit Utils                                           */
+/*--------------------------------------------------------------------*/
+#define R_USB_PIPE_CTR_PID_NAK            (0U << R_USB_PIPE_CTR_PID_Pos)    /* NAK response */
+#define R_USB_PIPE_CTR_PID_BUF            (1U << R_USB_PIPE_CTR_PID_Pos)    /* BUF response (depends buffer state) */
+#define R_USB_PIPE_CTR_PID_STALL          (2U << R_USB_PIPE_CTR_PID_Pos)    /* STALL response */
+#define R_USB_PIPE_CTR_PID_STALL2         (3U << R_USB_PIPE_CTR_PID_Pos)    /* Also STALL response */
+
+#define R_USB_DVSTCTR0_RHST_LS            (1U << R_USB_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
+#define R_USB_DVSTCTR0_RHST_FS            (2U << R_USB_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+#define R_USB_DVSTCTR0_RHST_HS            (3U << R_USB_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+
+#define R_USB_DEVADD_USBSPD_LS            (1U << R_USB_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
+#define R_USB_DEVADD_USBSPD_FS            (2U << R_USB_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */
+
+#define R_USB_CFIFOSEL_ISEL_WRITE         (1U << R_USB_CFIFOSEL_ISEL_Pos)   /* FIFO write AKA TX*/
+
+#define R_USB_FIFOSEL_BIGEND              (1U << R_USB_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
+#define R_USB_FIFOSEL_MBW_8BIT            (0U << R_USB_CFIFOSEL_MBW_Pos)    /* 8-bit width */
+#define R_USB_FIFOSEL_MBW_16BIT           (1U << R_USB_CFIFOSEL_MBW_Pos)    /* 16-bit width */
+#define R_USB_FIFOSEL_MBW_32BIT           (2U << R_USB_CFIFOSEL_MBW_Pos)    /* 32-bit width */
+
+#define R_USB_INTSTS0_CTSQ_CTRL_RDATA     (1U << R_USB_INTSTS0_CTSQ_Pos)
+
+#define R_USB_INTSTS0_DVSQ_STATE_DEF      (1U << R_USB_INTSTS0_DVSQ_Pos)    /* Default state */
+#define R_USB_INTSTS0_DVSQ_STATE_ADDR     (2U << R_USB_INTSTS0_DVSQ_Pos)    /* Address state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP0    (4U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP1    (5U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP2    (6U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define R_USB_INTSTS0_DVSQ_STATE_SUSP3    (7U << R_USB_INTSTS0_DVSQ_Pos)    /* Suspend state */
+
+#define R_USB_PIPECFG_TYPE_BULK           (1U << R_USB_PIPECFG_TYPE_Pos)
+#define R_USB_PIPECFG_TYPE_INT            (2U << R_USB_PIPECFG_TYPE_Pos)
+#define R_USB_PIPECFG_TYPE_ISO            (3U << R_USB_PIPECFG_TYPE_Pos)
+
+#endif /* R_USB_DEVICE_DEFINE_H */
\ No newline at end of file
diff --git a/port/renesas/device/usb_dc_rensas.c b/port/renesas/device/usb_dc_rensas.c
new file mode 100644
index 00000000..00408d3b
--- /dev/null
+++ b/port/renesas/device/usb_dc_rensas.c
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2026, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "usbd_core.h"
+#include "r_usb_device.h"
+
+static void udc_renesas_ra_event_handler(usbd_callback_arg_t *p_args);
+
+usbd_instance_ctrl_t g_usbd_ctrl[CONFIG_USBDEV_MAX_BUS];
+usbd_cfg_t g_usbd_cfg[CONFIG_USBDEV_MAX_BUS] = {
+    {
+        .module_number = 0,
+        .usb_speed = USBD_SPEED_FS,
+#if defined(VECTOR_NUMBER_USBFS_INT)
+        .irq = VECTOR_NUMBER_USBFS_INT,
+#else
+        .irq = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBFS_RESUME)
+        .irq_r = VECTOR_NUMBER_USBFS_RESUME,
+#else
+        .irq_r = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBFS_FIFO_0)
+        .irq_d0 = VECTOR_NUMBER_USBFS_FIFO_0,
+#else
+        .irq_d0 = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBFS_FIFO_1)
+        .irq_d1 = VECTOR_NUMBER_USBFS_FIFO_1,
+#else
+        .irq_d1 = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME)
+        .hs_irq = VECTOR_NUMBER_USBHS_USB_INT_RESUME,
+#else
+        .hs_irq = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBHS_FIFO_0)
+        .hsirq_d0 = VECTOR_NUMBER_USBHS_FIFO_0,
+#else
+        .hsirq_d0 = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBHS_FIFO_1)
+        .hsirq_d1 = VECTOR_NUMBER_USBHS_FIFO_1,
+#else
+        .hsirq_d1 = FSP_INVALID_VECTOR,
+#endif
+        .ipl = (12),
+        .ipl_r = (12),
+        .ipl_d0 = (12),
+        .ipl_d1 = (12),
+        .hsipl = (12),
+        .hsipl_d0 = (12),
+        .hsipl_d1 = (12),
+        .p_callback = udc_renesas_ra_event_handler,
+        .p_context = NULL,
+    },
+#if CONFIG_USBDEV_MAX_BUS > 1
+    {
+        .module_number = 1,
+        .usb_speed = USBD_SPEED_HS,
+#if defined(VECTOR_NUMBER_USBFS_INT)
+        .irq = VECTOR_NUMBER_USBFS_INT,
+#else
+        .irq = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBFS_RESUME)
+        .irq_r = VECTOR_NUMBER_USBFS_RESUME,
+#else
+        .irq_r = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBFS_FIFO_0)
+        .irq_d0 = VECTOR_NUMBER_USBFS_FIFO_0,
+#else
+        .irq_d0 = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBFS_FIFO_1)
+        .irq_d1 = VECTOR_NUMBER_USBFS_FIFO_1,
+#else
+        .irq_d1 = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME)
+        .hs_irq = VECTOR_NUMBER_USBHS_USB_INT_RESUME,
+#else
+        .hs_irq = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBHS_FIFO_0)
+        .hsirq_d0 = VECTOR_NUMBER_USBHS_FIFO_0,
+#else
+        .hsirq_d0 = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_USBHS_FIFO_1)
+        .hsirq_d1 = VECTOR_NUMBER_USBHS_FIFO_1,
+#else
+        .hsirq_d1 = FSP_INVALID_VECTOR,
+#endif
+        .ipl = (12),
+        .ipl_r = (12),
+        .ipl_d0 = (12),
+        .ipl_d1 = (12),
+        .hsipl = (12),
+        .hsipl_d0 = (12),
+        .hsipl_d1 = (12),
+        .p_callback = udc_renesas_ra_event_handler,
+        .p_context = NULL,
+    },
+#endif
+
+};
+
+uint8_t g_usbd_speed[CONFIG_USBDEV_MAX_BUS];
+uint8_t g_usbd_is_stalled[CONFIG_USBDEV_MAX_BUS][2][16];
+
+int usb_dc_init(uint8_t busid)
+{
+    g_usbd_speed[busid] = USB_SPEED_UNKNOWN;
+    R_USBD_Open(&g_usbd_ctrl[busid], &g_usbd_cfg[busid]);
+    R_USBD_Connect(&g_usbd_ctrl[busid]);
+    return 0;
+}
+
+int usb_dc_deinit(uint8_t busid)
+{
+    R_USBD_Disconnect(&g_usbd_ctrl[busid]);
+    R_USBD_Close(&g_usbd_ctrl[busid]);
+    return 0;
+}
+
+int usbd_set_address(uint8_t busid, const uint8_t addr)
+{
+    return 0;
+}
+
+int usbd_set_remote_wakeup(uint8_t busid)
+{
+    R_USBD_RemoteWakeup(&g_usbd_ctrl[busid]);
+    return 0;
+}
+
+uint8_t usbd_get_port_speed(uint8_t busid)
+{
+    return g_usbd_speed[busid];
+}
+
+int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
+{
+    if ((ep->bEndpointAddress & 0x0f) == 0) {
+        return 0;
+    }
+
+    return R_USBD_EdptOpen(&g_usbd_ctrl[busid], (usbd_desc_endpoint_t *)ep) == FSP_SUCCESS ? 0 : -1;
+}
+
+int usbd_ep_close(uint8_t busid, const uint8_t ep)
+{
+    R_USBD_EdptClose(&g_usbd_ctrl[busid], ep);
+    return 0;
+}
+
+int usbd_ep_set_stall(uint8_t busid, const uint8_t ep)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        g_usbd_is_stalled[busid][0][ep_idx] = 1;
+    } else {
+        g_usbd_is_stalled[busid][1][ep_idx] = 1;
+    }
+    R_USBD_EdptStall(&g_usbd_ctrl[busid], ep);
+    return 0;
+}
+
+int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        g_usbd_is_stalled[busid][0][ep_idx] = 0;
+    } else {
+        g_usbd_is_stalled[busid][1][ep_idx] = 0;
+    }
+    R_USBD_EdptClearStall(&g_usbd_ctrl[busid], ep);
+    return 0;
+}
+
+int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        *stalled = g_usbd_is_stalled[busid][0][ep_idx];
+    } else {
+        *stalled = g_usbd_is_stalled[busid][1][ep_idx];
+    }
+    return 0;
+}
+
+int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data,
+                        uint32_t data_len)
+{
+    R_USBD_XferStart(&g_usbd_ctrl[busid], ep, (uint8_t *)data, data_len);
+    if (data_len == 0 && ep == 0x80) {
+        usbd_event_ep_in_complete_handler(busid, ep, 0);
+        return 0;
+    }
+    return 0;
+}
+
+int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data,
+                       uint32_t data_len)
+{
+    if (data_len == 0) {
+        usbd_event_ep_out_complete_handler(busid, ep, 0);
+        return 0;
+    }
+
+    R_USBD_XferStart(&g_usbd_ctrl[busid], ep, data, data_len);
+    return 0;
+}
+
+void udc_renesas_ra_event_handler(usbd_callback_arg_t *p_args)
+{
+    switch (p_args->event.event_id) {
+        case R_USBD_EVENT_BUS_RESET:
+            g_usbd_speed[p_args->module_number] = p_args->event.bus_reset.speed + 1;
+            usbd_event_reset_handler(p_args->module_number);
+            break;
+        case R_USBD_EVENT_VBUS_RDY:
+            break;
+        case R_USBD_EVENT_VBUS_REMOVED:
+            break;
+        case R_USBD_EVENT_SOF:
+            break;
+        case R_USBD_EVENT_SUSPEND:
+            usbd_event_suspend_handler(p_args->module_number);
+            break;
+        case R_USBD_EVENT_RESUME:
+            usbd_event_resume_handler(p_args->module_number);
+            break;
+        case R_USBD_EVENT_SETUP_RECEIVED:
+            usbd_event_ep0_setup_complete_handler(p_args->module_number, (uint8_t *)&p_args->event.setup_received);
+            break;
+        case R_USBD_EVENT_XFER_COMPLETE:
+            if (p_args->event.xfer_complete.result == USBD_XFER_RESULT_SUCCESS) {
+                if (USB_EP_DIR_IS_IN(p_args->event.xfer_complete.ep_addr)) {
+                    usbd_event_ep_in_complete_handler(p_args->module_number, p_args->event.xfer_complete.ep_addr, p_args->event.xfer_complete.len);
+                } else {
+                    usbd_event_ep_out_complete_handler(p_args->module_number, p_args->event.xfer_complete.ep_addr, p_args->event.xfer_complete.len);
+                }
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+extern void usb_device_isr(void);
+
+void usbfs_interrupt_handler(void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+    R_BSP_IrqStatusClear(irq);
+    usb_device_isr();
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
+
+void usbfs_resume_handler(void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+    R_BSP_IrqStatusClear(irq);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
+
+void usbfs_d0fifo_handler(void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+    R_BSP_IrqStatusClear(irq);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
+
+void usbfs_d1fifo_handler(void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+    R_BSP_IrqStatusClear(irq);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
+
+void usbhs_interrupt_handler(void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+    R_BSP_IrqStatusClear(irq);
+    usb_device_isr();
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
+
+void usbhs_d0fifo_handler(void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+    R_BSP_IrqStatusClear(irq);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
+
+void usbhs_d1fifo_handler(void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+    R_BSP_IrqStatusClear(irq);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
diff --git a/port/renesas/host/.gitkeep b/port/renesas/host/.gitkeep
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/port/renesas/host/.gitkeep
diff --git a/port/renesas/rasc_config.png b/port/renesas/rasc_config.png
new file mode 100644
index 00000000..7d161aef
--- /dev/null
+++ b/port/renesas/rasc_config.png
diff --git a/port/renesas/usb_code.png b/port/renesas/usb_code.png
new file mode 100644
index 00000000..f2294f61
--- /dev/null
+++ b/port/renesas/usb_code.png