diff options
| author | Xiaoming Xi <[email protected]> | 2026-09-09 14:14:11 +0800 |
|---|---|---|
| committer | sakumisu <[email protected]> | 2026-09-09 15:53:40 +0800 |
| commit | 505d329ac8bc6c446994b0210eb80deb63b81a91 (patch) | |
| tree | d8c01fd2fbbc64c6931e040bbf662d4cf02ad4d0 /port | |
| parent | dd1ee3e7e10b0cc1568e5ed4172042b4666f1ea2 (diff) | |
fix(port/musb): Fix MUSB host TX/RX FIFO flush fail
musb_fifo_flush() selected the CSR side for device role, which is opposite to
the host direction. Now IN endpoints (host RX) flush RXCSR, OUT endpoints (host
TX) flush TXCSR, and EP0 writes the FLUSHFIFO bit in the csr0 high byte, so a
timed-out/killed bulk OUT no longer leaves TXPKTRDY and the FIFO uncleaned.
Diffstat (limited to 'port')
| -rw-r--r-- | port/musb/usb_hc_musb.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/port/musb/usb_hc_musb.c b/port/musb/usb_hc_musb.c index 784243e3..ebea2e09 100644 --- a/port/musb/usb_hc_musb.c +++ b/port/musb/usb_hc_musb.c @@ -188,14 +188,14 @@ static void musb_fifo_flush(struct usbh_bus *bus, uint8_t ep) uint8_t ep_idx = ep & 0x7f; if (ep_idx == 0) { if ((HWREGB(USB_TXCSRL_BASE(ep_idx)) & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) - HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_CSRH0_FLUSH; + HWREGB(USB_TXCSRH_BASE(ep_idx)) |= USB_CSRH0_FLUSH; } else { if (ep & 0x80) { - if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) - HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_FLUSH; - } else { if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_RXRDY) HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_RXCSRL1_FLUSH; + } else { + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_FLUSH; } } } |