add nocache ram config when enable dcache

5 files changed, 34 insertions, 29 deletions

diff --git a/port/ch32/usb_dc_usbfs.c b/port/ch32/usb_dc_usbfs.c
index 6cffdbef..1eaa1caa 100644
--- a/port/ch32/usb_dc_usbfs.c
+++ b/port/ch32/usb_dc_usbfs.c
@@ -4,8 +4,8 @@
 #ifdef CONFIG_USB_HS
 #error "usb fs do not support hs"
 #endif
-#ifndef CONFIG_USB_ALIGN32
-#error "usb hs dma must be align4"
+#ifndef CONFIG_USBDEV_ALIGN_CHECK_DISABLE
+#error "ch32 ip must disable align check"
 #endif
 
 #ifndef USBD_IRQHandler
diff --git a/port/ch32/usb_dc_usbhs.c b/port/ch32/usb_dc_usbhs.c
index 2fc8f243..30c31498 100644
--- a/port/ch32/usb_dc_usbhs.c
+++ b/port/ch32/usb_dc_usbhs.c
@@ -1,8 +1,8 @@
 #include "usbd_core.h"
 #include "usb_ch32_usbhs_reg.h"
 
-#ifndef CONFIG_USB_ALIGN32
-#error "usb hs dma must be align4"
+#ifndef CONFIG_USBDEV_ALIGN_CHECK_DISABLE
+#error "ch32 ip must disable align check"
 #endif
 
 #ifndef USBD_IRQHandler
diff --git a/port/dwc2/usb_dc_dwc2.c b/port/dwc2/usb_dc_dwc2.c
index 9f3ffd1b..d6b5e539 100644
--- a/port/dwc2/usb_dc_dwc2.c
+++ b/port/dwc2/usb_dc_dwc2.c
@@ -75,13 +75,14 @@
 #if defined(STM32F7) || defined(STM32H7)
 #ifndef CONFIG_USB_DCACHE_ENABLE
 #warning "if you enable dcache,please enable this macro"
-#endif
 #else
-#ifndef CONFIG_USB_ALIGN32
-#error "dwc2 hs with dma, must enable align32"
+#if CONFIG_USB_ALIGN_SIZE != 32
+#error "dwc2 hs with dma and cache, must enable align32"
+#endif
 #endif
 #endif
 #endif
+
 /*FIFO sizes in bytes (total available memory for FIFOs is 4KB )*/
 #ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE
 #define CONFIG_USB_DWC2_RX_FIFO_SIZE (1024)
diff --git a/port/dwc2/usb_hc_dwc2.c b/port/dwc2/usb_hc_dwc2.c
index 5520b78a..ceb30a46 100644
--- a/port/dwc2/usb_hc_dwc2.c
+++ b/port/dwc2/usb_hc_dwc2.c
@@ -5,6 +5,16 @@
 #error "dwc2 host must use high workq"
 #endif
 
+#if defined(STM32F7) || defined(STM32H7)
+#ifndef CONFIG_USB_DCACHE_ENABLE
+#warning "if you enable dcache,please enable this macro"
+#else
+#if CONFIG_USB_ALIGN_SIZE != 32
+#error "dwc2 hs with dma and cache, must enable align32"
+#endif
+#endif
+#endif
+
 #ifndef USBH_IRQHandler
 #define USBH_IRQHandler OTG_HS_IRQHandler
 #endif
@@ -59,14 +69,6 @@ struct dwc2_hcd {
     struct dwc2_pipe chan[CONFIG_USB_DWC2_PIPE_NUM];
 } g_dwc2_hcd;
 
-#ifdef CONFIG_USB_DCACHE_ENABLE
-void usb_dwc2_dcache_clean(uintptr_t addr, uint32_t len);
-void usb_dwc2_dcache_invalidate(uintptr_t addr, uint32_t len);
-#else
-#define usb_dwc2_dcache_clean(addr, len)
-#define usb_dwc2_dcache_invalidate(addr, len)
-#endif
-
 static inline int dwc2_reset(void)
 {
     uint32_t count = 0U;
@@ -821,7 +823,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
     chan->waiter = true;
     chan->result = -EBUSY;
     chan->num_packets = dwc2_calculate_packet_num(8, chan->ep_addr, chan->ep_mps, &chan->xferlen);
-    usb_dwc2_dcache_clean((uintptr_t)setup, 8);
+    usb_dcache_clean((uintptr_t)setup, 8);
     dwc2_pipe_init(chidx, chan->dev_addr, 0x00, 0x00, chan->ep_mps, chan->speed);
     dwc2_pipe_transfer(chidx, 0x00, (uint32_t *)setup, chan->xferlen, chan->num_packets, HC_PID_SETUP);
     ret = dwc2_pipe_wait(chan, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT);
@@ -840,7 +842,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
             if (ret < 0) {
                 goto error_out;
             }
-            usb_dwc2_dcache_invalidate((uintptr_t)buffer, setup->wLength);
+            usb_dcache_invalidate((uintptr_t)buffer, setup->wLength);
             chan->waiter = true;
             chan->result = -EBUSY;
             chan->num_packets = dwc2_calculate_packet_num(0, 0x00, chan->ep_mps, &chan->xferlen);
@@ -854,7 +856,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
             chan->waiter = true;
             chan->result = -EBUSY;
             chan->num_packets = dwc2_calculate_packet_num(setup->wLength, 0x00, chan->ep_mps, &chan->xferlen);
-            usb_dwc2_dcache_clean((uintptr_t)buffer, setup->wLength);
+            usb_dcache_clean((uintptr_t)buffer, setup->wLength);
             dwc2_pipe_init(chidx, chan->dev_addr, 0x00, 0x00, chan->ep_mps, chan->speed);
             dwc2_pipe_transfer(chidx, 0x00, (uint32_t *)buffer, chan->xferlen, chan->num_packets, HC_PID_DATA1);
             ret = dwc2_pipe_wait(chan, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT);
@@ -921,7 +923,7 @@ int usbh_ep_bulk_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
     chan->num_packets = dwc2_calculate_packet_num(buflen, chan->ep_addr, chan->ep_mps, &chan->xferlen);
 #ifdef CONFIG_USB_DCACHE_ENABLE
     if ((chan->ep_addr & 0x80) == 0x00) {
-        usb_dwc2_dcache_clean((uintptr_t)buffer, buflen);
+        usb_dcache_clean((uintptr_t)buffer, buflen);
     }
 #endif
     dwc2_pipe_transfer(chidx, chan->ep_addr, (uint32_t *)buffer, chan->xferlen, chan->num_packets, chan->data_pid);
@@ -931,7 +933,7 @@ int usbh_ep_bulk_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
     }
 #ifdef CONFIG_USB_DCACHE_ENABLE
     if ((chan->ep_addr & 0x80) == 0x80) {
-        usb_dwc2_dcache_invalidate((uintptr_t)buffer, buflen);
+        usb_dcache_invalidate((uintptr_t)buffer, buflen);
     }
 #endif
     usb_osal_mutex_give(chan->exclsem);
@@ -974,7 +976,7 @@ int usbh_ep_intr_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
     chan->num_packets = dwc2_calculate_packet_num(buflen, chan->ep_addr, chan->ep_mps, &chan->xferlen);
 #ifdef CONFIG_USB_DCACHE_ENABLE
     if ((chan->ep_addr & 0x80) == 0x00) {
-        usb_dwc2_dcache_clean((uintptr_t)buffer, buflen);
+        usb_dcache_clean((uintptr_t)buffer, buflen);
     }
 #endif
     while (1) {
@@ -996,7 +998,7 @@ int usbh_ep_intr_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
     }
 #ifdef CONFIG_USB_DCACHE_ENABLE
     if ((chan->ep_addr & 0x80) == 0x80) {
-        usb_dwc2_dcache_invalidate((uintptr_t)buffer, buflen);
+        usb_dcache_invalidate((uintptr_t)buffer, buflen);
     }
 #endif
     usb_osal_mutex_give(chan->exclsem);
@@ -1038,7 +1040,7 @@ int usbh_ep_bulk_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
     chan->num_packets = dwc2_calculate_packet_num(buflen, chan->ep_addr, chan->ep_mps, &chan->xferlen);
 #ifdef CONFIG_USB_DCACHE_ENABLE
     if ((chan->ep_addr & 0x80) == 0x00) {
-        usb_dwc2_dcache_clean((uintptr_t)buffer, buflen);
+        usb_dcache_clean((uintptr_t)buffer, buflen);
     }
 #endif
     dwc2_pipe_transfer(chidx, chan->ep_addr, (uint32_t *)buffer, chan->xferlen, chan->num_packets, chan->data_pid);
diff --git a/port/ehci/usb_ehci.c b/port/ehci/usb_ehci.c
index 4d349d4d..85c3f620 100644
--- a/port/ehci/usb_ehci.c
+++ b/port/ehci/usb_ehci.c
@@ -87,10 +87,12 @@ struct usb_ehci_qh_s {
 
     struct usb_ehci_epinfo_s *epinfo; /* Endpoint used for the transfer */
     uint32_t fqp;                     /* First qTD in the list (physical address) */
-#if (CONFIG_DCACHE_LINE_SIZE == 64)
+#if (CONFIG_USB_ALIGN_SIZE == 64)
     uint8_t pad[4]; /* Padding to assure 64-byte alignment */
-#else
+#elif (CONFIG_USB_ALIGN_SIZE == 32)
     uint8_t pad[8]; /* Padding to assure 32-byte alignment */
+#else
+#error "ehci align size must be 32 or 64"
 #endif
 };
 
@@ -149,10 +151,10 @@ struct usb_ehci_epinfo_s {
 /* This structure retains the overall state of the USB host controller */
 
 struct ehci_hcd {
-    struct usb_ehci_list_s *qhfree;                                                      /* List of free Queue Head (QH) structures */
-    struct usb_ehci_list_s *qtdfree;                                                     /* List of free Queue Element Transfer Descriptor (qTD) */
-    __attribute__((aligned(32))) struct usb_ehci_qh_s qhpool[CONFIG_USB_EHCI_QH_NUM];    /* Queue Head (QH) pool */
-    __attribute__((aligned(32))) struct usb_ehci_qtd_s qtdpool[CONFIG_USB_EHCI_QTD_NUM]; /* Queue Element Transfer Descriptor (qTD) pool */
+    struct usb_ehci_list_s *qhfree;                                        /* List of free Queue Head (QH) structures */
+    struct usb_ehci_list_s *qtdfree;                                       /* List of free Queue Element Transfer Descriptor (qTD) */
+    USB_MEM_ALIGNX struct usb_ehci_qh_s qhpool[CONFIG_USB_EHCI_QH_NUM];    /* Queue Head (QH) pool */
+    USB_MEM_ALIGNX struct usb_ehci_qtd_s qtdpool[CONFIG_USB_EHCI_QTD_NUM]; /* Queue Element Transfer Descriptor (qTD) pool */
     struct usb_ehci_epinfo_s chan[CONFIG_USBHOST_PIPE_NUM];
 };