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authorChao-ying Fu <[email protected]>2025-07-23 13:40:10 -0700
committerAnup Patel <[email protected]>2025-08-28 11:00:16 +0530
commit1ffbd063c4da252f59cc570e537a3c8821ed6967 (patch)
treeda21b8acd1b7aff627579f8eedbb3dce81763732
parent6a1f53bc2d91310adc44c158596dd1c3efa18080 (diff)
generic: mips: support harts to boot from mips_warm_boot
We program reset base for harts (other than hart 0) to boot at mips_warm_boot that jumps to _start_warm. This helps to skip some code sequence to speed up. Signed-off-by: Chao-ying Fu <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
-rw-r--r--platform/generic/mips/mips_warm_boot.S12
-rw-r--r--platform/generic/mips/objects.mk2
-rw-r--r--platform/generic/mips/p8700.c5
3 files changed, 18 insertions, 1 deletions
diff --git a/platform/generic/mips/mips_warm_boot.S b/platform/generic/mips/mips_warm_boot.S
new file mode 100644
index 00000000..c4a74c59
--- /dev/null
+++ b/platform/generic/mips/mips_warm_boot.S
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2025 MIPS
+ *
+ */
+ .text
+ .align 12
+ .globl mips_warm_boot
+mips_warm_boot:
+ j _start_warm
+ .align 2
diff --git a/platform/generic/mips/objects.mk b/platform/generic/mips/objects.mk
index bbbc15a0..a08c4c63 100644
--- a/platform/generic/mips/objects.mk
+++ b/platform/generic/mips/objects.mk
@@ -4,5 +4,5 @@
ifeq ($(PLATFORM_RISCV_XLEN), 64)
carray-platform_override_modules-$(CONFIG_PLATFORM_MIPS_P8700) += mips_p8700
-platform-objs-$(CONFIG_PLATFORM_MIPS_P8700) += mips/p8700.o
+platform-objs-$(CONFIG_PLATFORM_MIPS_P8700) += mips/p8700.o mips/mips_warm_boot.o
endif
diff --git a/platform/generic/mips/p8700.c b/platform/generic/mips/p8700.c
index 888a45c6..d3e015ba 100644
--- a/platform/generic/mips/p8700.c
+++ b/platform/generic/mips/p8700.c
@@ -16,6 +16,8 @@
#include <mips/p8700.h>
#include <mips/mips-cm.h>
+extern void mips_warm_boot(void);
+
static unsigned long mips_csr_read_num(int csr_num)
{
#define switchcase_csr_read(__csr_num, __val) \
@@ -150,6 +152,9 @@ static int mips_hart_start(u32 hartid, ulong saddr)
if (hartid == 0)
return SBI_ENOTSUPP;
+ /* Change reset base to mips_warm_boot */
+ write_gcr_co_reset_base(hartid, (unsigned long)mips_warm_boot, local_p);
+
if (cpu_hart(hartid) == 0) {
/* Ensure its coherency is disabled */
write_gcr_co_coherence(hartid, 0, local_p);