diff options
| author | Anup Patel <[email protected]> | 2019-12-12 07:22:03 +0530 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2019-12-16 14:48:19 +0530 |
| commit | 4370f18f3467fee4a80fd463f1c0247d02f912d6 (patch) | |
| tree | 0f166f806818afe8d60db7fe1711693447f78dc1 | |
| parent | 6590a7dab9d7182b659a13338043889350d9c6bb (diff) | |
include: Extend struct sbi_trap_info for mtval2 and mtinst
We have two new trap CSRs namely mtval2 and mtinst when
RISC-V hypervisor extension is available hence we extend
struct sbi_trap_info accordingly.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
| -rw-r--r-- | include/sbi/sbi_trap.h | 4 | ||||
| -rw-r--r-- | lib/sbi/sbi_unpriv.c | 6 |
2 files changed, 10 insertions, 0 deletions
diff --git a/include/sbi/sbi_trap.h b/include/sbi/sbi_trap.h index 4baa3a57..9a35a6e5 100644 --- a/include/sbi/sbi_trap.h +++ b/include/sbi/sbi_trap.h @@ -178,6 +178,10 @@ struct sbi_trap_info { unsigned long cause; /** tval Trap value */ unsigned long tval; + /** tval2 Trap value 2 */ + unsigned long tval2; + /** tinst Trap instruction */ + unsigned long tinst; }; struct sbi_scratch; diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c index aa74c43d..9d384bb3 100644 --- a/lib/sbi/sbi_unpriv.c +++ b/lib/sbi/sbi_unpriv.c @@ -24,6 +24,8 @@ trap->epc = 0; \ trap->cause = 0; \ trap->tval = 0; \ + trap->tval2 = 0; \ + trap->tinst = 0; \ sbi_hart_set_trap_info(scratch, trap); \ asm volatile( \ "csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \ @@ -47,6 +49,8 @@ trap->epc = 0; \ trap->cause = 0; \ trap->tval = 0; \ + trap->tval2 = 0; \ + trap->tinst = 0; \ sbi_hart_set_trap_info(scratch, trap); \ asm volatile( \ "csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \ @@ -117,6 +121,8 @@ ulong sbi_get_insn(ulong mepc, struct sbi_scratch *scratch, trap->epc = 0; trap->cause = 0; trap->tval = 0; + trap->tval2 = 0; + trap->tinst = 0; sbi_hart_set_trap_info(scratch, trap); #ifndef __riscv_compressed |