diff options
| author | Anup Patel <[email protected]> | 2024-12-09 20:06:18 +0530 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2024-12-15 11:30:48 +0530 |
| commit | 5545602f778e3065674df3a630c67b820f5dc1da (patch) | |
| tree | 78d8906cffac640389bce92fc9f5532354929cce | |
| parent | 74c6ea014db8fc7d56254ba9dd371b7454bd7220 (diff) | |
Makefile: Don't enable V-extension using -march option
Enabling V-extension using -march option causes OpenSBI boot-time
hang with LLVM compiler.
As a work-around, don't enable V-extension using -march option and
instead use a custom OpenSBI specific define inform availability of
V-extension to lib/sbi/sbi_trap_v_ldst.c.
Fixes: c2acc5e5b0d8 ("lib: sbi_misaligned_ldst: Add handling of vector load/store")
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | lib/sbi/sbi_trap_v_ldst.c | 5 |
2 files changed, 7 insertions, 6 deletions
@@ -190,7 +190,7 @@ CC_SUPPORT_STRICT_ALIGN := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep -e "zicsr" -e "zifencei" > /dev/null && echo n || echo y) # Check whether the assembler and the compiler support the Vector extension -CC_SUPPORT_VECT := $(shell echo | $(CC) -dM -E -march=rv$(OPENSBI_CC_XLEN)gv - | grep -q riscv.*vector && echo y || echo n) +CC_SUPPORT_VECTOR := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)gv -dM -E -x c /dev/null 2>&1 | grep -q riscv.*vector && echo y || echo n) ifneq ($(OPENSBI_LD_PIE),y) $(error Your linker does not support creating PIEs, opensbi requires this.) @@ -298,9 +298,6 @@ endif ifndef PLATFORM_RISCV_ISA ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1) PLATFORM_RISCV_ISA := rv$(PLATFORM_RISCV_XLEN)imafdc - ifeq ($(CC_SUPPORT_VECT), y) - PLATFORM_RISCV_ISA := $(PLATFORM_RISCV_ISA)v - endif ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y) PLATFORM_RISCV_ISA := $(PLATFORM_RISCV_ISA)_zicsr_zifencei endif @@ -363,6 +360,9 @@ GENFLAGS += $(firmware-genflags-y) CFLAGS = -g -Wall -Werror -ffreestanding -nostdlib -fno-stack-protector -fno-strict-aliasing -ffunction-sections -fdata-sections CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls # Optionally supported flags +ifeq ($(CC_SUPPORT_VECTOR),y) +CFLAGS += -DOPENSBI_CC_SUPPORT_VECTOR +endif ifeq ($(CC_SUPPORT_SAVE_RESTORE),y) CFLAGS += -mno-save-restore endif diff --git a/lib/sbi/sbi_trap_v_ldst.c b/lib/sbi/sbi_trap_v_ldst.c index 9929215c..f4d469dc 100644 --- a/lib/sbi/sbi_trap_v_ldst.c +++ b/lib/sbi/sbi_trap_v_ldst.c @@ -17,7 +17,8 @@ #include <sbi/sbi_unpriv.h> #include <sbi/sbi_trap.h> -#ifdef __riscv_vector +#ifdef OPENSBI_CC_SUPPORT_VECTOR + #define VLEN_MAX 65536 static inline void set_vreg(ulong vlenb, ulong which, @@ -340,4 +341,4 @@ int sbi_misaligned_v_st_emulator(int wlen, union sbi_ldst_data in_val, { return 0; } -#endif /* __riscv_vector */ +#endif /* OPENSBI_CC_SUPPORT_VECTOR */ |