diff options
| author | Anup Patel <[email protected]> | 2018-12-22 12:40:54 +0530 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2018-12-22 20:49:52 +0530 |
| commit | 58ca525a7d35b2d4cd7045fd343fb6d85567f01d (patch) | |
| tree | 01d947176b3f14ec1bb5c7487d1b725682bd68bd | |
| parent | 1cf7ec9e3bbf287fc9d601d2346b9e73fda40a84 (diff) | |
firmware: Don't depend on PLAT_HART_COUNT and PLAT_HART_STACK_SIZE
The hart_count and hart_stack_size information is already available
in "struct sbi_platform" so we use that instead of depending on
PLAT_HART_COUNT and PLAT_HART_STACK_SIZE.
Signed-off-by: Anup Patel <[email protected]>
| -rw-r--r-- | firmware/fw_common.S | 10 | ||||
| -rw-r--r-- | include/sbi/riscv_asm.h | 5 |
2 files changed, 11 insertions, 4 deletions
diff --git a/firmware/fw_common.S b/firmware/fw_common.S index 4c11e852..d426f15f 100644 --- a/firmware/fw_common.S +++ b/firmware/fw_common.S @@ -132,8 +132,9 @@ _start_warm: * s8 -> HART Stack Size */ csrr s6, mhartid - li s7, PLAT_HART_COUNT - li s8, PLAT_HART_STACK_SIZE + la a4, platform + lwu s7, RISCV_PLATFORM_HART_COUNT_OFFSET(a4) + lwu s8, RISCV_PLATFORM_HART_STACK_SIZE_OFFSET(a4) /* HART ID should be within expected limit */ csrr s6, mhartid @@ -202,8 +203,9 @@ _hartid_to_scratch: * s1 -> HART Stack End * s2 -> Temporary */ - li s0, PLAT_HART_STACK_SIZE - li s2, PLAT_HART_COUNT + la s2, platform + lwu s0, RISCV_PLATFORM_HART_STACK_SIZE_OFFSET(s2) + lwu s2, RISCV_PLATFORM_HART_COUNT_OFFSET(s2) mul s2, s2, s0 la s1, _fw_end add s1, s1, s2 diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h index 516bf6f9..045310b5 100644 --- a/include/sbi/riscv_asm.h +++ b/include/sbi/riscv_asm.h @@ -81,6 +81,11 @@ #define RISCV_SCRATCH_IPI_TYPE_OFFSET (9 * __SIZEOF_POINTER__) #define RISCV_SCRATCH_SIZE 256 +#define RISCV_PLATFORM_NAME_OFFSET (0x0) +#define RISCV_PLATFORM_FEATURES_OFFSET (0x40) +#define RISCV_PLATFORM_HART_COUNT_OFFSET (0x48) +#define RISCV_PLATFORM_HART_STACK_SIZE_OFFSET (0x4c) + #define RISCV_TRAP_REGS_zero 0 #define RISCV_TRAP_REGS_ra 1 #define RISCV_TRAP_REGS_sp 2 |