diff options
| author | Anup Patel <[email protected]> | 2020-12-19 17:39:57 +0530 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2020-12-24 16:35:28 +0530 |
| commit | 7dcb1e1753e9c5daec0580779ea8c31778bff152 (patch) | |
| tree | 656e705d4b88996733f03d0bd8067a85ee67ec87 | |
| parent | a029bd90c63307e9ef2d7ddbaa2eb2c799fca98a (diff) | |
lib: sbi: Fix sign-extension in sbi_misaligned_load_handler()
The misaligned load emulation does not sign-extend values correctly
due to missing sign typecast in value passed to the SET_RD() macro.
A very easy way to reproduce this issue is to load 16-bit value
0xff1e from a byte aligned address using LH instruction on hardware
lacking misaligned load/store.
This patch fixes sbi_misaligned_load_handler() for above issue.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 964a372f..5057cb5e 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -128,7 +128,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, } if (!fp) - SET_RD(insn, regs, val.data_ulong << shift >> shift); + SET_RD(insn, regs, ((long)(val.data_ulong << shift)) >> shift); #ifdef __riscv_flen else if (len == 8) SET_F64_RD(insn, regs, val.data_u64); |