diff options
| author | Nick Hu <[email protected]> | 2023-01-17 16:14:28 +0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2023-02-08 10:39:21 +0530 |
| commit | 84d15f4f529c92d3f32fbc570c02f7d40e9e70cb (patch) | |
| tree | 64289a8185500e0b15f662baefefa8b4b216923f | |
| parent | 8050081f68b2b66f8937b15a6753ec6408c2fdee (diff) | |
lib: sbi_hsm: Use csr_set to restore the MIP
If we use the csr_write to restore the MIP, we may clear the SEIP.
In generic behavior of QEMU, if the pending bits of PLIC are set and we
clear the SEIP, the QEMU may not set it back immediately. It may cause
the interrupts won't be handled anymore until the new interrupts arrived
and QEMU set the bits back.
Signed-off-by: Nick Hu <[email protected]>
Signed-off-by: Jim Shu <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
| -rw-r--r-- | lib/sbi/sbi_hsm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c index d4cce4ac..8499bb1d 100644 --- a/lib/sbi/sbi_hsm.c +++ b/lib/sbi/sbi_hsm.c @@ -357,7 +357,7 @@ static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch) hart_data_offset); csr_write(CSR_MIE, hdata->saved_mie); - csr_write(CSR_MIP, (hdata->saved_mip & (MIP_SSIP | MIP_STIP))); + csr_set(CSR_MIP, (hdata->saved_mip & (MIP_SSIP | MIP_STIP))); } void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch) |