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authorVladimir Kondratiev <[email protected]>2026-02-23 16:55:02 +0200
committerAnup Patel <[email protected]>2026-02-25 18:49:03 +0530
commit8d1c21b38752301fc6c727eece45c15c663649b0 (patch)
treeb5f198feb6075f421c27ed883281c50725b61f7d
parentf07be546e5ec992fe7c766491a5403c8bc864ceb (diff)
platform: generic: eyeq7h: enable ECC on L1 cache
Signed-off-by: Vladimir Kondratiev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
-rw-r--r--platform/generic/mips/eyeq7h.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c
index f09ec5f0..242cbb3c 100644
--- a/platform/generic/mips/eyeq7h.c
+++ b/platform/generic/mips/eyeq7h.c
@@ -436,6 +436,8 @@ static int eyeq7h_nascent_init(void)
/* Per hart set up */
/* Enable AMO and RDTIME illegal instruction exceptions. */
csr_set(CSR_MIPSCONFIG6, (1<<2)|(1<<1));
+ /* enable ECC for L1 I/D and FTLB */
+ csr_set(CSR_MIPSERRCTL, MIPSERRCTL_PE);
return 0;
}