diff options
| author | Atish Patra <[email protected]> | 2019-11-24 23:33:48 -0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2019-12-23 09:12:16 +0530 |
| commit | 94072025325b639d603f428366b53b470e625f64 (patch) | |
| tree | 69fde845727dda8f86c32eb34b5450009616ce0d | |
| parent | 9777aeef41a613b3c27056a695d4d6007760b3a8 (diff) | |
lib: Add hfence instruction encoding
Currently, the toolchains do not have support for hfence instruction.
Hence, the instruction are hardcode until we have toolchain support.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
| -rw-r--r-- | include/sbi/sbi_hfence.h | 36 | ||||
| -rw-r--r-- | lib/sbi/objects.mk | 1 | ||||
| -rw-r--r-- | lib/sbi/sbi_hfence.S | 75 |
3 files changed, 112 insertions, 0 deletions
diff --git a/include/sbi/sbi_hfence.h b/include/sbi/sbi_hfence.h new file mode 100644 index 00000000..824a8d60 --- /dev/null +++ b/include/sbi/sbi_hfence.h @@ -0,0 +1,36 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra <[email protected]> + * Anup Patel <[email protected]> + */ + +#ifndef __SBI_FENCE_H__ +#define __SBI_FENCE_H__ +/** Invalidate Stage2 TLBs for given VMID and guest physical address */ +void __sbi_hfence_gvma_vmid_gpa(unsigned long vmid, unsigned long gpa); + +/** Invalidate Stage2 TLBs for given VMID */ +void __sbi_hfence_gvma_vmid(unsigned long vmid); + +/** Invalidate Stage2 TLBs for given guest physical address */ +void __sbi_hfence_gvma_gpa(unsigned long gpa); + +/** Invalidate all possible Stage2 TLBs */ +void __sbi_hfence_gvma_all(void); + +/** Invalidate unified TLB entries for given asid and guest virtual address */ +void __sbi_hfence_vvma_asid_va(unsigned long asid, unsigned long va); + +/** Invalidate unified TLB entries for given ASID for a guest*/ +void __sbi_hfence_vvma_asid(unsigned long asid); + +/** Invalidate unified TLB entries for a given guest virtual address */ +void __sbi_hfence_vvma_va(unsigned long va); + +/** Invalidate all possible Stage2 TLBs */ +void __sbi_hfence_vvma_all(void); +#endif diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk index 0e247fe0..b84453e4 100644 --- a/lib/sbi/objects.mk +++ b/lib/sbi/objects.mk @@ -16,6 +16,7 @@ libsbi-objs-y += sbi_console.o libsbi-objs-y += sbi_ecall.o libsbi-objs-y += sbi_emulate_csr.o libsbi-objs-y += sbi_fifo.o +libsbi-objs-y += sbi_hfence.o libsbi-objs-y += sbi_hart.o libsbi-objs-y += sbi_illegal_insn.o libsbi-objs-y += sbi_init.o diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S new file mode 100644 index 00000000..30a6e9fa --- /dev/null +++ b/lib/sbi/sbi_hfence.S @@ -0,0 +1,75 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel <[email protected]> + * Atish Patra <[email protected]> + */ + + /* + * Instruction encoding of hfence.gvma is: + * 0110001 rs2(5) rs1(5) 000 00000 1110011 + */ + + .align 3 + .global __sbi_hfence_gvma_vmid_gpa +__sbi_hfence_gvma_vmid_gpa: + /* hfence.gvma a1, a0 */ + .word 0x62a60073 + ret + + .align 3 + .global __sbi_hfence_gvma_vmid +__sbi_hfence_gvma_vmid: + /* hfence.gvma zero, a0 */ + .word 0x62a00073 + ret + + .align 3 + .global __sbi_hfence_gvma_gpa +__sbi_hfence_gvma_gpa: + /* hfence.gvma a0 */ + .word 0x62050073 + ret + + .align 3 + .global __sbi_hfence_gvma_all +__sbi_hfence_gvma_all: + /* hfence.gvma */ + .word 0x62000073 + ret + + /* + * Instruction encoding of hfence.bvma is: + * 0010001 rs2(5) rs1(5) 000 00000 1110011 + */ + + .align 3 + .global __sbi_hfence_vvma_asid_va +__sbi_hfence_vvma_asid_va: + /* hfence.bvma a1, a0 */ + .word 0x22a60073 + ret + + .align 3 + .global __sbi_hfence_vvma_asid +__sbi_hfence_vvma_asid: + /* hfence.bvma zero, a0 */ + .word 0x22a00073 + ret + + .align 3 + .global __sbi_hfence_vvma_va +__sbi_hfence_vvma_va: + /* hfence.bvma a0 */ + .word 0x22050073 + ret + + .align 3 + .global __sbi_hfence_vvma_all +__sbi_hfence_vvma_all: + /* hfence.bvma */ + .word 0x22000073 + ret |
