diff options
| author | Xiang W <[email protected]> | 2022-11-19 16:55:07 +0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2022-12-04 20:38:46 +0530 |
| commit | 9a740f5c4655053f4d8c7df65f51ad58cfb1bb2e (patch) | |
| tree | 019e12f6ee180284441d57b57106b0dbeef08ec2 | |
| parent | 1b0d71bb9ff9180c4ae0026de5f4a92a88f1884e (diff) | |
platform: generic/allwinner: Remove ghostly type cast
Corrected the same parameter of writel_relaxed in sun20i_d1_riscv_cfg_init
to be u32 for a while and u64 for a while.
Signed-off-by: Xiang W <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
| -rw-r--r-- | platform/generic/allwinner/sun20i-d1.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c index 707313b2..18d330d4 100644 --- a/platform/generic/allwinner/sun20i-d1.c +++ b/platform/generic/allwinner/sun20i-d1.c @@ -146,14 +146,14 @@ static void sun20i_d1_riscv_cfg_restore(void) static void sun20i_d1_riscv_cfg_init(void) { - unsigned long entry = sbi_hartid_to_scratch(0)->warmboot_addr; + u64 entry = sbi_hartid_to_scratch(0)->warmboot_addr; /* Enable MMIO access. */ writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG); /* Program the reset entry address. */ - writel_relaxed((u32)entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG); - writel_relaxed((u64)entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG); + writel_relaxed(entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG); + writel_relaxed(entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG); } static int sun20i_d1_hart_suspend(u32 suspend_type) |