diff options
| author | Amanieu d'Antras <[email protected]> | 2023-10-01 10:12:02 +0100 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2023-10-09 13:53:20 +0530 |
| commit | ec0559eb315bd11a5ef8865a8a8fa91ab6888250 (patch) | |
| tree | b154ae11eeb53a4016cae5f7560fd7f02d88d983 | |
| parent | 3632f2b5c43e2a01bbfdcf4864d358845dcf281e (diff) | |
lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP
Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
register, so checking that the rs2 field is non-zero is unnecessary.
Additionally, the previous check was incorrect since it was checking
the immediate field of the instruction instead of the rs2 field.
Signed-off-by: Amanieu d'Antras <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
| -rw-r--r-- | lib/sbi/sbi_misaligned_ldst.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 4b91e072..aa512de3 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -211,16 +211,14 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) { len = 8; val.data_ulong = GET_RS2S(insn, regs); - } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP && - ((insn >> SH_RD) & 0x1f)) { + } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) { len = 8; val.data_ulong = GET_RS2C(insn, regs); #endif } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) { len = 4; val.data_ulong = GET_RS2S(insn, regs); - } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP && - ((insn >> SH_RD) & 0x1f)) { + } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) { len = 4; val.data_ulong = GET_RS2C(insn, regs); #ifdef __riscv_flen |