diff options
| author | Atish Patra <[email protected]> | 2020-04-03 11:13:08 -0700 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2020-04-06 08:58:56 +0530 |
| commit | f281de885ec9417a6d3ae702d0ed5acab6396bee (patch) | |
| tree | c67743b7504f94e18ce5c4efb3a84a9383a7dfa0 | |
| parent | e5a7f556ce22984128bed0a336551a968c818450 (diff) | |
lib: irqchip/plic: Fix maximum priority threshold value
As per the PLIC specification, maximum priority threshold value is 0x7.
Even though, writing a higher value doesn't cause any error in qemu
hifive unleashed, there may be some implementation which checks the upper
and may result in an illegal access.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
| -rw-r--r-- | lib/utils/irqchip/plic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index 40c41706..7c40d287 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -66,11 +66,11 @@ int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id) /* By default, disable M-mode threshold */ if (m_cntx_id > -1) - plic_set_thresh(m_cntx_id, 0xffffffff); + plic_set_thresh(m_cntx_id, 0x7); /* By default, disable S-mode threshold */ if (s_cntx_id > -1) - plic_set_thresh(s_cntx_id, 0xffffffff); + plic_set_thresh(s_cntx_id, 0x7); return 0; } |