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| author | Atish Patra <[email protected]> | 2019-01-21 18:17:45 -0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2019-01-22 10:03:49 +0530 |
| commit | 023aa6bb043420cd215379a0b31b8aceef38807b (patch) | |
| tree | d01330ff6db909b3fa70ba35def32d99b9903a2e /docs | |
| parent | bc545539d2f2842c12c8b16d898a21113ce70417 (diff) | |
lib: Do not access mi/edeleg register if S mode is not present.
As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.
We shouldn't access these CSRs if non S-mode harts.
Signed-off-by: Atish Patra <[email protected]>
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions