diff options
| author | Nikita Shubin <[email protected]> | 2022-09-02 10:41:03 +0300 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2022-09-13 16:42:03 +0530 |
| commit | d32b0a92dbba0f96d5e6c930e24e8e60f3baf7b4 (patch) | |
| tree | 2666fb4e4de4a18908acaa18e948093a9cc42b7b /docs | |
| parent | 5019fd124b4c46e1581129c5154fc2cdd3b777ed (diff) | |
docs: pmu: fix Unmatched example typo
bitmap for MHPMCOUNTERx should be 0x18 and not 0x0c, we check
against SBI_PMU_FIXED_CTR_MASK which assumes than first 3 bits are
dedicated to mcycle, mtime and minstret, u74 has 2 hardware counters.
Reported-by: Zhang Xin <[email protected]>
Signed-off-by: Nikita Shubin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/pmu_support.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/pmu_support.md b/docs/pmu_support.md index 8751bb54..ca6ca250 100644 --- a/docs/pmu_support.md +++ b/docs/pmu_support.md @@ -93,8 +93,8 @@ pmu { */ pmu { compatible = "riscv,pmu"; - riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0xc>, - <0x0 0x1 0xffffffff 0xfff800ff 0xc>, - <0x0 0x2 0xffffffff 0xffffe0ff 0xc>; + riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>, + <0x0 0x1 0xffffffff 0xfff800ff 0x18>, + <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; }; ``` |