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| author | Vladimir Kondratiev <[email protected]> | 2025-12-28 09:33:21 +0200 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2025-12-28 20:44:03 +0530 |
| commit | f6fa62bd169e55f479b137da13ca83b27bb304a9 (patch) | |
| tree | 31ef2428b6a703114892f89f186b867e555596f3 /firmware | |
| parent | 4c1c77e085599f6f95df4b94714e1d7829ebefbf (diff) | |
lib: atomics: fix AMO test macros
The "RISC-V C API" [1] defines architecture extension test macros
says naming rule for the test macros is __riscv_<ext_name>, where
<ext_name> is all lower-case.
Three extensions dealing with atomics implementation are:
"zaamo" consists of AMO instructions,
"zalrsc" - LR/SC,
"a" extension means both "zaamo" and "zalrsc"
Built-in test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc.
Alternative to the __riscv_a macro name, __riscv_atomic, is deprecated.
Use correct test macro __riscv_zaamo for the AMO variant of atomics.
It used to be __riscv_atomic that is both deprecated and incorrect
because it tests for the "a" extension; i.e. both "zaamo" and "zalrsc"
If ISA enables only zaamo but not zalrsc, code as it was would not compile.
Older toolchains may have neither __riscv_zaamo nor __riscv_zalrsc, so
query __riscv_atomic - it should be treated as both __riscv_zaamo and
__riscv_zalrsc, in all present cases __riscv_zaamo is more favorable
so take is as alternative for __riscv_zaamo
[1] https://github.com/riscv-non-isa/riscv-c-api-doc
Signed-off-by: Vladimir Kondratiev <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/fw_base.S | 4 | ||||
| -rw-r--r-- | firmware/payloads/test_head.S | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index 5300ecf2..bce9e226 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -59,10 +59,10 @@ _try_lottery: /* Jump to relocation wait loop if we don't get relocation lottery */ lla a6, _boot_lottery li a7, BOOT_LOTTERY_ACQUIRED -#ifdef __riscv_atomic +#if defined(__riscv_atomic) || defined(__riscv_zaamo) amoswap.w a6, a7, (a6) bnez a6, _wait_for_boot_hart -#elif __riscv_zalrsc +#elif defined(__riscv_zalrsc) _sc_fail: lr.w t0, (a6) sc.w t1, a7, (a6) diff --git a/firmware/payloads/test_head.S b/firmware/payloads/test_head.S index 070ce8aa..9a87e56f 100644 --- a/firmware/payloads/test_head.S +++ b/firmware/payloads/test_head.S @@ -30,9 +30,9 @@ _start: /* Pick one hart to run the main boot sequence */ lla a3, _hart_lottery li a2, 1 -#ifdef __riscv_atomic +#if defined(__riscv_atomic) || defined(__riscv_zaamo) amoadd.w a3, a2, (a3) -#elif __riscv_zalrsc +#elif defined(__riscv_zalrsc) _sc_fail: lr.w t0, (a3) addw t1, t0, a2 |