diff options
| author | Samuel Holland <[email protected]> | 2025-03-04 17:45:43 -0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2025-04-13 05:51:17 +0530 |
| commit | afa0e3091bebf2aaba167f37119a9a4f608a55a8 (patch) | |
| tree | f26bc7e0175eb84099a08308c079d03bbad02ec4 /include | |
| parent | 995f226f3f335864d2fca6254af32fa7ab0162e6 (diff) | |
lib: sbi_trap: Add support for vectored interrupts
When redirecting an exception to S-mode, transform the (v)stvec CSR
value as described in the privileged spec to derive the S-mode PC.
Since OpenSBI never redirects interrupts, only synchronous exceptions,
the only action needed is to mask out the (v)stvec.MODE field.
Reported-by: Jan Reinhard <[email protected]>
Closes: https://github.com/riscv-software-src/opensbi/issues/391
Signed-off-by: Samuel Holland <[email protected]>
Reviwed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 84d3c17b..64f0249b 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -86,6 +86,8 @@ #define HSTATUS_GVA _UL(0x00000040) #define HSTATUS_VSBE _UL(0x00000020) +#define MTVEC_MODE _UL(0x00000003) + #define MCAUSE_IRQ_MASK (_UL(1) << (__riscv_xlen - 1)) #define IRQ_S_SOFT 1 |