diff options
| author | Zishun Yi <[email protected]> | 2026-04-30 02:17:47 +0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2026-06-09 22:12:48 +0530 |
| commit | 73bc794b40fc917feb146afd34970cf44563b561 (patch) | |
| tree | 859e5f3b7adcd6769a81224e7671fab2fba861db /lib/utils/cppc/objects.mk | |
| parent | 243035c565ac22a3d694247bd7fc324743999978 (diff) | |
lib: sbi_domain_context: Flush TLB after SATP mode switch
When switching between domains with different satp.MODE values (e.g.
Sv39 to Sv48), the RISC-V ISA permits hardware to use cached translations
from the old virtual-address width if no SFENCE.VMA intervenes. This
constrained-unpredictable behavior is clarified in riscv-isa-manual
PR #2219.
The hart protection re-configuration will anyway do full SFENCE / HFENCE
so move the hart protection re-configuration after register context switch
in switch_to_next_domain_context() to ensure translations from the new
domain's address width are used.
Link: https://github.com/riscv/riscv-isa-manual/pull/2219
Signed-off-by: Zishun Yi <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'lib/utils/cppc/objects.mk')
0 files changed, 0 insertions, 0 deletions
