diff options
| author | Icenowy Zheng <[email protected]> | 2022-12-12 16:22:37 +0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2022-12-17 11:01:03 +0530 |
| commit | ca7810aecdbae0630c506f05dbed641f3875ec5b (patch) | |
| tree | c2edf0a92745e26543f733ae4866c71ee6f5c30b /lib/utils/timer/aclint_mtimer.c | |
| parent | a8ee82cd8c008f09c91b5c307de4c9b37660ff71 (diff) | |
lib: utils/timer: mtimer: add a quirk for lacking mtime register
T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.
Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Diffstat (limited to 'lib/utils/timer/aclint_mtimer.c')
| -rw-r--r-- | lib/utils/timer/aclint_mtimer.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/lib/utils/timer/aclint_mtimer.c b/lib/utils/timer/aclint_mtimer.c index 3f00c218..1846a9a7 100644 --- a/lib/utils/timer/aclint_mtimer.c +++ b/lib/utils/timer/aclint_mtimer.c @@ -149,10 +149,10 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt, int rc; /* Sanity checks */ - if (!mt || !mt->mtime_size || + if (!mt || (mt->hart_count && !mt->mtimecmp_size) || - (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1)) || - (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1)) || + (mt->mtime_size && (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1))) || + (mt->mtime_size && (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1))) || (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) || (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) || (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) || @@ -178,6 +178,11 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt, for (i = 0; i < mt->hart_count; i++) mtimer_hartid2data[mt->first_hartid + i] = mt; + if (!mt->mtime_size) { + /* Disable reading mtime when mtime is not available */ + mtimer.timer_value = NULL; + } + /* Add MTIMER regions to the root domain */ if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) { rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr, |