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authorNick Hu <[email protected]>2023-01-17 16:14:27 +0800
committerAnup Patel <[email protected]>2023-02-08 10:39:20 +0530
commit8050081f68b2b66f8937b15a6753ec6408c2fdee (patch)
tree1af715441c6e1e628c6d3a711c00bdbf6991a8f2 /lib/utils/timer/objects.mk
parentc8ea836ee33eb778f48f780412e147386dac5301 (diff)
firmware: Not to clear all the MIP
In generic behavior of QEMU, if the pending bits of PLIC are still set and we clear the SEIP, the QEMU may not set the SEIP back immediately and the interrupt may not be handled anymore until the new interrupts arrived and QEMU set the SEIP back which is a generic behavior in QEMU. Signed-off-by: Nick Hu <[email protected]> Signed-off-by: Jim Shu <[email protected]> Reviewed-by: Anup Patel <[email protected]>
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