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| author | Lad Prabhakar <[email protected]> | 2022-12-10 10:30:09 +0000 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2022-12-12 18:50:46 +0530 |
| commit | 684090272af9ce84ff0768d8294bf7d42f14edeb (patch) | |
| tree | 26d2b0d6c57e4ef71fd7360338a5bd5dcf674b21 /lib/utils/timer | |
| parent | 0021b437377b4ea95f567f91fbf506c0b0b9e227 (diff) | |
lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
which is equipped with AX45MP AndesCore.
While at it drop the comma after the sentinel as it does not make sense to
have a comma after a sentinel, as any new elements must be added before the
sentinel.
dts example (Single-core AX45MP):
soc: soc {
....
plic: interrupt-controller@12c00000 {
compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
#interrupt-cells = <2>;
#address-cells = <0>;
riscv,ndev = <511>;
interrupt-controller;
reg = <0x0 0x12c00000 0 0x400000>;
clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
};
....
};
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Diffstat (limited to 'lib/utils/timer')
0 files changed, 0 insertions, 0 deletions
