diff options
| author | Yu Chien Peter Lin <[email protected]> | 2023-09-27 18:08:31 +0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2023-10-06 16:53:26 +0530 |
| commit | d36709fcafe2d39c3d999489a8ca836b138e4f04 (patch) | |
| tree | c1fefec1382d82c4484fef38cf6119e9aa632341 /lib/utils/timer | |
| parent | a12542316c98bbc8731dd6048d0a7ba3ab67fa6c (diff) | |
lib: utils: timer/ipi: Update memregion flags for PLMT and PLICSW
This patch adds unspecified permission flags for the PLICSW region
and updates the permission of the PLMT region.
With this update, both regions will become M-mode only read/write
regions in the root domain.
Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W)
Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: ()
Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: ()
> Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: ()
> Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: ()
Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
The PMP rules of AE350-AX65 (single-core) w/ Smepmp:
p/x $pmpcfg0
$1 = {0x1f9b9b9d9b1e00,
pmp0cfg = {0x0},
L--AAXWR
pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1)
pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff
pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff
pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff
pmp7cfg = {0x0 }}
The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp:
p/x $pmpcfg0
$1 = {0x1f181818181b,
L--AAXWR
pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1)
pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff
pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff
pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff
pmp6cfg = {0x0 }}
Note that starting from this patch, we restrict the S/U-mode read
permission to the PLMT region, since we should read the TIME CSR
in a lower privilege mode.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Diffstat (limited to 'lib/utils/timer')
| -rw-r--r-- | lib/utils/timer/andes_plmt.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/utils/timer/andes_plmt.c b/lib/utils/timer/andes_plmt.c index 94a86cc5..6e4bfafe 100644 --- a/lib/utils/timer/andes_plmt.c +++ b/lib/utils/timer/andes_plmt.c @@ -81,8 +81,11 @@ int plmt_cold_timer_init(struct plmt_data *plmt) /* Add PLMT region to the root domain */ rc = sbi_domain_root_add_memrange( - (unsigned long)plmt->time_val, plmt->size, PLMT_REGION_ALIGN, - SBI_DOMAIN_MEMREGION_MMIO | SBI_DOMAIN_MEMREGION_READABLE); + (unsigned long)plmt->time_val, plmt->size, + PLMT_REGION_ALIGN, + SBI_DOMAIN_MEMREGION_MMIO | + SBI_DOMAIN_MEMREGION_M_READABLE | + SBI_DOMAIN_MEMREGION_M_WRITABLE); if (rc) return rc; |