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authorBo Gan <[email protected]>2026-06-05 00:57:08 -0700
committerAnup Patel <[email protected]>2026-06-15 10:38:09 +0530
commit7bff4e529e6c32df5c9364960c174fa1a682cd5d (patch)
treef3af882c8c83f075793094ad2fdf9addc409dd17 /lib/utils
parent0f42eff6eaca80bd483292c8911292cbaa2341fd (diff)
platform: generic: eswin: Add eic770x_hsm and fix warm reset issues
During warm reset, my EIC770X/Hifive Premier P550 can sometimes encounter memory corruption issue crashing Linux boot. Currently the issue is mitigated by having a sbi_printf before writing to the reset register. I analyzed the issue further since then. From the SoC datasheet[1], it's recommended to implement power-down flow as: a. Designate a primary core, and let it broadcast requests to other cores to execute a CEASE insn. Primary core also notifies an "Externel Agent" to start monitoring. b. Primary core waits for other cores to CEASE before it CEASEs. c. "External Agent" waits for primary core to CEASE before resets the Core Complex. It's possible that EIC770X can trigger undefined behavior if the core complex is reset while the harts are actively running. The sbi_printf in the reset handler effectively hides the problem by delaying the reset -- by the time sbi_printf finishes, all other harts will have already landed in the loop in sbi_hsm_hart_wait(), which parks the hart. Without the sbi_printf, I confirmed that other harts haven't reached sbi_hsm_hart_wait yet before current hart resets the SoC. (by debugging) To safely reset, and inspired by the datasheet, the warm reset logic in eic770x.c now use the current hart as both primary core and the "External Agent", and other harts as secondary cores. It leverages the HSM framework and a new eic770x_hsm device to CEASE other harts, and wait for them to CEASE before resets the SoC. with the sbi_printf before reset removed, and this logic in place, stress test shows that the memory corruption issue no longer occurs. The new eic770x_hsm device is only used for the reset-CEASE logic at the moment, and may be extended to a fully functional HSM device in the future. [1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual Fixes: e5797e0688c1 ("platform: generic: eswin: add EIC7700") Signed-off-by: Bo Gan <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
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