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authorHuaqi Fang <[email protected]>2020-06-12 17:01:49 +0800
committerAnup Patel <[email protected]>2020-06-17 21:06:40 +0530
commit518e85cccb18a6dfe71fc8d1227c8f8d74527dc9 (patch)
tree316d87e2a2e4f7d93e9ec5347c12bda42b242bb1 /lib
parent6966ad0abe7077b1b5c9342f588621426d997c38 (diff)
platform: Update Nuclei ux600 platform support
Changes are made to support our FPGA evaluation board, it has DDR memory(0xA0000000-0xB0000000). * Adapt the config.mk to match FPGA evaluation board DDR memory address * Since the RISC-V CPU core frequency of FPGA might change, so we use the fixed TIMER frequency to measure the real CPU core frequency. * And the UART baudrate has to set to 57600bps for Nuclei FPGA evaluation board when CPU core frequency is about 8MHz, otherwise the UART input will not work correctly. Signed-off-by: Huaqi Fang <[email protected]> Reviewed-by: Anup Patel <[email protected]>
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