diff options
| author | Rajnesh Kanwal <[email protected]> | 2025-03-07 12:44:41 +0000 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2025-04-13 06:11:43 +0530 |
| commit | aa40c53ce498d1774f7779ea25ab1326640d8c63 (patch) | |
| tree | c33e66dfa8bfdc510d5e37f43926b211e9484d9b /lib | |
| parent | afa0e3091bebf2aaba167f37119a9a4f608a55a8 (diff) | |
lib: sbi: Enable Control Transfer Records (CTR) Ext using xstateen.
The Control Transfer Records (CTR) extension provides a method to
record a limited branch history in register-accessible internal chip
storage.
This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here
https://github.com/riscv/riscv-control-transfer-records/release
Signed-off-by: Rajnesh Kanwal <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/sbi/sbi_hart.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 8e2979b5..c343805c 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -105,6 +105,11 @@ static void mstatus_init(struct sbi_scratch *scratch) else mstateen_val &= ~(SMSTATEEN0_SVSLCT); + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCTR)) + mstateen_val |= SMSTATEEN0_CTR; + else + mstateen_val &= ~SMSTATEEN0_CTR; + csr_write(CSR_MSTATEEN0, mstateen_val); #if __riscv_xlen == 32 csr_write(CSR_MSTATEEN0H, mstateen_val >> 32); @@ -688,6 +693,8 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = { __SBI_HART_EXT_DATA(zicfilp, SBI_HART_EXT_ZICFILP), __SBI_HART_EXT_DATA(zicfiss, SBI_HART_EXT_ZICFISS), __SBI_HART_EXT_DATA(ssdbltrp, SBI_HART_EXT_SSDBLTRP), + __SBI_HART_EXT_DATA(smctr, SBI_HART_EXT_SMCTR), + __SBI_HART_EXT_DATA(ssctr, SBI_HART_EXT_SSCTR), }; _Static_assert(SBI_HART_EXT_MAX == array_size(sbi_hart_ext), |