diff options
| author | Alvin Chang <[email protected]> | 2025-07-03 23:19:56 +0800 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2025-07-20 20:54:34 +0530 |
| commit | ea5abd1f5e33ed3afedc92686ec8bfd00bc49235 (patch) | |
| tree | e917fe60050c62f2c0a7806715f7647a5d4d64c6 /lib | |
| parent | 61083eb504e853e18c57f9f5794f8318c267d091 (diff) | |
lib: sbi: Remove redundant call to sbi_hart_expected_trap_addr()
The variable "sbi_hart_expected_trap" has already been extern variable.
Therefore, the program can directly refer to it instead of calling
sbi_hart_expected_trap_addr().
Signed-off-by: Alvin Chang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/sbi/sbi_illegal_atomic.c | 4 | ||||
| -rw-r--r-- | lib/sbi/sbi_unpriv.c | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/lib/sbi/sbi_illegal_atomic.c b/lib/sbi/sbi_illegal_atomic.c index 2161b237..8fd6c557 100644 --- a/lib/sbi/sbi_illegal_atomic.c +++ b/lib/sbi/sbi_illegal_atomic.c @@ -30,7 +30,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs) { \ register ulong tinfo asm("a3"); \ register ulong mstatus = 0; \ - register ulong mtvec = sbi_hart_expected_trap_addr(); \ + register ulong mtvec = (ulong)sbi_hart_expected_trap; \ type ret = 0; \ trap->cause = 0; \ asm volatile( \ @@ -57,7 +57,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs) { \ register ulong tinfo asm("a3"); \ register ulong mstatus = 0; \ - register ulong mtvec = sbi_hart_expected_trap_addr(); \ + register ulong mtvec = (ulong)sbi_hart_expected_trap; \ type ret = 0; \ trap->cause = 0; \ asm volatile( \ diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c index 2a55d9db..f9bbec59 100644 --- a/lib/sbi/sbi_unpriv.c +++ b/lib/sbi/sbi_unpriv.c @@ -24,7 +24,7 @@ { \ register ulong tinfo asm("a3"); \ register ulong mstatus = 0; \ - register ulong mtvec = sbi_hart_expected_trap_addr(); \ + register ulong mtvec = (ulong)sbi_hart_expected_trap; \ type ret = 0; \ trap->cause = 0; \ asm volatile( \ @@ -51,7 +51,7 @@ { \ register ulong tinfo asm("a3") = (ulong)trap; \ register ulong mstatus = 0; \ - register ulong mtvec = sbi_hart_expected_trap_addr(); \ + register ulong mtvec = (ulong)sbi_hart_expected_trap; \ trap->cause = 0; \ asm volatile( \ "add %[tinfo], %[taddr], zero\n" \ @@ -121,7 +121,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap) register ulong tinfo asm("a3"); register ulong ttmp asm("a4"); register ulong mstatus = 0; - register ulong mtvec = sbi_hart_expected_trap_addr(); + register ulong mtvec = (ulong)sbi_hart_expected_trap; ulong insn = 0; trap->cause = 0; |