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authorVladimir Kondratiev <[email protected]>2026-02-23 16:54:57 +0200
committerAnup Patel <[email protected]>2026-02-25 18:49:03 +0530
commit2ca2e0caf081ca1bbab8bf42d645268a95ad72e2 (patch)
treeb1d6cc89dcc6579326ea918cc3e9a8a23e093aa6 /platform/generic/include/mips/p8700.h
parenta3aeef7c14bd3fd3b67379e84f5a954d59554df4 (diff)
platform: generic: mips eyeq7h: synchronize timers across clusters
Use eyeq7 specific method to synchronously restart architectural mtimer and eyeq7h specific high-resolution timer with common hardware trigger. This ensures all timers are precisely in sync Signed-off-by: Vladimir Kondratiev <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'platform/generic/include/mips/p8700.h')
-rw-r--r--platform/generic/include/mips/p8700.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/platform/generic/include/mips/p8700.h b/platform/generic/include/mips/p8700.h
index 4530fdf0..06756355 100644
--- a/platform/generic/include/mips/p8700.h
+++ b/platform/generic/include/mips/p8700.h
@@ -147,6 +147,11 @@ extern const struct p8700_cm_info *p8700_cm_info;
/* CPC Block offsets */
#define CPC_PWRUP_CTL 0x0030
+#define CPC_TIMECTL 0x0058
+#define TIMECTL_HARMED BIT(3)
+#define TIMECTL_HSTOP BIT(2)
+#define TIMECTL_MARMED BIT(1)
+#define TIMECTL_MSTOP BIT(0)
#define CPC_HRTIME 0x0090
#define CPC_CM_STAT_CONF 0x1008