diff options
| author | Anup Patel <[email protected]> | 2021-05-21 16:33:33 +0530 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2021-06-24 09:39:55 +0530 |
| commit | a731c7e36988c3308e1978ecde491f2f6182d490 (patch) | |
| tree | e6d966c4cc40d92863326914bc1e8b736bcf93c6 /platform/nuclei | |
| parent | 03d6bb51ba96a16a8ac9a2fcbaebec9f6c31d900 (diff) | |
platform: Replace CLINT library usage with ACLINT library
The ACLINT devices are backward compatible with SiFive CLINT
so we replace all CLINT library usage in various platforms
with ACLINT library. As a result of this replacement, the
CLINT library is not used by any part of OpenSBI hence we
remove it.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Xiang W <[email protected]>
Diffstat (limited to 'platform/nuclei')
| -rw-r--r-- | platform/nuclei/ux600/platform.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c index 5414316c..22ca4c9c 100644 --- a/platform/nuclei/ux600/platform.c +++ b/platform/nuclei/ux600/platform.c @@ -17,9 +17,10 @@ #include <sbi/sbi_platform.h> #include <sbi/sbi_system.h> #include <sbi_utils/fdt/fdt_fixup.h> +#include <sbi_utils/ipi/aclint_mswi.h> #include <sbi_utils/irqchip/plic.h> #include <sbi_utils/serial/sifive-uart.h> -#include <sbi_utils/sys/clint.h> +#include <sbi_utils/timer/aclint_mtimer.h> /* clang-format off */ @@ -32,6 +33,10 @@ #define UX600_NUCLEI_TIMER_MSFTRST_KEY 0x80000A5F /* The clint compatiable timer offset is 0x1000 against nuclei timer */ #define UX600_CLINT_TIMER_ADDR (UX600_NUCLEI_TIMER_ADDR + 0x1000) +#define UX600_ACLINT_MSWI_ADDR (UX600_CLINT_TIMER_ADDR + \ + CLINT_MSWI_OFFSET) +#define UX600_ACLINT_MTIMER_ADDR (UX600_CLINT_TIMER_ADDR + \ + CLINT_MTIMER_OFFSET) #define UX600_PLIC_ADDR 0x8000000 #define UX600_PLIC_NUM_SOURCES 0x35 @@ -61,12 +66,21 @@ static struct plic_data plic = { .num_src = UX600_PLIC_NUM_SOURCES, }; -static struct clint_data clint = { - .addr = UX600_CLINT_TIMER_ADDR, +static struct aclint_mswi_data mswi = { + .addr = UX600_ACLINT_MSWI_ADDR, + .size = ACLINT_MSWI_SIZE, + .first_hartid = 0, + .hart_count = UX600_HART_COUNT, +}; + +static struct aclint_mtimer_data mtimer = { + .addr = UX600_ACLINT_MTIMER_ADDR, + .size = ACLINT_MTIMER_SIZE, .first_hartid = 0, .hart_count = UX600_HART_COUNT, .has_64bit_mmio = TRUE, }; + static u32 measure_cpu_freq(u32 n) { u32 start_mtime, delta_mtime; @@ -188,12 +202,12 @@ static int ux600_ipi_init(bool cold_boot) int rc; if (cold_boot) { - rc = clint_cold_ipi_init(&clint); + rc = aclint_mswi_cold_init(&mswi); if (rc) return rc; } - return clint_warm_ipi_init(); + return aclint_mswi_warm_init(); } static int ux600_timer_init(bool cold_boot) @@ -201,12 +215,12 @@ static int ux600_timer_init(bool cold_boot) int rc; if (cold_boot) { - rc = clint_cold_timer_init(&clint, NULL); + rc = aclint_mtimer_cold_init(&mtimer, NULL); if (rc) return rc; } - return clint_warm_timer_init(); + return aclint_mtimer_warm_init(); } const struct sbi_platform_operations platform_ops = { |