diff options
| author | Anup Patel <[email protected]> | 2023-12-11 14:07:56 +0530 |
|---|---|---|
| committer | Anup Patel <[email protected]> | 2023-12-19 15:56:37 +0530 |
| commit | cdebae2cc9539e2e0553b9c68eab22997c734cbb (patch) | |
| tree | 3a0c68c8935b8381ba36da2eb60eaf7e350d2da1 /platform/nuclei | |
| parent | 80169b25f8a9a7cb8becceff9a414900919527c6 (diff) | |
lib: utils/irqchip: Add shared MMIO region for PLIC in root domain
On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.
If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.
Signed-off-by: Anup Patel <[email protected]>
Diffstat (limited to 'platform/nuclei')
| -rw-r--r-- | platform/nuclei/ux600/platform.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c index 6fd6cd70..f688b50a 100644 --- a/platform/nuclei/ux600/platform.c +++ b/platform/nuclei/ux600/platform.c @@ -39,6 +39,8 @@ CLINT_MTIMER_OFFSET) #define UX600_PLIC_ADDR 0x8000000 +#define UX600_PLIC_SIZE (0x200000 + \ + (UX600_HART_COUNT * 0x1000)) #define UX600_PLIC_NUM_SOURCES 0x35 #define UX600_PLIC_NUM_PRIORITIES 7 @@ -63,6 +65,7 @@ static u32 ux600_clk_freq = 8000000; static struct plic_data plic = { .addr = UX600_PLIC_ADDR, + .size = UX600_PLIC_SIZE, .num_src = UX600_PLIC_NUM_SOURCES, }; |