diff options
| -rw-r--r-- | include/sbi/riscv_encoding.h | 5 | ||||
| -rw-r--r-- | lib/sbi/sbi_hart.c | 20 |
2 files changed, 9 insertions, 16 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 0996d649..f20df761 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -207,13 +207,8 @@ #define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) -#if __riscv_xlen > 32 #define ENVCFG_STCE (_ULL(1) << 63) #define ENVCFG_PBMTE (_ULL(1) << 62) -#else -#define ENVCFGH_STCE (_UL(1) << 31) -#define ENVCFGH_PBMTE (_UL(1) << 30) -#endif #define ENVCFG_CBZE (_UL(1) << 7) #define ENVCFG_CBCFE (_UL(1) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 27390052..bef4e6a3 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -33,11 +33,11 @@ static unsigned long hart_features_offset; static void mstatus_init(struct sbi_scratch *scratch) { - unsigned long menvcfg_val, mstatus_val = 0; int cidx; + unsigned long mstatus_val = 0; unsigned int mhpm_mask = sbi_hart_mhpm_mask(scratch); uint64_t mhpmevent_init_val = 0; - uint64_t mstateen_val; + uint64_t menvcfg_val, mstateen_val; /* Enable FPU */ if (misa_extension('D') || misa_extension('F')) @@ -108,6 +108,9 @@ static void mstatus_init(struct sbi_scratch *scratch) if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) { menvcfg_val = csr_read(CSR_MENVCFG); +#if __riscv_xlen == 32 + menvcfg_val |= ((uint64_t)csr_read(CSR_MENVCFGH)) << 32; +#endif /* * Set menvcfg.CBZE == 1 @@ -148,18 +151,13 @@ static void mstatus_init(struct sbi_scratch *scratch) * Enable access to stimecmp if sstc extension is present in the * hardware. */ - if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSTC)) { -#if __riscv_xlen == 32 - unsigned long menvcfgh_val; - menvcfgh_val = csr_read(CSR_MENVCFGH); - menvcfgh_val |= ENVCFGH_STCE; - csr_write(CSR_MENVCFGH, menvcfgh_val); -#else + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSTC)) menvcfg_val |= ENVCFG_STCE; -#endif - } csr_write(CSR_MENVCFG, menvcfg_val); +#if __riscv_xlen == 32 + csr_write(CSR_MENVCFGH, menvcfg_val >> 32); +#endif /* Enable S-mode access to seed CSR */ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_ZKR)) { |