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-rw-r--r--docs/platform/fpga-openpiton.md6
-rw-r--r--docs/platform/generic.md2
-rw-r--r--docs/platform/platform.md5
-rw-r--r--platform/fpga/openpiton/Kconfig10
-rw-r--r--platform/fpga/openpiton/configs/defconfig0
-rw-r--r--platform/fpga/openpiton/objects.mk41
-rw-r--r--platform/generic/Kconfig4
-rw-r--r--platform/generic/configs/defconfig1
-rw-r--r--platform/generic/openhwgroup/objects.mk8
-rw-r--r--platform/generic/openhwgroup/openpiton.c (renamed from platform/fpga/openpiton/platform.c)59
-rwxr-xr-xscripts/create-binary-archive.sh1
11 files changed, 44 insertions, 93 deletions
diff --git a/docs/platform/fpga-openpiton.md b/docs/platform/fpga-openpiton.md
index 7861a197..e5352884 100644
--- a/docs/platform/fpga-openpiton.md
+++ b/docs/platform/fpga-openpiton.md
@@ -7,8 +7,8 @@ processor from ETH Zurich. To this end, Ariane has been equipped with a
different L1 cache subsystem that follows a write-through protocol and that has
support for cache invalidations and atomics.
-To build platform specific library and firmwares, provide the
-*PLATFORM=fpga/openpiton* parameter to the top level `make` command.
+To build platform specific library and firmwares, provide the *PLATFORM=generic*
+parameter to the top level `make` command.
Platform Options
----------------
@@ -21,7 +21,7 @@ Building Ariane FPGA Platform
**Linux Kernel Payload**
```
-make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
```
Booting Ariane FPGA Platform
diff --git a/docs/platform/generic.md b/docs/platform/generic.md
index 709b436e..495baa73 100644
--- a/docs/platform/generic.md
+++ b/docs/platform/generic.md
@@ -47,6 +47,7 @@ RISC-V Platforms Using Generic Platform
* **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
* **Spike** (*[spike.md]*)
* **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
+* **OpenPiton FPGA SoC** (*[fpga-openpiton.md]*)
[andes-ae350.md]: andes-ae350.md
[qemu_virt.md]: qemu_virt.md
@@ -55,3 +56,4 @@ RISC-V Platforms Using Generic Platform
[sifive_fu540.md]: sifive_fu540.md
[spike.md]: spike.md
[thead-c9xx.md]: thead-c9xx.md
+[fpga-openpiton.md]: fpga-openpiton.md
diff --git a/docs/platform/platform.md b/docs/platform/platform.md
index 4504d87a..048c2c4f 100644
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -31,10 +31,6 @@ OpenSBI currently supports the following virtual and hardware platforms:
* **Spike**: Platform support for the Spike emulator. More
details on this platform can be found in the file *[spike.md]*.
-* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based
- on ariane core. More details on this platform can be found in the file
- *[fpga-openpiton.md]*.
-
* **Shakti C-class SoC Platform**: Platform support for Shakti C-class
processor based SOCs. More details on this platform can be found in the
file *[shakti_cclass.md]*.
@@ -56,6 +52,5 @@ comments to facilitate the implementation.
[andes-ae350.md]: andes-ae350.md
[thead-c910.md]: thead-c910.md
[spike.md]: spike.md
-[fpga-openpiton.md]: fpga-openpiton.md
[shakti_cclass.md]: shakti_cclass.md
[renesas-rzfive.md]: renesas-rzfive.md
diff --git a/platform/fpga/openpiton/Kconfig b/platform/fpga/openpiton/Kconfig
deleted file mode 100644
index bc9c86ee..00000000
--- a/platform/fpga/openpiton/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-config PLATFORM_OPENPITON_FPGA
- bool
- select FDT
- select IPI_MSWI
- select IRQCHIP_PLIC
- select SERIAL_UART8250
- select TIMER_MTIMER
- default y
diff --git a/platform/fpga/openpiton/configs/defconfig b/platform/fpga/openpiton/configs/defconfig
deleted file mode 100644
index e69de29b..00000000
--- a/platform/fpga/openpiton/configs/defconfig
+++ /dev/null
diff --git a/platform/fpga/openpiton/objects.mk b/platform/fpga/openpiton/objects.mk
deleted file mode 100644
index 1a0ce0c7..00000000
--- a/platform/fpga/openpiton/objects.mk
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# SPDX-License-Identifier: BSD-2-Clause
-#
-# Copyright (c) 2020 Western Digital Corporation or its affiliates.
-#
-
-# Compiler flags
-platform-cppflags-y =
-platform-cflags-y =
-platform-asflags-y =
-platform-ldflags-y =
-
-# Objects to build
-platform-objs-y += platform.o
-
-PLATFORM_RISCV_XLEN = 64
-
-# Blobs to build
-FW_JUMP=n
-
-ifeq ($(PLATFORM_RISCV_XLEN), 32)
- # This needs to be 4MB aligned for 32-bit support
- FW_JUMP_ADDR=0x80400000
- else
- # This needs to be 2MB aligned for 64-bit support
- FW_JUMP_ADDR=0x80200000
- endif
-FW_JUMP_FDT_ADDR=0x82200000
-
-# Firmware with payload configuration.
-FW_PAYLOAD=y
-
-ifeq ($(PLATFORM_RISCV_XLEN), 32)
-# This needs to be 4MB aligned for 32-bit support
- FW_PAYLOAD_OFFSET=0x400000
-else
-# This needs to be 2MB aligned for 64-bit support
- FW_PAYLOAD_OFFSET=0x200000
-endif
-FW_PAYLOAD_FDT_ADDR=0x82200000
-FW_PAYLOAD_ALIGN=0x1000
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index a24d6ab2..7559a4bd 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -36,6 +36,10 @@ config PLATFORM_ANDES_AE350
select ANDES_PMA
default n
+config PLATFORM_OPENHWGROUP_OPENPITON
+ bool "OpenHWGroup Openpiton support"
+ default n
+
config PLATFORM_RENESAS_RZFIVE
bool "Renesas RZ/Five support"
select ANDES_PMA
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c7a6531e..4b93d0bc 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -7,6 +7,7 @@ CONFIG_PLATFORM_SOPHGO_SG2042=y
CONFIG_PLATFORM_STARFIVE_JH7110=y
CONFIG_PLATFORM_THEAD=y
CONFIG_PLATFORM_MIPS_P8700=y
+CONFIG_PLATFORM_OPENHWGROUP_OPENPITON=y
CONFIG_FDT_CPPC=y
CONFIG_FDT_CPPC_RPMI=y
CONFIG_FDT_GPIO=y
diff --git a/platform/generic/openhwgroup/objects.mk b/platform/generic/openhwgroup/objects.mk
new file mode 100644
index 00000000..ab6ca79d
--- /dev/null
+++ b/platform/generic/openhwgroup/objects.mk
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2020 Western Digital Corporation or its affiliates.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_OPENHWGROUP_OPENPITON) += openhwgroup_openpiton
+platform-objs-$(CONFIG_PLATFORM_OPENHWGROUP_OPENPITON) += openhwgroup/openpiton.o
diff --git a/platform/fpga/openpiton/platform.c b/platform/generic/openhwgroup/openpiton.c
index faa299ce..9be7f9a4 100644
--- a/platform/fpga/openpiton/platform.c
+++ b/platform/generic/openhwgroup/openpiton.c
@@ -3,12 +3,7 @@
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*/
-#include <sbi/riscv_asm.h>
-#include <sbi/riscv_encoding.h>
-#include <sbi/riscv_io.h>
-#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
-#include <sbi/sbi_platform.h>
+#include <platform_override.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/ipi/aclint_mswi.h>
@@ -16,19 +11,19 @@
#include <sbi_utils/serial/uart8250.h>
#include <sbi_utils/timer/aclint_mtimer.h>
-#define OPENPITON_DEFAULT_UART_ADDR 0xfff0c2c000
+#define OPENPITON_DEFAULT_UART_ADDR 0xfff0c2c000ULL
#define OPENPITON_DEFAULT_UART_FREQ 60000000
#define OPENPITON_DEFAULT_UART_BAUDRATE 115200
#define OPENPITON_DEFAULT_UART_REG_SHIFT 0
#define OPENPITON_DEFAULT_UART_REG_WIDTH 1
#define OPENPITON_DEFAULT_UART_REG_OFFSET 0
#define OPENPITON_DEFAULT_UART_CAPS 0
-#define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000
+#define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000ULL
#define OPENPITON_DEFAULT_PLIC_SIZE (0x200000 + \
(OPENPITON_DEFAULT_HART_COUNT * 0x1000))
#define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2
#define OPENPITON_DEFAULT_HART_COUNT 3
-#define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000
+#define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000ULL
#define OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ 1000000
#define OPENPITON_DEFAULT_ACLINT_MSWI_ADDR \
(OPENPITON_DEFAULT_CLINT_ADDR + CLINT_MSWI_OFFSET)
@@ -36,12 +31,12 @@
(OPENPITON_DEFAULT_CLINT_ADDR + CLINT_MTIMER_OFFSET)
static struct platform_uart_data uart = {
- OPENPITON_DEFAULT_UART_ADDR,
+ (unsigned long)OPENPITON_DEFAULT_UART_ADDR,
OPENPITON_DEFAULT_UART_FREQ,
OPENPITON_DEFAULT_UART_BAUDRATE,
};
static struct plic_data plic = {
- .addr = OPENPITON_DEFAULT_PLIC_ADDR,
+ .addr = (unsigned long)OPENPITON_DEFAULT_PLIC_ADDR,
.size = OPENPITON_DEFAULT_PLIC_SIZE,
.num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES,
.flags = PLIC_FLAG_ARIANE_BUG,
@@ -53,7 +48,7 @@ static struct plic_data plic = {
};
static struct aclint_mswi_data mswi = {
- .addr = OPENPITON_DEFAULT_ACLINT_MSWI_ADDR,
+ .addr = (unsigned long)OPENPITON_DEFAULT_ACLINT_MSWI_ADDR,
.size = ACLINT_MSWI_SIZE,
.first_hartid = 0,
.hart_count = OPENPITON_DEFAULT_HART_COUNT,
@@ -61,10 +56,10 @@ static struct aclint_mswi_data mswi = {
static struct aclint_mtimer_data mtimer = {
.mtime_freq = OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ,
- .mtime_addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
+ .mtime_addr = (unsigned long)OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIME_OFFSET,
.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
- .mtimecmp_addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
+ .mtimecmp_addr = (unsigned long)OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIMECMP_OFFSET,
.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
.first_hartid = 0,
@@ -156,25 +151,23 @@ static int openpiton_timer_init(void)
return aclint_mtimer_cold_init(&mtimer, NULL);
}
-/*
- * Platform descriptor.
- */
-const struct sbi_platform_operations platform_ops = {
- .early_init = openpiton_early_init,
- .final_init = openpiton_final_init,
- .irqchip_init = openpiton_irqchip_init,
- .ipi_init = openpiton_ipi_init,
- .timer_init = openpiton_timer_init,
+static int openhwgroup_openpiton_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
+{
+ generic_platform_ops.early_init = openpiton_early_init;
+ generic_platform_ops.timer_init = openpiton_timer_init;
+ generic_platform_ops.ipi_init = openpiton_ipi_init;
+ generic_platform_ops.irqchip_init = openpiton_irqchip_init;
+ generic_platform_ops.final_init = openpiton_final_init;
+
+ return 0;
+}
+
+static const struct fdt_match openhwgroup_openpiton_match[] = {
+ { .compatible = "openpiton,cva6platform" },
+ { },
};
-const struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION,
- .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
- .name = "OPENPITON RISC-V",
- .features = SBI_PLATFORM_DEFAULT_FEATURES,
- .hart_count = OPENPITON_DEFAULT_HART_COUNT,
- .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
- .heap_size =
- SBI_PLATFORM_DEFAULT_HEAP_SIZE(OPENPITON_DEFAULT_HART_COUNT),
- .platform_ops_addr = (unsigned long)&platform_ops
+const struct fdt_driver openhwgroup_openpiton = {
+ .match_table = openhwgroup_openpiton_match,
+ .init = openhwgroup_openpiton_platform_init,
};
diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
index 73bdef21..19ae9045 100755
--- a/scripts/create-binary-archive.sh
+++ b/scripts/create-binary-archive.sh
@@ -102,7 +102,6 @@ build_opensbi() {
BUILD_PLATFORM_SUBDIR+=("nuclei/ux600")
BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
- BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
BUILD_PLATFORM_SUBDIR+=("generic")
;;
*)
generated by cgit v1.3.1 (git 2.54.0) at 2026-09-04 12:33:54 +0000