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-rw-r--r--lib/utils/serial/fdt_serial_uart8250.c7
-rw-r--r--lib/utils/serial/uart8250.c11
2 files changed, 14 insertions, 4 deletions
diff --git a/lib/utils/serial/fdt_serial_uart8250.c b/lib/utils/serial/fdt_serial_uart8250.c
index af5ceac9..3a6650d6 100644
--- a/lib/utils/serial/fdt_serial_uart8250.c
+++ b/lib/utils/serial/fdt_serial_uart8250.c
@@ -14,8 +14,9 @@
static int serial_uart8250_init(const void *fdt, int nodeoff,
const struct fdt_match *match)
{
- int rc;
struct platform_uart_data uart = { 0 };
+ ulong caps = (ulong)match->data;
+ int rc;
rc = fdt_parse_uart_node(fdt, nodeoff, &uart);
if (rc)
@@ -23,13 +24,15 @@ static int serial_uart8250_init(const void *fdt, int nodeoff,
return uart8250_init(uart.addr, uart.freq, uart.baud,
uart.reg_shift, uart.reg_io_width,
- uart.reg_offset);
+ uart.reg_offset, caps);
}
static const struct fdt_match serial_uart8250_match[] = {
{ .compatible = "ns16550" },
{ .compatible = "ns16550a" },
{ .compatible = "snps,dw-apb-uart" },
+ { .compatible = "intel,xscale-uart",
+ .data = (void *)UART_CAP_UUE },
{ },
};
diff --git a/lib/utils/serial/uart8250.c b/lib/utils/serial/uart8250.c
index 1fe053f8..82fb142a 100644
--- a/lib/utils/serial/uart8250.c
+++ b/lib/utils/serial/uart8250.c
@@ -39,6 +39,12 @@
#define UART_LSR_DR 0x01 /* Receiver data ready */
#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
+/* The XScale PXA UARTs define these bits */
+#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
+#define UART_IER_UUE 0x40 /* UART Unit Enable */
+#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
+#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
+
/* clang-format on */
static volatile char *uart8250_base;
@@ -93,7 +99,7 @@ static struct sbi_console_device uart8250_console = {
};
int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
- u32 reg_width, u32 reg_offset)
+ u32 reg_width, u32 reg_offset, u32 caps)
{
u16 bdiv = 0;
@@ -109,7 +115,8 @@ int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
}
/* Disable all interrupts */
- set_reg(UART_IER_OFFSET, 0x00);
+ set_reg(UART_IER_OFFSET, (caps & UART_CAP_UUE) ?
+ UART_IER_UUE : 0x00);
/* Enable DLAB */
set_reg(UART_LCR_OFFSET, 0x80);