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We should use MTINST CSR in misaligned load/store emulation whenever
possible to avoid unpriv read in getting trapped instruction. This will
improve preformance on HW having proper implementation of MTINST CSR.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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The hypervisor v0.5 spec introduces two new CSRs for both M-mode
and HS-mode which need to be considered when redirecting traps
hence this patch.
Signed-off-by: Anup Patel <[email protected]>
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We should treat load guest page fault in sbi_get_insn() as
fetch guest patch fault.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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We have two new trap CSRs namely mtval2 and mtinst when
RISC-V hypervisor extension is available hence we extend
struct sbi_trap_info accordingly.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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As-per RISC-V hypervisor v0.5 spec, we have new guest page faults
which need to be delegated to HS-mode.
Also, we can have bits in in MIDELEG and MEDELEG hardwired to 1
which means we need to fix the sainty check on these CSRs at the
end of delegate_traps() function.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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With RISC-V H-extension v0.5 draft, we have special support for guest
external interrupts so this patch adds related defines which were
missed-out previously.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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GCC-9 will throw a warning when using the %s format specifier with a
possible NULL parameter and since -Werror is used, the compilation breaks
for GCC-9.
In function 'sbi_boot_prints',
inlined from 'init_coldboot' at <redacted>/opensbi/lib/sbi/sbi_init.c:107:3,
inlined from 'sbi_init' at <redacted>/opensbi/lib/sbi/sbi_init.c:189:3:
<redacted>/opensbi/lib/sbi/sbi_init.c:56:2: error: '%s' directive argument is null [-Werror=format-overflow=]
56 | sbi_printf("Platform Name : %s\n", sbi_platform_name(plat));
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cc1: all warnings being treated as errors
This is one way to fix this, currently there is nothing in the tree
checking for `sbi_platfrom_name() == NULL` so we can just return "Unknown"
instead of NULL on failure.
Signed-off-by: Martin Pietryka <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Tested-by: David Abdurachmanov <[email protected]>
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Add assertions for misa_extension to prevent incoming illegal
characters.
Signed-off-by: Xiang Wang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The break statement is missing in base extension function handling.
Fix the typo.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Xiang Wang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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On some platforms, misa may not be implemented. On such a platform,
reading misa will get 0. At this time, platform is required to
implement a non-standard function to detect the CPU's capabilities.
Therefore, this modification add interfaces for non-standard function.
The MXL field of misa is always at the highest two bits, whether it
is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification
fixes the use of a fixed offset to detect the machine length.
Signed-off-by: Xiang Wang <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
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The out_tcause and out_tval parameters are not sufficient for most
sbi_ecall functions because this will grow in-future when we support
RISC-V hypervisor v0.5 draft. We replace these parameters with out_trap
which is a pointer to struct sbi_trap_info.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The unpriv APIs can be useful to external firmware and out-of-tree
platform support code.
This patch adds "sbi_" prefix to unpriv load/store APIs and rename
struct riscv_unpriv to struct sbi_trap_info everywhere. We also
place struct sbi_trap_info in sbi/sbi_trap.h so that we can use
it for sbi_trap_redirect() as well.
Overall, this patch will make naming of unpriv APIs consistent
with other OpenSBI APIs.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We don't need to set VSSTATUS.MXR bit in get_insn() for
unpriv instruction read because MSTATUS.MXR bit applies
to both "Stage1" and "Stage2" page tables.
This also allows us to remove the "virt" parameter of
get_insn() function.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We simplify struct unpriv_trap by removing ilen member. This
can be achieved by ensuring that at all unpriv load/store
instructions are 4 bytes long using GCC assembler option.
Additionally, this also reduces few instructions from unpriv
load/store functions.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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Building the date and time into the binary means the OpenSBI isn't
reproducible. We don't really need the time so let's remove it.
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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It has been reported that link address range of previous booting stage
(such as U-Boot SPL) can overlap the link address rage of FW_DYNAMIC.
This means self-relocation in FW_DYNAMIC can potentially corrupt
previous booting stage if any of the secondary HART enter FW_DYNAMIC
before primary HART.
To tackle this, we add preferred boot HART field (i.e boot_hart) in
struct fw_dyanmic_info. We use this field to force secondary HARTs
into relocation wait loop till preferred/primary boot HART enters
FW_DYNAMIC completes self-relocation. If preferred boot HART is not
available then we fall back to relocation lottery approach.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The riscv_encoding.h is shared with assembly sources so we use
_UL() and _ULL() for register fields related defines.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This patch sync-up encoding header with the latest privilege
specifications draft v1.12 and hypervisor specifications draft v0.5.
The MSTATUS.MTL and HSTATUS.STL bits are not present anymore and
will be removed by another patch series for hypervisor v0.5-draft.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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Instead of forcing HART0 to do the relocation and scratch init
work, we should have an atomic lottery to decide which HART does
the relocation and scratch init.
This way any HART can be boot/main HART.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We get following compile error for FW_PAYLOAD with latest GCC
binutils:
fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte
boundary, but only 14 present
Further investigating, it turn-out to be a known issue with RISC-V
GCC binutils.
(Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298)
As a work-around, we disable relaxation when including DTB and
PAYLOAD binary in fw_payload.S.
Reported-by: David Abdurachmanov <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Tested-by: David Abdurachmanov <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This patch updates OpenSBI version to 0.5 as part of
release preparation.
Signed-off-by: Anup Patel <[email protected]>
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SBI v0.2 specification allows vendor extensions and it should be
implemented in a independent of the core sbi library.
Introduce a single platform callback that will let platforms handle
all vendor extensions in platform specific code if they want.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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SBI v0.2 introduces a base specification which is mandatory to
implement for any SBI implementations that is not legacy.
Add support for the base extension.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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An ecall handler should only return error if valid SBI function
fails. Otherwise, it should succeed with appropriate error in a0.
Get rid of unnecessary setting of the temporary return variable to
zero for the cases where errors are not expected.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Current SBI implementation is now considered as version 0.1 and will be
removed/replaced with newer extension/functions in future.
Rename the existing implementations accordingly to be in sync with the
specification.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Zong Li <[email protected]>
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Follow the SBI specification for error codes.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Test payload uses an SBI call and uses the macros defined in interface
header which is not the correct place to have these definitions.
The interface header file should be used to keep SBI specification
related macros.
Keep all the test payload related code in test itself.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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If we are running on RISC-V emulator/simulator with large number of
HARTs where each HART is a regular thread under UNIX host then it is
possible that some of the secondary HARTs don't get chance to run and
sbi_hart_wake_coldboot_harts() is called before secondary HARTs call
sbi_hart_wait_for_coldboot(). In this situation, some of the secondary
HARTs will never come-out of coldboot wait loop.
To tackle this, we introduce a global flag coldboot_done which will
be protected by coldboot lock and it will be set by primary HART from
sbi_hart_wake_coldboot_harts() before waking-up secondary HARTs. We
also re-arrange acquire/release of coldboot lock to reduce further
chances of race-condition.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Zong Li <[email protected]>
Reviewed-by: Nylon Chen<[email protected]>
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Currently, if someone has forked OpenSBI repo quite sometime back
and this fork is not having updated tags from upstream riscv/opensbi
repo then "git describe" command can fail. To tackle this, we redirect
error output of "git describe" to /dev/null.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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For platforms not having TIME CSR, we trap-n-emulate TIME CSR
read/write in OpenSBI. Same rationale applies to HTIMEDELTA CSR
as well so we trap-n-emulate HTIMEDELTA CSR for platforms not
having TIME CSR.
Signed-off-by: Anup Patel <[email protected]>
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Current implementation of get_insn() is not suitable for reading
instruction from VS/VU mode because we have to set SSTATUS_MXR bit
in VSSTATUS CSR for reading instruction from VS/VU mode.
This patch extends get_insn() to read instruction from VS/VU mode.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
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The WFI will trap as illegal instruction trap when executed
in VS/VU mode so we just forward/redirect it to HS-mode so
that hypervisor can deal with it appropriately.
Signed-off-by: Anup Patel <[email protected]>
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When hypervisor extension is available, we can get traps from VS/VU
modes. We should be able to force redirect some of these traps to
HS-mode. In other words, we should be able forward traps from VS/VU
mode to HS-mode using sbi_trap_redirect() hence this patch.
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
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This patch extends sbi_hart_switch_mode() to support entering
VS/VU modes when hypervisor extension is available.
Signed-off-by: Anup Patel <[email protected]>
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When hypervisor extension is available, we only handle hypervisor
ecalls coming from HS-mode and we let hypervisor handle ecalls coming
from VS-mode.
Signed-off-by: Anup Patel <[email protected]>
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The machine-level MSIP bits are written by accesses to memory-mapped
control registers. Only use CSR instruction for SSIP and USIP.
There is no effect that using CSR instruction to write MSIP when testing
on unleashed board and QEMU.
Signed-off-by: Zong Li <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Use platform defined flush range limit value only if it is non-zero.
Otherwise, use the default value.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Commit 9dfe72057957 ("kendryte/k210: remove sysctl code") missed
removing the file sysctl.c. Fix this here.
Fixes: 9dfe72057957 ("kendryte/k210: remove sysctl code")
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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With QEMU v4.2 release that has improved the emulation fidelity
of 'sifive_u' machine, OpenSBI v0.4 / U-Boot v2019.10-rc1 / Linux
kernel v5.3-rc2 images built for the SiFive HiFive Unleashed board
can be used out of the box without any special hack.
Update our documents to mention 'qemu/sifive_u' platform should
only be used with QEMU v4.1 or before, and it will be dropped
sometime in the future release.
Going forward, 'sifive/fu540' platform can be used on both real
hardware and QEMU v4.2+ 'sifive_u' machine.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Currently, the tlb range flush threshold is fixed and set to 4k for
all platforms. However, it should be platform specific as it completely
depends upon how platform actually implements sfence instruction.
Define a platform feature that allows every individual platform to set
different values. If a platform doesn't define it, just use a page size as
the threshold.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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In RISC-V, tlb flush happens at a page granularity. That's why OpenSBI
also have a tlb range flush limit which decides the which tlb flush
requests should be upgraded to full flush to avoid long delays.
Currently, this is set to 1G which would result in a many sfence.vma
execution in a tight loop for a large range.
Change the threshold to 4k to speed things up.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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With the Kendryte K210 platform code cleanup, none of the code copied
from Kendryte standalone SDK remains and this platform code is now
entirely licensed under OpenSBI BSD-2-clause license. Update the
README.md and ThirdPartyNotices.md files to reflect this.
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Directly implement frequency discovery, making the sysctl code
unnecessary. While at it, Move all macro definitions from platform.c
into platform.h and cleanup that file, removing the need for the
Apache 2.0 license and Canaan Inc copyright.
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The Kendryte K210 UARTHS is compatible with SiFive UART. So use the
sifive uart driver and remove the k210 uarths platform code.
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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U-Boot readme for fu540 platform suggest that fdt_addr_r should be used
as DT address after DT is copied via tftpboot.
Update the OpenSBI docs to reflect that. Remove other stale informations
as well.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Currently, we upgrade to a full tlb flush only If a tlb flush request
size is greater than the threshold. This is done as sfence in RISC-V
can only flush 4KB at a time. Doing a large number of flushes page by
page impacts the performance. It is better to do a full tlbflush if the
request size is at least equal to the threshold size.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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If compiler supports riscv atomic instructions, we should
use them instead of legacy gcc built-in macros
__sync_lock_test_and_set in atomic exchange functions.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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To read 64bit time in 32 bit we have to read lower & upper half
separately and 'or' them together. However, upper half time may
have changed by the time we read lower half. Thus, the resultant
64 bit time may not be accurate.
Consider lower half time value only if upper half time value has
not changed.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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This patch adds Andes AE350 to RV64 platform list in the binary
archive script.
Signed-off-by: Nylon Chen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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This commit provides basic support for the AE350 platform.
Signed-off-by: Zong Li <[email protected]>
Signed-off-by: Nylon Chen <[email protected]>
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