| Age | Commit message (Collapse) | Author |
|---|
|
Signed-off-by: Bo Gan <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Added exception handling for compressed instructions C.LHU, C.LH, and
C.SH from the zcb extension to the sbi_misaligned_ldst library.
Signed-off-by: Nylon Chen <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
register, so checking that the rs2 field is non-zero is unnecessary.
Additionally, the previous check was incorrect since it was checking
the immediate field of the instruction instead of the rs2 field.
Signed-off-by: Amanieu d'Antras <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
If a particular misaligned load or store cannot be emulated at all, for
the redirected trap, trap.gva is set to 0, but it should be the same as
mstatus[h].GVA of the original trap. Fix this so that if the trap is
destined for HS-mode, hstatus.GVA is then set correctly.
Fixes: 1c4ce74f5128 ("lib: sbi: Set gva when creating sbi_trap_info")
Signed-off-by: Vivian Wang <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
In some cases the sbi_trap_info argument passed to sbi_trap_redirect is
created from scratch by filling its fields. Since we previously added a
gva field to struct sbi_trap_info, initialize gva in these cases also.
Suggested-by: Andrew Jones <[email protected]>
Signed-off-by: Vivian Wang <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
If there is an exception while emulating a misaligned load/store, fixup
uptrap.tinst before redirecting. Otherwise, HS-mode software may receive
an htinst describing the lbu/sb instruction that faulted during
emulation[1].
[1]: https://github.com/riscv-software-src/opensbi/issues/258
Signed-off-by: dramforever <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
RISC-V SBI v0.3 specification defines a set of firmware events that can
provide additional information about the current firmware context. All
of the firmware event monitoring are enabled now. The firmware
events must be defined as raw perf event with MSB set as specified in the
specification.
Reviewed-by: Anup Patel <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
|
|
The misaligned load emulation does not sign-extend values correctly
due to missing sign typecast in value passed to the SET_RD() macro.
A very easy way to reproduce this issue is to load 16-bit value
0xff1e from a byte aligned address using LH instruction on hardware
lacking misaligned load/store.
This patch fixes sbi_misaligned_load_handler() for above issue.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
If MTINST[0:0] bit is 1 then we have transformed instruction encoding
in MTINST CSR. For transformed instructions, if the MTINST[1:1] bit
is Zero then original trapped instruction was a 16bit instruction
which was converted to 32bit instruction at time of taking trap.
We should use MTINST[1:1] bit to determine correct instruction length
of transformed instruction.
This patch updates misaligned load/store emulation as-per above.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
We remove mcause, scratch and hartid parameters from various functions
for misaligned load/store handling because we can always get current
HART id and current scratch pointer using just one CSR access.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
The scratch parameter of sbi_trap_redirect() is not used hence we
remove it.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
The scratch parameter of unpriv load/store functions is now redundant
hence we remove it.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
Compile time checks of __riscv_compressed can only check if OpenSBI is
being compiled using compressed instructions or not. Checking this macro
does not indicate if an instruction that generated a misaligned trap is
a compressed instruction or not.
Since the misaligned trap handling code inspects instructions _C_ bits
to detect compressed instructions, we can remove all static checks on
__riscv_compressed and dissociate hanlding of misaligned traps and
OpenSBI compilation.
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
We should use MTINST CSR in misaligned load/store emulation whenever
possible to avoid unpriv read in getting trapped instruction. This will
improve preformance on HW having proper implementation of MTINST CSR.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
|
|
The hypervisor v0.5 spec introduces two new CSRs for both M-mode
and HS-mode which need to be considered when redirecting traps
hence this patch.
Signed-off-by: Anup Patel <[email protected]>
|
|
The unpriv APIs can be useful to external firmware and out-of-tree
platform support code.
This patch adds "sbi_" prefix to unpriv load/store APIs and rename
struct riscv_unpriv to struct sbi_trap_info everywhere. We also
place struct sbi_trap_info in sbi/sbi_trap.h so that we can use
it for sbi_trap_redirect() as well.
Overall, this patch will make naming of unpriv APIs consistent
with other OpenSBI APIs.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
We don't need to set VSSTATUS.MXR bit in get_insn() for
unpriv instruction read because MSTATUS.MXR bit applies
to both "Stage1" and "Stage2" page tables.
This also allows us to remove the "virt" parameter of
get_insn() function.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
Current implementation of get_insn() is not suitable for reading
instruction from VS/VU mode because we have to set SSTATUS_MXR bit
in VSSTATUS CSR for reading instruction from VS/VU mode.
This patch extends get_insn() to read instruction from VS/VU mode.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
|
|
We can get a page/access trap when doing unpriv load/store in
get_insn() function because on a SMP system Linux swapper running
on HART A can unmap pages from page table used by HART B.
To tackle this we extend get_insn() implementation so that if
we get trap in get_insn() then we redirect it to S-mode as fetch
page/access fault.
Signed-off-by: Anup Patel <[email protected]>
|
|
Currently, we mandate 'F' and 'D' extension in riscv_fp.h so that
misaligned load/store emulation has access to FP registers.
The above is too restrictive and we should certainly allow compilation
for soft-FP toolchains and explicit PLATFORM_RISCV_ISA not having 'F'
and 'D' extensions.
This patch extends riscv_fp.h and misaligned load/store emulation to
allow compiling OpenSBI without FP support.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Signed-off-by: Atish Patra <[email protected]>
Acked-by: Anup Patel <[email protected]>
|
