| Age | Commit message (Collapse) | Author |
|---|
|
While sbi_pmu_irq_bit() was used to delegate irq to S-mode, LCOFIP usage
was still hardcoded in various places. This led to change the returned
value of sbi_pmu_irq_bit() to be a bit number rather than a bit mask
since it returns an 'int' and we need to obtain the bit number itself to
handle it in the IRQs handlers. Add a similar function to return the
irq mask which can also be used where the mask is required rather than
the bit itself.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
C23 pre-defines bool so we need to gate our defines.
Signed-off-by: Michael Neuling <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Initialize serial drivers first, so messages printed by other drivers do
not need to use the early console buffer.
Suggested-by: Anup Patel <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Add a generic RPMI mailbox client driver which provides a MPXY channel.
Initially, this driver only supports RPMI clock service group but can
be extended to support multiple RPMI service groups.
Signed-off-by: Rahul Pathak <[email protected]>
Co-developed-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
The generic platform can have multiple MPXY drivers so add a simple
FDT based MPXY driver framework.
Signed-off-by: Anup Patel <[email protected]>
|
|
Add RPMI based driver for CPPC register read, write and probe.
Signed-off-by: Subrahmanya Lingappa <[email protected]>
Co-developed-by: Rahul Pathak <[email protected]>
Signed-off-by: Rahul Pathak <[email protected]>
Co-developed-by: Sunil V L <[email protected]>
Signed-off-by: Sunil V L <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
The generic platform can have multiple CPPC drivers so add a simple
FDT based CPPC driver framework.
Signed-off-by: Anup Patel <[email protected]>
|
|
The RPMI HSM service group provides set of routine to query and control
power states of a Hart. Add RPMI based Hart State Management (HSM) driver.
Signed-off-by: Subrahmanya Lingappa <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
The generic platform can have multiple HSM drivers so add a simple
FDT based HSM driver framework.
Signed-off-by: Anup Patel <[email protected]>
|
|
Add an optional resume address to the platform specific hart suspend call.
Signed-off-by: Subrahmanya Lingappa <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
Add RPMI based system suspend driver.
To test this, execute the follwoing in Linux:
$ echo mem > /sys/power/state
To wake up, execute the following command on qemu monitor terminal:
(qemu) system_wakeup
Signed-off-by: Subrahmanya Lingappa <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
The generic platform can have multiple system suspend drivers so add a
simple FDT based system suspend driver framework.
Signed-off-by: Anup Patel <[email protected]>
|
|
Add RPMI based driver for system reset and enable it in the generic
platform defconfig
Signed-off-by: Rahul Pathak <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
The RISC-V Platform Management Interface (RPMI) defines a messaging protocol
and shared memory based transport for bi-directional communication with an
on-chip or external microcontroller.
To support RPMI in OpenSBI, add:
1) The RPMI messaging protocol defines and helper macros
2) A FDT mailbox driver for the RPMI shared memory transport
Signed-off-by: Rahul Pathak <[email protected]>
Co-developed-by: Subrahmanya Lingappa <[email protected]>
Signed-off-by: Subrahmanya Lingappa <[email protected]>
Co-developed-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
As per the updated ISA specification and SBI PMU v3.0, lower 56
bits are available for the platform to implement mhpmeventX
encoding. Implement the PMU raw event V2 support defined in SBI
v3.0 which allows more bits for platforms to encode the raw events.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The reset driver subsystem does not need any extra data, so it can use
`struct fdt_driver` directly. The generic fdt_reset_init() performs a
best-effort initialization of all matching DT nodes. Platform-specific
logic expects exactly one DT node to match a single driver. This is
accomplished by using fdt_driver_init_one() with a local list containing
that one driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
This allows the compiler to generate significantly better code, because
it does not have to maintain either the loop counter or loop limit. Plus
there are half as many symbols to relocate. This also simplifies passing
carray arrays to helper functions.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Now that driver lifecycle is managed from within the SBI irqchip core,
platforms need only to initialize the driver once during cold init.
Remove the remaining platform hooks that are no longer used.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Currently, each platform keeps track of which irqchip driver is in use
and calls its warm init function. Since the generic platform may use
multiple irqchip drivers, it has logic to track an array of drivers.
The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.
For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The per-hart PLIC pointer is not really specific to FDT platforms. Move
it into the main driver and drop the extra wrapper functions.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Move the PLIC save/restore functions inside the driver, so they can be
reused on any platform that needs them. The memory needed to store the
PLIC context is also allocated by the driver. The PM data cannot be
completely encapsulated, as some platforms (including Allwinner D1) need
to program the IRQ enable status to a sideband interrupt controller for
wakeup capability.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
This removes platform-specific arguments to plic_warm_irqchip_init(),
which makes the driver independent from the platform after cold init,
and allows for further refactoring.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Unlike other platforms, Ariane and OpenPiton enable all IRQs by default.
This was described in commit b44e844880d0 ("Add support for Ariane FPGA
SoC") as "due to some issue of the design." Add this workaround behind a
flag in plic_warm_irqchip_init(), so every platform can use the same
warm init function.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Now that the SBI IPI core clears IPIs at warm boot in a generic way,
none of the drivers or platforms use these hooks, and we can remove
them. Platforms need only to initialize the driver once during cold
init. If other hooks are needed in the future, they can be added to
struct sbi_ipi_device.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
sbi_ipi_init() expects the platform warm init function to clear IPIs
on the local hart, but there is already a generic function to do this.
After this change, none of the existing drivers need a warm init
callback.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The default heap size will work for most platforms, but for some
special platforms, the heap is too small to hold all the information
or is too big so that it take too much ram. Introduce configurable
heap should solve this problem and make all generic platforms happy.
Add DT-based heap-size for the generic platform.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Xiang W <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Now that driver lifecycle is managed from within the SBI timer core,
platforms need only to initialize the driver once during cold init.
Remove the remaining platform hooks that are no longer used.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Currently, the platform's timer device is tracked in two places: the
core SBI implementation has `timer_dev`, and the FDT timer layer has
`current_driver`. The latter is used for warm initialization of the
timer device. However, this warm init is not specific to FDT-based
platforms; other platforms call exactly the same functions from the
same point in the boot sequence.
The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.
For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
All callers already have the hartindex available, so this removes a
hartid to hartindex conversion.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
It is possible that the OpenSBI config DT node is present but
the "cold-boot-harts" DT property is not present. In this case,
the fw_platform_coldboot_harts_init() will do nothing which
in-turn causes OpenSBI firmware hang at boot time.
To address the above issue, fallback to the default approach
when the "cold-boot-harts" DT property is not present.
Fixes: 67ce5a763cfb ("platform: generic: Add support for specify coldboot harts in DT")
Signed-off-by: Anup Patel <[email protected]>
|
|
Help tracking the lifecycle of the FDT blob by indicating which parts of
the firmware modify it, and thus invalidate any previously-obtained
offsets or pointers to data inside the blob.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Indicate that this function does not modify the FDT blob, and
deduplicate the call to fdt_get_address().
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Indicate that this function does not modify the FDT blob, and
deduplicate the call to fdt_get_address().
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Several of these override functions access the FDT blob. Explicitly
indicate which callbacks are allowed to modify the FDT blob by passing
the parameter as a possibly-const pointer. This also reduces code size
by deduplicating the call to fdt_get_address().
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Indicate that none of these functions modify the devicetree by
constifying the parameter type.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Indicate that none of these functions modify the devicetree by
constifying the parameter type.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Add a new Andes SBI call to free a PMA entry, and reset the memory
attributes for the corresponding NAPOT region.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Implement a new Andes SBI call, which is to set up a NAPOT region
with given memory attributes.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Add a new Andes SBI call to check whether PPMA is supported by hardware
or not.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Describe Andes PPMA in the config option, and select it for AE350
platform.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The sbi_console_init() does not do any special initialization so
setup serial console device in early_init() so that console prints
work as early as possible.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-By: Himanshu Chauhan <[email protected]>
|
|
We would like to clean any files generated by the carray
scripts by just searching for the filename as the current
make system turns f.carray into f.o. Change to make the
make system turn f.carray into f.carray.o
note, command to go through .mk files changing the .o
in the .mk files is:
find . -type f -name "*.carray" | xargs -t -I fname /bin/bash -x -c ' fn=`basename -s .carray fname`; echo "$fn"; sed -i `dirname fname `/objects.mk -e s/"$fn".o/"$fn".carray.o/g'
Link: https://patchwork.ozlabs.org/project/opensbi/patch/[email protected]/
Reported-by: Ivan Orlov <[email protected]>
Suggested-by: Andrew Jones <[email protected]>
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Like PMP, the behaviors to configure PMA will be different from
RV64 and RV32. RV64 uses two Andes custom CSRs, pmacfg0 and pmacfg2,
but RV32 uses four Andes custom CSRs, pmacfg0 ~ pmacfg3. This patch
adds support to PMA for RV32.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
This patch refines the Andes PMA related code. The main change is
refactor andes_pma_[read|write]_cfg() and andes_pma_[read|write]_addr()
into new functions andes_pma_[read|write]_num().
Also, fix some coding style problems.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The Sophgo CV18XX/SG200X series SoCs have a standard C906
core. Add support for it.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
SG2042 uses an onboard MCU to provide reset function.
Add reset driver to support this onboard MCU.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Canaan Kendryte K230 SoC has T-Head C908 cores inside. The dt-binding has
been merged into the linux kernel [1]. However, it has early version of
C908 core which does not have Sscofpmf and need to use T-Head PMU
extension. Thus, we add a K230 compatible string to thead_generic_match
and set quirk for T-Head PMU.
[1] https://lore.kernel.org/linux-riscv/[email protected]/
Signed-off-by: Yangyu Chen <[email protected]>
Reviewed-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
As Guo Ren said from the kernel mailing list [1], future T-Head CPUs,
including the newer versions of T-Head C908, will feature standard
Sscofpmf extension. For these CPUs, T-Head's implementation of PMU
Overflow Interrupts may not needed anymore. In this case, we shouldn't
apply T-Head PMU for all T-Head CPUs. Thus, this patch separated T-Head PMU
errata.
[1] https://lore.kernel.org/linux-riscv/[email protected]/
Signed-off-by: Yangyu Chen <[email protected]>
Reviewed-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
To make the framework suit all Andes CPUs, change all occurrences of
andes45 to andes.
In addition, we fix some coding style problems and remove an unused
macro in andes.h.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Rename files with the prefix andes45 to andes.
Signed-off-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
