diff options
| author | Bernard Xiong <[email protected]> | 2020-11-13 07:10:16 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-11-13 07:10:16 +0800 |
| commit | 065488e74652806a9f58055d5fbb644fda338ae5 (patch) | |
| tree | 5ae3d0dfd554e986a76951aadbcf7903c8806074 | |
| parent | c5656fbefba2868afe93cac1c043bfc1a674b8bd (diff) | |
| parent | 10fb49318c45653a68555343e33cded10f5b092c (diff) | |
Merge pull request #3956 from xfwangqiang/gcc-fix
[Components]&&[BSP][imxrt]add ethernet configuration for imxrt1064-nxp-evk
33 files changed, 1494 insertions, 711 deletions
diff --git a/bsp/imxrt/imxrt1052-nxp-evk/.config b/bsp/imxrt/imxrt1052-nxp-evk/.config index 22f25240aa..6c073109cc 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/.config +++ b/bsp/imxrt/imxrt1052-nxp-evk/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 @@ -115,12 +118,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y # CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PHY=y CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -128,10 +132,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -145,6 +149,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -156,14 +161,25 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP212 is not set # # AT commands @@ -178,7 +194,6 @@ CONFIG_RT_USING_LIBC=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set @@ -230,13 +245,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set # # security packages @@ -294,6 +308,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -310,7 +325,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set # # miscellaneous packages @@ -354,10 +368,13 @@ CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_LPUART1_RX_USING_DMA is not set # CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART3 is not set # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set # # Board extended module Drivers diff --git a/bsp/imxrt/imxrt1052-nxp-evk/SConstruct b/bsp/imxrt/imxrt1052-nxp-evk/SConstruct index 9e5cd55bc0..f9ddc50fa3 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/SConstruct +++ b/bsp/imxrt/imxrt1052-nxp-evk/SConstruct @@ -67,5 +67,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons # include drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) +# include peripherals +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript'))) + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig index d77cd8d8f5..06a1cee7d4 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig @@ -96,19 +96,41 @@ menu "Onboard Peripheral Drivers" menuconfig BSP_USING_ETH bool "Enable Ethernet" - select PHY_USING_KSZ8081 select RT_USING_NETDEV default n + if BSP_USING_ETH - config PHY_USING_KSZ8081 - bool "i.MX RT1050EVKB uses ksz8081 phy" + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" default y - config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE - bool "Enable the PHY ksz8081 RMII50M mode" - depends on PHY_USING_KSZ8081 - default y + if BSP_USING_PHY + config PHY_DEVICE_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_USING_KSZ8081 + bool "i.MX RT1064EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_RESET_PORT + int "indicate port of reset" + default 1 + + config PHY_RESET_PIN + int "indicate pin of reset" + default 9 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + + endif endif endmenu diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript b/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript index 468395b44d..a338eca9fa 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript @@ -12,10 +12,6 @@ MCUX_Config/pin_mux.c CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1'] -if GetDepend(['PHY_USING_KSZ8081']): - src += Glob('ports/phyksz8081/fsl_phy.c') - CPPPATH += [cwd + '/ports/phyksz8081'] - group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c deleted file mode 100644 index 4197514aa5..0000000000 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_phy.h" -#include <rtthread.h> -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Defines the timeout macro. */ -#define PHY_TIMEOUT_COUNT 0x3FFFFFFU - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the ENET instance from peripheral base address. - * - * @param base ENET peripheral base address. - * @return ENET instance. - */ -extern uint32_t ENET_GetInstance(ENET_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to enet clocks for each instance. */ -extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) -{ - uint32_t bssReg; - uint32_t counter = PHY_TIMEOUT_COUNT; - uint32_t idReg = 0; - status_t result = kStatus_Success; - uint32_t instance = ENET_GetInstance(base); - uint32_t timeDelay; - uint32_t ctlReg = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Set SMI first. */ - CLOCK_EnableClock(s_enetClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - ENET_SetSMI(base, srcClock_Hz, false); - - /* Initialization after PHY stars to work. */ - while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) - { - PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); - counter --; - } - - if (!counter) - { - return kStatus_Fail; - } - - /* Reset PHY. */ - counter = PHY_TIMEOUT_COUNT; - result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); - if (result == kStatus_Success) - { - -#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) - uint32_t data = 0; - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if ( result != kStatus_Success) - { - return result; - } - result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); - if (result != kStatus_Success) - { - return result; - } -#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ - - /* Set the negotiation. */ - result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, - (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | - PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); - if (result == kStatus_Success) - { - result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, - (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); - if (result == kStatus_Success) - { - /* Check auto negotiation complete. */ - while (counter --) - { - result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); - if ( result == kStatus_Success) - { - PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); - if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK)) - { - /* Wait a moment for Phy status stable. */ - for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++) - { - __ASM("nop"); - } - break; - } - } - - if (!counter) - { - return kStatus_PHY_AutoNegotiateFail; - } - } - } - } - } - - return result; -} - -status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) -{ - uint32_t counter; - - /* Clear the SMI interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - /* Starts a SMI write command. */ - ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); - - /* Wait for SMI complete. */ - for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) - { - if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) - { - break; - } - } - - /* Check for timeout. */ - if (!counter) - { - return kStatus_PHY_SMIVisitTimeout; - } - - /* Clear MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - return kStatus_Success; -} - -status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) -{ - assert(dataPtr); - - uint32_t counter; - - /* Clear the MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - /* Starts a SMI read command operation. */ - ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); - - /* Wait for MII complete. */ - for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) - { - if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) - { - break; - } - } - - /* Check for timeout. */ - if (!counter) - { - return kStatus_PHY_SMIVisitTimeout; - } - - /* Get data from MII register. */ - *dataPtr = ENET_ReadSMIData(base); - - /* Clear MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - return kStatus_Success; -} - -status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) -{ - status_t result; - uint32_t data = 0; - - /* Set the loop mode. */ - if (enable) - { - if (mode == kPHY_LocalLoop) - { - if (speed == kPHY_Speed100M) - { - data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; - } - else - { - data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; - } - return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); - } - else - { - /* First read the current status in control register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if (result == kStatus_Success) - { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); - } - } - } - else - { - /* Disable the loop mode. */ - if (mode == kPHY_LocalLoop) - { - /* First read the current status in control register. */ - result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); - if (result == kStatus_Success) - { - data &= ~PHY_BCTL_LOOP_MASK; - return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); - } - } - else - { - /* First read the current status in control one register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if (result == kStatus_Success) - { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); - } - } - } - return result; -} - -status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) -{ - assert(status); - - status_t result = kStatus_Success; - uint32_t data; - - /* Read the basic status register. */ - result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); - if (result == kStatus_Success) - { - if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) - { - /* link down. */ - *status = false; - } - else - { - /* link up. */ - *status = true; - } - } - return result; -} - -status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) -{ - assert(duplex); - - status_t result = kStatus_Success; - uint32_t data, ctlReg; - - /* Read the control two register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); - if (result == kStatus_Success) - { - data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; - if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) - { - /* Full duplex. */ - *duplex = kPHY_FullDuplex; - } - else - { - /* Half duplex. */ - *duplex = kPHY_HalfDuplex; - } - - data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; - if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) - { - /* 100M speed. */ - *speed = kPHY_Speed100M; - } - else - { /* 10M speed. */ - *speed = kPHY_Speed10M; - } - } - - return result; -} diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h deleted file mode 100644 index a1eff6d723..0000000000 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PHY_H_ -#define _FSL_PHY_H_ - -#include "fsl_enet.h" - -/*! - * @addtogroup phy_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief PHY driver version */ -#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - -/*! @brief Defines the PHY registers. */ -#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ -#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ -#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ -#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ -#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ -#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ -#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ - -#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ - -/*! @brief Defines the mask flag in basic control register. */ -#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ -#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ -#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ -#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ -#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ -#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ -#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ - -/*!@brief Defines the mask flag of operation mode in control two register*/ -#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ -#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ -#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ -#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ -#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ -#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ -#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ -#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ -#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ -#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) - -/*! @brief Defines the mask flag in basic status register. */ -#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ -#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ -#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ - -/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ -#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ -#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ -#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ -#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ -#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ - -/*! @brief Defines the PHY status. */ -enum _phy_status -{ - kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ - kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ -}; - -/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ -typedef enum _phy_speed -{ - kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ - kPHY_Speed100M /*!< ENET PHY 100M speed. */ -} phy_speed_t; - -/*! @brief Defines the PHY link duplex. */ -typedef enum _phy_duplex -{ - kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ - kPHY_FullDuplex /*!< ENET PHY full duplex. */ -} phy_duplex_t; - -/*! @brief Defines the PHY loopback mode. */ -typedef enum _phy_loop -{ - kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ - kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ -} phy_loop_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name PHY Driver - * @{ - */ - -/*! - * @brief Initializes PHY. - * - * This function initialize the SMI interface and initialize PHY. - * The SMI is the MII management interface between PHY and MAC, which should be - * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. - * @retval kStatus_Success PHY initialize success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail - */ -status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); - -/*! - * @brief PHY Write function. This function write data over the SMI to - * the specified PHY register. This function is called by all PHY interfaces. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param data The data written to the PHY register. - * @retval kStatus_Success PHY write success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); - -/*! - * @brief PHY Read function. This interface read data over the SMI from the - * specified PHY register. This function is called by all PHY interfaces. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param dataPtr The address to store the data read from the PHY register. - * @retval kStatus_Success PHY read success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); - -/*! - * @brief Enables/disables PHY loopback. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param mode The loopback mode to be enabled, please see "phy_loop_t". - * the two loopback mode should not be both set. when one loopback mode is set - * the other one should be disabled. - * @param speed PHY speed for loopback mode. - * @param enable True to enable, false to disable. - * @retval kStatus_Success PHY loopback success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable); - -/*! - * @brief Gets the PHY link status. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param status The link up or down status of the PHY. - * - true the link is up. - * - false the link is down. - * @retval kStatus_Success PHY get link status success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); - -/*! - * @brief Gets the PHY link speed and duplex. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param speed The address of PHY link speed. - * @param duplex The link duplex of PHY. - * @retval kStatus_Success PHY get link speed and duplex success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PHY_H_ */ diff --git a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h index b2aafbad7b..1ed1ff6671 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h +++ b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h @@ -40,7 +40,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40003 /* RT-Thread Components */ @@ -78,11 +78,9 @@ #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_CPUTIME +#define RT_USING_PHY #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ @@ -95,10 +93,17 @@ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -163,6 +168,7 @@ /* Onboard Peripheral Drivers */ + /* Board extended module Drivers */ diff --git a/bsp/imxrt/imxrt1064-nxp-evk/README.md b/bsp/imxrt/imxrt1064-nxp-evk/README.md index 37a5e3d1dd..e5b51dbe0d 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/README.md +++ b/bsp/imxrt/imxrt1064-nxp-evk/README.md @@ -39,7 +39,7 @@ | :----------------- | :----------: | :------------------------------------- | | USB 转串口 | 支持 | | | SPI Flash | 支持 | | -| 以太网 | 暂不支持 | | +| 以太网 | 支持 | | | SD卡 | 暂不支持 | | | CAN | 暂不支持 | | | **片上外设** | **支持情况** | **备注** | diff --git a/bsp/imxrt/imxrt1064-nxp-evk/SConstruct b/bsp/imxrt/imxrt1064-nxp-evk/SConstruct index 01c823f118..92ab729ed1 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/SConstruct +++ b/bsp/imxrt/imxrt1064-nxp-evk/SConstruct @@ -66,5 +66,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons # include drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) +# include peripherals +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript'))) + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c index 12c9d0df52..1b373138f2 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c @@ -18,6 +18,7 @@ int main(void) { +#ifndef PHY_USING_KSZ8081 /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); @@ -28,6 +29,7 @@ int main(void) rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } +#endif } void reboot(void) diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig index 7bfd46cf4b..5c660b91c7 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig @@ -37,7 +37,49 @@ menu "On-chip Peripheral Drivers" endmenu menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + default n + + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_DEVICE_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_USING_KSZ8081 + bool "i.MX RT1064EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_RESET_PORT + int "indicate port of reset" + default 1 + + config PHY_RESET_PIN + int "indicate pin of reset" + default 9 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + + endif + endif endmenu menu "Board extended module Drivers" diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c b/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c index 88dc4624c3..c26370df1c 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c @@ -1,4 +1,11 @@ /* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* * How to setup clock using clock driver functions: * * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. @@ -15,15 +22,15 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v5.0 +product: Clocks v4.1 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 -processor_version: 5.0.1 +processor_version: 0.0.0 +board: MIMXRT1064-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" -#include "fsl_iomuxc.h" /******************************************************************************* * Definitions @@ -57,35 +64,23 @@ outputs: - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} -- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 264 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2880/11 MHz} - {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} @@ -95,10 +90,10 @@ outputs: settings: - {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} -- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true} -- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '8'} @@ -107,6 +102,7 @@ settings: - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.div, value: '22'} - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} @@ -182,6 +178,77 @@ void BOARD_BootClockRUN(void) while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ @@ -193,8 +260,14 @@ void BOARD_BootClockRUN(void) CLOCK_SetDiv(kCLOCK_IpgDiv, 3); /* Set ARM_PODF. */ CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set PERIPH_CLK2_PODF. */ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); /* Disable PERCLK clock gate. */ CLOCK_DisableClock(kCLOCK_Gpt1); CLOCK_DisableClock(kCLOCK_Gpt1S); @@ -203,6 +276,8 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ @@ -241,9 +316,9 @@ void BOARD_BootClockRUN(void) /* Disable Flexspi2 clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi2); /* Set FLEXSPI2_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 0); /* Set Flexspi2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3); + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); #endif /* Disable CSI clock gate. */ CLOCK_DisableClock(kCLOCK_Csi); @@ -325,9 +400,9 @@ void BOARD_BootClockRUN(void) /* Disable LCDIF clock gate. */ CLOCK_DisableClock(kCLOCK_LcdPixel); /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6); + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 7); + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); /* Set Lcdif pre clock source. */ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); /* Disable SPDIF clock gate. */ @@ -356,85 +431,6 @@ void BOARD_BootClockRUN(void) CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); /* Set Pll3 sw clock source. */ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Set Enet2 output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); - /* Enable Enet2 output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Set lvds1 clock source. */ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); /* Set clock out1 divider. */ @@ -451,26 +447,6 @@ void BOARD_BootClockRUN(void) CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; /* Disable clock out2. */ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET1 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set ENET2 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; } diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript b/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript index 4f8e797f9a..050a6c10bc 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript @@ -13,7 +13,7 @@ MCUX_Config/pin_mux.c CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] -CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'STD=C99', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1'] +CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1'] if rtconfig.CROSS_TOOL == 'keil': CPPDEFINES.append('__FPU_PRESENT=1') diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c index a56282ea00..603cd856c5 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c @@ -12,6 +12,8 @@ #include <rtthread.h> #include "board.h" #include "pin_mux.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" #ifdef BSP_USING_DMA #include "fsl_dmamux.h" @@ -109,6 +111,347 @@ void imxrt_dma_init(void) EDMA_Init(DMA0, &config); } #endif + +#ifdef BSP_USING_LPUART +void imxrt_uart_pins_init(void) +{ +#ifdef BSP_USING_LPUART1 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +#endif +#ifdef BSP_USING_LPUART2 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0x10B0u); + +#endif +#ifdef BSP_USING_LPUART3 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART4 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART5 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART6 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART7 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART8 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0x10B0u); +#endif +} +#endif /* BSP_USING_LPUART */ + +#ifdef BSP_USING_ETH +void imxrt_enet_pins_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/6 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Disabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +} + +#ifndef BSP_USING_PHY +void imxrt_enet_phy_reset_by_gpio(void) +{ + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + GPIO_PinInit(GPIO1, 9, &gpio_config); + GPIO_PinInit(GPIO1, 10, &gpio_config); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 10, 1); + GPIO_WritePinOutput(GPIO1, 9, 0); + rt_thread_delay(100); + GPIO_WritePinOutput(GPIO1, 9, 1); +} +#endif /* BSP_USING_PHY */ + +#endif /* BSP_USING_ETH */ + +#ifdef BSP_USING_PHY +void imxrt_phy_pins_init( void ) +{ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_B0_00 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +} +#endif /* BSP_USING_PHY */ + /** * This function will initial rt1050 board. */ @@ -121,6 +464,18 @@ void rt_hw_board_init() NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); +#ifdef BSP_USING_LPUART + imxrt_uart_pins_init(); +#endif + +#ifdef BSP_USING_ETH + imxrt_enet_pins_init(); +#endif + +#ifdef BSP_USING_PHY + imxrt_phy_pins_init(); +#endif + #ifdef BSP_USING_DMA imxrt_dma_init(); #endif diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/board.h b/bsp/imxrt/imxrt1064-nxp-evk/board/board.h index 692569842b..dd7b7d3e56 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/board.h +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/board.h @@ -45,5 +45,11 @@ extern int heap_end; void rt_hw_board_init(void); +#ifdef BSP_USING_ETH +void imxrt_enet_pins_init(void); +void imxrt_enet_phy_reset_by_gpio(void); + +#endif + #endif diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct index 7b7bf4fbba..f36201c200 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct @@ -66,6 +66,8 @@ #define m_data3_start 0x00000000 ; ITCM 128KB
#define m_data3_size 0x00020000
+#define m_ncache_start 0x81E00000
+#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
@@ -124,7 +126,7 @@ LR_IROM1 m_text_start m_text_size RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
- RW_m_ncache m_data2_start m_data2_size
+ RW_m_ncache m_ncache_start m_ncache_size
{
* (NonCacheable.init)
* (NonCacheable)
diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h b/bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h new file mode 100644 index 0000000000..477987b4e7 --- /dev/null +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-05 zylx The first version for STM32F4xx + * 2019-4-25 misonyo port to IMXRT + */ + +#ifndef SDRAM_PORT_H__ +#define SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) +/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ +#define SDRAM_REGION kSEMC_SDRAM_CS0 +/* CS pin: kSEMC_MUXCSX0/1/2/3 */ +#define SDRAM_CS_PIN kSEMC_MUXCSX0 +/* size(kbyte):32MB = 32*1024*1KBytes */ +#define SDRAM_SIZE ((uint32_t)0x8000) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit +/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ +#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit +/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ +#define SDRAM_CAS_LATENCY kSEMC_LatencyThree + +/* Timing configuration for W9825G6KH */ +/* TRP:precharge to active command time (ns) */ +#define SDRAM_TRP 18 +/* TRCD:active to read/write command delay time (ns) */ +#define SDRAM_TRCD 18 +/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ +#define SDRAM_REFRESH_RECOVERY 67 +/* TWR:write recovery time (ns). */ +#define SDRAM_TWR 12 +/* TRAS:active to precharge command time (ns). */ +#define SDRAM_TRAS 42 +/* TRC time (ns). */ +#define SDRAM_TRC 60 +/* active to active time (ns). */ +#define SDRAM_ACT2ACT 60 +/* refresh time (ns). 64ms */ +#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 + +#endif /* SDRAM_PORT_H__ */ diff --git a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py index eeef72b0c6..9689ac0bcb 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py +++ b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py @@ -48,7 +48,7 @@ if PLATFORM == 'gcc': DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -Xlinker -print-memory-usage' CPATH = '' LPATH = '' @@ -57,8 +57,8 @@ if PLATFORM == 'gcc': AFLAGS += ' -D__STARTUP_CLEAR_BSS' if BUILD == 'debug': - CFLAGS += ' -gdwarf-2' - AFLAGS += ' -gdwarf-2' + CFLAGS += ' -g' + AFLAGS += ' -g' CFLAGS += ' -O0' else: CFLAGS += ' -O2 -Os' diff --git a/bsp/imxrt/libraries/drivers/SConscript b/bsp/imxrt/libraries/drivers/SConscript index c806dada25..c610fcd082 100644 --- a/bsp/imxrt/libraries/drivers/SConscript +++ b/bsp/imxrt/libraries/drivers/SConscript @@ -44,6 +44,9 @@ if GetDepend('BSP_USING_LCD'): if GetDepend('BSP_USING_ETH'): src += ['drv_eth.c'] + +if GetDepend('BSP_USING_PHY'): + src += ['drv_mdio.c'] if GetDepend('BSP_USING_USB_DEVICE'): src += ['drv_usbd.c'] diff --git a/bsp/imxrt/libraries/drivers/drv_eth.c b/bsp/imxrt/libraries/drivers/drv_eth.c index 4558312be8..ecff2bb6ab 100644 --- a/bsp/imxrt/libraries/drivers/drv_eth.c +++ b/bsp/imxrt/libraries/drivers/drv_eth.c @@ -7,6 +7,7 @@ * Date Author Notes * 2017-10-10 Tanek the first version * 2019-5-10 misonyo add DMA TX and RX function + * 2020-10-14 wangqiang use phy device in phy monitor thread */ #include <rtthread.h> @@ -19,7 +20,6 @@ #include "fsl_enet.h" #include "fsl_gpio.h" -#include "fsl_phy.h" #include "fsl_cache.h" #include "fsl_iomuxc.h" #include "fsl_common.h" @@ -537,31 +537,47 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) return NULL; } +#ifdef BSP_USING_PHY +static struct rt_phy_device *phy_dev = RT_NULL; static void phy_monitor_thread_entry(void *parameter) { - phy_speed_t speed; - phy_duplex_t duplex; - bool link = false; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_bool_t link = RT_FALSE; - imxrt_enet_phy_reset_by_gpio(); - - PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); + phy_dev = (struct rt_phy_device *)rt_device_find("rtt-phy"); + if ((RT_NULL == phy_dev) || (RT_NULL == phy_dev->ops)) + { + // TODO print warning information + LOG_E("Can not find phy device called \"rtt-phy\""); + return ; + } + if (RT_NULL == phy_dev->ops->init) + { + LOG_E("phy driver error!"); + return ; + } + rt_phy_status status = phy_dev->ops->init(imxrt_eth_device.enet_base, PHY_DEVICE_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); + if (PHY_STATUS_OK != status) + { + LOG_E("Phy device initialize unsuccessful!\n"); + return ; + } while (1) { - bool new_link = false; - status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link); + rt_bool_t new_link = RT_FALSE; + rt_phy_status status = phy_dev->ops->get_link_status(&new_link); - if ((status == kStatus_Success) && (link != new_link)) + if ((PHY_STATUS_OK == status) && (link != new_link)) { link = new_link; - if (link) // link up + if (link) // link up { - PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, - PHY_ADDRESS, &speed, &duplex); + phy_dev->ops->get_link_speed_duplex(&speed, &duplex); - if (kPHY_Speed10M == speed) + if (PHY_SPEED_10M == speed) { dbg_log(DBG_LOG, "10M\n"); } @@ -570,7 +586,7 @@ static void phy_monitor_thread_entry(void *parameter) dbg_log(DBG_LOG, "100M\n"); } - if (kPHY_HalfDuplex == duplex) + if (PHY_HALF_DUPLEX == duplex) { dbg_log(DBG_LOG, "half dumplex\n"); } @@ -579,8 +595,7 @@ static void phy_monitor_thread_entry(void *parameter) dbg_log(DBG_LOG, "full dumplex\n"); } - if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) - || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) + if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) { imxrt_eth_device.speed = (enet_mii_speed_t)speed; imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; @@ -605,6 +620,7 @@ static void phy_monitor_thread_entry(void *parameter) rt_thread_delay(RT_TICK_PER_SECOND * 2); } } +#endif static int rt_hw_imxrt_eth_init(void) { @@ -657,6 +673,7 @@ static int rt_hw_imxrt_eth_init(void) /* start phy monitor */ { + #ifdef BSP_USING_PHY rt_thread_t tid; tid = rt_thread_create("phy", phy_monitor_thread_entry, @@ -666,6 +683,7 @@ static int rt_hw_imxrt_eth_init(void) 2); if (tid != RT_NULL) rt_thread_startup(tid); + #endif } return state; @@ -673,50 +691,47 @@ static int rt_hw_imxrt_eth_init(void) INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init); #endif -#ifdef RT_USING_FINSH +#if defined(RT_USING_FINSH) && defined(RT_USING_PHY) #include <finsh.h> -void phy_read(uint32_t phyReg) +void phy_read(rt_uint32_t phy_reg) { - uint32_t data; - status_t status; + rt_uint32_t data; - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data); - if (kStatus_Success == status) + rt_phy_status status = phy_dev->ops->read(phy_reg, &data); + if (PHY_STATUS_OK == status) { - rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data); + rt_kprintf("PHY_Read: %02X --> %08X", phy_reg, data); } else { - rt_kprintf("PHY_Read: %02X --> faild", phyReg); + rt_kprintf("PHY_Read: %02X --> faild", phy_reg); } } -void phy_write(uint32_t phyReg, uint32_t data) +void phy_write(rt_uint32_t phy_reg, rt_uint32_t data) { - status_t status; - - status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data); - if (kStatus_Success == status) + rt_phy_status status = phy_dev->ops->write(phy_reg, data); + if (PHY_STATUS_OK == status) { - rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data); + rt_kprintf("PHY_Write: %02X --> %08X\n", phy_reg, data); } else { - rt_kprintf("PHY_Write: %02X --> faild\n", phyReg); + rt_kprintf("PHY_Write: %02X --> faild\n", phy_reg); } } void phy_dump(void) { - uint32_t data; - status_t status; + rt_uint32_t data; + rt_phy_status status; int i; for (i = 0; i < 32; i++) { - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data); - if (kStatus_Success != status) + status = phy_dev->ops->read(i, &data); + if (PHY_STATUS_OK != status) { rt_kprintf("phy_dump: %02X --> faild", i); break; @@ -730,10 +745,11 @@ void phy_dump(void) { rt_kprintf("%02X --> %08X\n", i, data); } - } } +#endif +#if defined(RT_USING_FINSH) && defined(RT_USING_LWIP) void enet_reg_dump(void) { ENET_Type *enet_base = imxrt_eth_device.enet_base; diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.c b/bsp/imxrt/libraries/drivers/drv_mdio.c new file mode 100644 index 0000000000..3e98d57f29 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/drv_mdio.c @@ -0,0 +1,160 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-29 WangQiang the first version + * + */ + +#include <rtthread.h> + +#ifdef BSP_USING_PHY + +#define LOG_TAG "drv.mdio" +#include <drv_log.h> + +#include <rtdevice.h> +#include "drv_mdio.h" + + + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0x3FFFFFFU + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +static rt_bool_t rt_hw_mdio_init(void *bus, rt_uint32_t src_clock_hz) +{ + struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus; + uint32_t instance = ENET_GetInstance((ENET_Type *)(bus_obj->hw_obj)); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + ENET_SetSMI((ENET_Type *)(bus_obj->hw_obj), src_clock_hz, RT_FALSE); + + return RT_TRUE; +} + +static rt_size_t rt_hw_mdio_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + RT_ASSERT(data); + struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus; + + rt_uint32_t counter; + rt_uint32_t *data_ptr = (rt_uint32_t *)data; + + if (4 != size) + { + return 0; + } + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + // return kStatus_PHY_SMIVisitTimeout; + return 0; + } + + /* Get data from MII register. */ + *data_ptr = ENET_ReadSMIData((ENET_Type *)(bus_obj->hw_obj)); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)bus_obj->hw_obj, ENET_EIR_MII_MASK); + + return 4; +} + + +static rt_size_t rt_hw_mdio_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus; + uint32_t counter; + rt_uint32_t *data_ptr = (rt_uint32_t *)data; + + if (4 != size) + { + return 0; + } + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiWriteValidFrame, *data_ptr); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return 0; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK); + + return size; +} + +static struct rt_mdio_bus_ops imxrt_mdio_ops = +{ + .init = rt_hw_mdio_init, + .read = rt_hw_mdio_read, + .write = rt_hw_mdio_write, + .uninit = RT_NULL, +}; + +static rt_mdio_t mdio_bus; + +rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name) +{ + mdio_bus.hw_obj = hw_obj; + mdio_bus.name = name; + mdio_bus.ops = &imxrt_mdio_ops; + return &mdio_bus; +} + +rt_mdio_t *rt_hw_mdio_get(void) +{ + return &mdio_bus; +} + +#endif diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.h b/bsp/imxrt/libraries/drivers/drv_mdio.h new file mode 100644 index 0000000000..a1623cfc2c --- /dev/null +++ b/bsp/imxrt/libraries/drivers/drv_mdio.h @@ -0,0 +1,25 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-29 WangQiang the first version + * + */ + +#ifndef DRV_MDIO_H__ +#define DRV_MDIO_H__ + +#include <rtdevice.h> + +#include "fsl_enet.h" + + +rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name); + +rt_mdio_t *rt_hw_mdio_get(void); + +#endif /*DRV_MDIO_H__*/ diff --git a/bsp/imxrt/libraries/peripherals/SConscript b/bsp/imxrt/libraries/peripherals/SConscript new file mode 100644 index 0000000000..13d040cf2b --- /dev/null +++ b/bsp/imxrt/libraries/peripherals/SConscript @@ -0,0 +1,16 @@ +from building import * + +src = [] +cwd = [] +CPPDEFINES = [] + +cwd = GetCurrentDir() + +if GetDepend('BSP_USING_PHY') and GetDepend('PHY_USING_KSZ8081'): + src += ['phyksz8081.c'] + +path = [cwd] + +group = DefineGroup('Peripherals', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/libraries/peripherals/phyksz8081.c b/bsp/imxrt/libraries/peripherals/phyksz8081.c new file mode 100644 index 0000000000..3735965663 --- /dev/null +++ b/bsp/imxrt/libraries/peripherals/phyksz8081.c @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-14 wangqiang the first version + */ + +#include <rtthread.h> + +#ifdef PHY_USING_KSZ8081 + +#include <rtdevice.h> +#include "drv_gpio.h" +#include "drv_mdio.h" + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ +#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + + + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0x3FFFFFFU + +/* defined the Reset pin, PORT and PIN config by menuconfig */ +#define RESET_PIN GET_PIN(PHY_RESET_PORT, PHY_RESET_PIN) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + + +/******************************************************************************* + * Variables + ******************************************************************************/ +static struct rt_phy_device phy_ksz8081; + +/******************************************************************************* + * Code + ******************************************************************************/ + + + +static inline rt_bool_t read_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t *value) +{ + if (4 != bus->ops->read(bus, addr, reg_id, value, 4)) + { + return RT_FALSE; + } + return RT_TRUE; +} + +static inline rt_bool_t write_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t value) +{ + if (4 != bus->ops->write(bus, addr, reg_id, &value, 4)) + { + return RT_FALSE; + } + return RT_TRUE; +} + +static rt_phy_status rt_phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ + rt_bool_t ret; + rt_phy_status result; + rt_uint32_t counter = PHY_TIMEOUT_COUNT; + rt_uint32_t id_reg = 0; + rt_uint32_t time_delay; + rt_uint32_t bss_reg; + rt_uint32_t ctl_reg = 0; + + // reset phy device by gpio + rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT); + rt_pin_write(RESET_PIN, PIN_LOW); + rt_thread_mdelay(100); + rt_pin_write(RESET_PIN, PIN_HIGH); + + rt_mdio_t *mdio_bus = rt_hw_mdio_register(object, "phy_mdio"); + if (RT_NULL == mdio_bus) + { + return PHY_STATUS_FAIL; + } + phy_ksz8081.bus = mdio_bus; + phy_ksz8081.addr = phy_addr; + ret = mdio_bus->ops->init(mdio_bus, src_clock_hz); + if ( !ret ) + { + return PHY_STATUS_FAIL; + } + + /* Initialization after PHY stars to work. */ + while ((id_reg != PHY_CONTROL_ID1) && (counter != 0)) + { + phy_ksz8081.ops->read(PHY_ID1_REG, &id_reg); + counter--; + } + + if (!counter) + { + return PHY_STATUS_FAIL; + } + + /* Reset PHY. */ + counter = PHY_TIMEOUT_COUNT; + result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (PHY_STATUS_OK == result) + { + #if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) + rt_uint32_t data = 0; + result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data); + if (PHY_STATUS_FAIL == result) + { + return PHY_STATUS_FAIL; + } + result = phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); + if (PHY_STATUS_FAIL == result) + { + return PHY_STATUS_FAIL; + } + #endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ + + /* Set the negotiation. */ + result = phy_ksz8081.ops->write(PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (PHY_STATUS_OK == result) + { + result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (PHY_STATUS_OK == result) + { + /* Check auto negotiation complete. */ + while (counter--) + { + result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &bss_reg); + if (PHY_STATUS_OK == result) + { + phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg); + if (((bss_reg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctl_reg & PHY_LINK_READY_MASK)) + { + /* Wait a moment for Phy status stable. */ + for (time_delay = 0; time_delay < PHY_TIMEOUT_COUNT; time_delay++) + { + __ASM("nop"); + } + break; + } + } + + if (!counter) + { + return PHY_STATUS_FAIL; + } + } + } + } + } + + return PHY_STATUS_OK; +} + + +static rt_phy_status rt_phy_read(rt_uint32_t reg, rt_uint32_t *data) +{ + rt_mdio_t *mdio_bus = phy_ksz8081.bus; + rt_uint32_t device_id = phy_ksz8081.addr; + + if (read_reg(mdio_bus, device_id, reg, data)) + { + return PHY_STATUS_OK; + } + return PHY_STATUS_FAIL; +} + +static rt_phy_status rt_phy_write(rt_uint32_t reg, rt_uint32_t data) +{ + rt_mdio_t *mdio_bus = phy_ksz8081.bus; + rt_uint32_t device_id = phy_ksz8081.addr; + + if (write_reg(mdio_bus, device_id, reg, data)) + { + return PHY_STATUS_OK; + } + return PHY_STATUS_FAIL; +} + +static rt_phy_status rt_phy_loopback(rt_uint32_t mode, rt_uint32_t speed, rt_bool_t enable) +{ + rt_uint32_t data = 0; + rt_phy_status result; + + /* Set the loop mode. */ + if (enable) + { + if (PHY_LOCAL_LOOP == mode) + { + if (PHY_SPEED_100M == speed) + { + data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + else + { + data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, data); + } + else + { + /* First read the current status in control register. */ + result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data); + if (PHY_STATUS_OK == result) + { + return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (PHY_LOCAL_LOOP == mode) + { + /* First read the current status in control register. */ + result = phy_ksz8081.ops->read(PHY_BASICCONTROL_REG, &data); + if (PHY_STATUS_OK == result) + { + data &= ~PHY_BCTL_LOOP_MASK; + return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data); + if (PHY_STATUS_OK == result) + { + return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +static rt_phy_status get_link_status(rt_bool_t *status) +{ + rt_phy_status result; + rt_uint32_t data; + + /* Read the basic status register. */ + result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &data); + if (PHY_STATUS_OK == result) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = RT_FALSE; + } + else + { + /* link up. */ + *status = RT_TRUE; + } + } + return result; +} +static rt_phy_status get_link_speed_duplex(rt_uint32_t *speed, rt_uint32_t *duplex) +{ + rt_phy_status result = PHY_STATUS_OK; + rt_uint32_t data, ctl_reg; + + /* Read the control two register. */ + result = phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg); + if (PHY_STATUS_OK == result) + { + data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* Full duplex. */ + *duplex = PHY_FULL_DUPLEX; + } + else + { + /* Half duplex. */ + *duplex = PHY_HALF_DUPLEX; + } + + data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* 100M speed. */ + *speed = PHY_SPEED_100M; + } + else + { /* 10M speed. */ + *speed = PHY_SPEED_10M; + } + } + + return result; +} + +static struct rt_phy_ops phy_ops = +{ + .init = rt_phy_init, + .read = rt_phy_read, + .write = rt_phy_write, + .loopback = rt_phy_loopback, + .get_link_status = get_link_status, + .get_link_speed_duplex = get_link_speed_duplex, +}; + +static int rt_phy_ksz8081_register( void ) +{ + phy_ksz8081.ops = &phy_ops; + rt_hw_phy_register(&phy_ksz8081, "rtt-phy"); + return 1; +} + +INIT_DEVICE_EXPORT(rt_phy_ksz8081_register); + + + +#endif /* PHY_USING_KSZ8081 */ diff --git a/bsp/imxrt/tools/sdk_dist.py b/bsp/imxrt/tools/sdk_dist.py index 89b7da4356..b663628504 100644 --- a/bsp/imxrt/tools/sdk_dist.py +++ b/bsp/imxrt/tools/sdk_dist.py @@ -21,3 +21,6 @@ def dist_do_building(BSP_ROOT, dist_dir=None): print("=> copy bsp drivers") bsp_copy_files(os.path.join(library_path, 'drivers'), os.path.join(library_dir, 'drivers')) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + + print("=> copy bsp peripherals") + bsp_copy_files(os.path.join(library_path, 'peripherals'), os.path.join(library_dir, 'peripherals')) diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 457b8751fe..db4455160e 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -103,6 +103,10 @@ if RT_USING_I2C endif endif +config RT_USING_PHY + bool "Using ethernet phy device drivers" + default n + config RT_USING_PIN bool "Using generic GPIO device drivers" default y diff --git a/components/drivers/include/drivers/phy.h b/components/drivers/include/drivers/phy.h new file mode 100644 index 0000000000..2d1ad9f91f --- /dev/null +++ b/components/drivers/include/drivers/phy.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-14 wangqiang the first version + */ + +#ifndef __PHY_H__ +#define __PHY_H__ + +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Defines the PHY link speed. This is align with the speed for MAC. */ +enum phy_speed +{ + PHY_SPEED_10M = 0U, /* PHY 10M speed. */ + PHY_SPEED_100M /* PHY 100M speed. */ +}; + +/* Defines the PHY link duplex. */ +enum phy_duplex +{ + PHY_HALF_DUPLEX = 0U, /* PHY half duplex. */ + PHY_FULL_DUPLEX /* PHY full duplex. */ +}; + +/*! @brief Defines the PHY loopback mode. */ +enum phy_loop +{ + PHY_LOCAL_LOOP = 0U, /* PHY local loopback. */ + PHY_REMOTE_LOOP /* PHY remote loopback. */ +}; + + +struct rt_phy_msg +{ + rt_uint32_t reg; + rt_uint32_t value; +}; + +typedef struct rt_phy_msg rt_phy_msg_t; + + +struct rt_phy_device +{ + struct rt_device parent; + struct rt_mdio_bus *bus; + rt_uint32_t addr; + struct rt_phy_ops *ops; +}; + +typedef struct rt_phy_device rt_phy_t; + + +enum { + PHY_STATUS_OK = 0, + PHY_STATUS_FAIL, + PHY_STATUS_TIMEOUT, +}; + +typedef rt_int32_t rt_phy_status; + +struct rt_phy_ops +{ + rt_phy_status (*init)(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz); + rt_phy_status (*read)(rt_uint32_t reg, rt_uint32_t *data); + rt_phy_status (*write)(rt_uint32_t reg, rt_uint32_t data); + rt_phy_status (*loopback)(rt_uint32_t mode, rt_uint32_t speed, rt_bool_t enable); + rt_phy_status (*get_link_status)(rt_bool_t *status); + rt_phy_status (*get_link_speed_duplex)(rt_uint32_t *speed, rt_uint32_t *duplex); +}; + +rt_err_t rt_hw_phy_register(struct rt_phy_device *phy, const char *name); + +#ifdef __cplusplus +} +#endif + +#endif /* __PHY_H__*/ diff --git a/components/drivers/include/drivers/phy_mdio.h b/components/drivers/include/drivers/phy_mdio.h new file mode 100644 index 0000000000..d978ec2984 --- /dev/null +++ b/components/drivers/include/drivers/phy_mdio.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-14 wangqiang the first version + */ + +#ifndef __MDIO_H__ +#define __MDIO_H__ + +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + + +struct rt_mdio_bus_ops +{ + rt_bool_t (*init)(void *bus, rt_uint32_t src_clock_hz); + rt_size_t (*read)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); + rt_size_t (*write)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); + rt_bool_t (*uninit)(void *bus); +}; + +struct rt_mdio_bus +{ + void *hw_obj; + char *name; + struct rt_mdio_bus_ops *ops; +}; + +typedef struct rt_mdio_bus rt_mdio_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index f54290097c..f0fa2f5b4a 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -69,6 +69,11 @@ extern "C" { #endif /* RT_USING_I2C_BITOPS */ #endif /* RT_USING_I2C */ +#ifdef RT_USING_PHY +#include "drivers/phy.h" +#include "drivers/phy_mdio.h" +#endif /* RT_USING_PHY */ + #ifdef RT_USING_SDIO #include "drivers/mmcsd_core.h" #include "drivers/sd.h" diff --git a/components/drivers/phy/SConscript b/components/drivers/phy/SConscript new file mode 100644 index 0000000000..ec12ed24c2 --- /dev/null +++ b/components/drivers/phy/SConscript @@ -0,0 +1,8 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd + '/../include'] +group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_PHY'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/drivers/phy/phy.c b/components/drivers/phy/phy.c new file mode 100644 index 0000000000..3ed4a1a265 --- /dev/null +++ b/components/drivers/phy/phy.c @@ -0,0 +1,78 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-27 wangqiang first version + */ + +#include <rthw.h> +#include <rtthread.h> +#include <rtdevice.h> + +#define DBG_TAG "PHY" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + + +static rt_size_t phy_device_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t count) +{ + struct rt_phy_device *phy = (struct rt_phy_device *)dev->user_data; + struct rt_phy_msg *msg = (struct rt_phy_msg *)buffer; + return phy->bus->ops->read(phy->bus, phy->addr, msg->reg, &(msg->value), 4); +} +static rt_size_t phy_device_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t count) +{ + struct rt_phy_device *phy = (struct rt_phy_device *)dev->user_data; + struct rt_phy_msg *msg = (struct rt_phy_msg *)buffer; + return phy->bus->ops->write(phy->bus, phy->addr, msg->reg, &(msg->value), 4); +} + + + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops phy_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + phy_device_read, + phy_device_write, + RT_NULL, +}; +#endif + +/* +* phy device register +*/ +rt_err_t rt_hw_phy_register(struct rt_phy_device *phy, const char *name) +{ + rt_err_t ret; + struct rt_device *device; + + device = &(phy->parent); + + device->type = RT_Device_Class_PHY; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + device->ops = phy_ops; +#else + device->init = NULL; + device->open = NULL; + device->close = NULL; + device->read = phy_device_read; + device->write = phy_device_write; + device->control = NULL; +#endif + device->user_data = phy; + + /* register a character device */ + ret = rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); + + return ret; +} diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index d764ea4231..afbda59e90 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -821,6 +821,7 @@ static char *const device_type_str[] = "Miscellaneous Device", "Sensor Device", "Touch Device", + "Phy Device", "Unknown" }; diff --git a/include/rtdef.h b/include/rtdef.h index 0690371c6d..e4ddbd37d3 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -871,6 +871,7 @@ enum rt_device_class_type RT_Device_Class_Miscellaneous, /**< Miscellaneous device */ RT_Device_Class_Sensor, /**< Sensor device */ RT_Device_Class_Touch, /**< Touch device */ + RT_Device_Class_PHY, /**< PHY device */ RT_Device_Class_Unknown /**< unknown device */ }; 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