diff options
| author | zhaohengbo <[email protected]> | 2018-12-15 20:25:43 +0800 |
|---|---|---|
| committer | zhaohengbo <[email protected]> | 2018-12-15 20:25:43 +0800 |
| commit | 0d1cc3565ab1b1dbda66af516389c2ee600bdbf4 (patch) | |
| tree | 5c6236fe964fa0de97d9a13ce5362775744fa1a3 | |
| parent | afcd8b452114d3ba3ed72d6d143942da7d8a30f4 (diff) | |
| parent | c72dc1a7e5493c9f6af4a221b27499e2f00e2620 (diff) | |
Merge remote-tracking branch 'upstream/master'
| -rw-r--r-- | libcpu/arm/cortex-m0/cpuport.c | 19 | ||||
| -rw-r--r-- | libcpu/risc-v/e310/interrupt_gcc.S | 4 | ||||
| -rw-r--r-- | libcpu/risc-v/rv32m1/interrupt_gcc.S | 4 |
3 files changed, 23 insertions, 4 deletions
diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c index f5ff8ec113..5d36fa11fe 100644 --- a/libcpu/arm/cortex-m0/cpuport.c +++ b/libcpu/arm/cortex-m0/cpuport.c @@ -114,3 +114,22 @@ void rt_hw_hard_fault_exception(struct exception_stack_frame *contex) while (1); } + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED00) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk); +} diff --git a/libcpu/risc-v/e310/interrupt_gcc.S b/libcpu/risc-v/e310/interrupt_gcc.S index 297851d71e..1eac7af90a 100644 --- a/libcpu/risc-v/e310/interrupt_gcc.S +++ b/libcpu/risc-v/e310/interrupt_gcc.S @@ -69,9 +69,9 @@ trap_entry: /* need to switch new thread */ la s0, rt_thread_switch_interrupt_flag - LOAD s2, 0(s0) + lw s2, 0(s0) beqz s2, spurious_interrupt - STORE zero, 0(s0) + sw zero, 0(s0) csrr a0, mepc STORE a0, 0 * REGBYTES(sp) diff --git a/libcpu/risc-v/rv32m1/interrupt_gcc.S b/libcpu/risc-v/rv32m1/interrupt_gcc.S index d74cf441bc..eacf667c67 100644 --- a/libcpu/risc-v/rv32m1/interrupt_gcc.S +++ b/libcpu/risc-v/rv32m1/interrupt_gcc.S @@ -69,10 +69,10 @@ IRQ_Handler: /* need to switch new thread */ la s0, rt_thread_switch_interrupt_flag - LOAD s2, 0(s0) + lw s2, 0(s0) beqz s2, spurious_interrupt /* clear switch interrupt flag */ - STORE zero, 0(s0) + sw zero, 0(s0) csrr a0, mepc STORE a0, 0 * REGBYTES(sp) |