diff options
| author | tanek liang <[email protected]> | 2017-06-14 17:07:08 +0800 |
|---|---|---|
| committer | tanek liang <[email protected]> | 2017-06-14 17:07:08 +0800 |
| commit | 1d6c38f42fb86587888af3cae083d247fa2ff437 (patch) | |
| tree | def745efdf1b4db21015c2e99ef76667e679fd23 | |
| parent | df40819b4b636172cb89263454fc76b630f5a910 (diff) | |
[bsp] remove RT_ASSERT() because UART not work now
| -rw-r--r-- | bsp/stm32l072/board/board.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c index 80c7946a04..92411be737 100644 --- a/bsp/stm32l072/board/board.c +++ b/bsp/stm32l072/board/board.c @@ -68,10 +68,7 @@ static void RCC_Configuration(void) OscInit.PLL.PLLDIV = RCC_PLLDIV_2; OscInit.PLL.PLLMUL = RCC_PLLMUL_4; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; - if (HAL_RCC_OscConfig(&OscInit) != HAL_OK) - { - RT_ASSERT(RT_NULL); - } + HAL_RCC_OscConfig(&OscInit); /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ @@ -84,10 +81,7 @@ static void RCC_Configuration(void) ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1; ClkInit.APB1CLKDivider = RCC_HCLK_DIV1; ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK) - { - RT_ASSERT(RT_NULL); - } + HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1); } #ifdef PRINT_RCC_FREQ_INFO |