[bsp][nxp]support imxrt1180-evk board gpio and LPUART, Serial V2, DMA (V2) (#11489)

* support gpio and LPUART, Serial V2, DMA (V2) * remove unused ci comment workflows * fix: correct YAML indentation on line 12 in ci workflow files * [bsp][nxp]support imxrt1180-evk board gpio and LPUART, Serial V2, DMA V2 * fix: address review feedback - revert CI/drv_uart.c/dev_serial.c, remove drv_uart_v2.h, use drv_uart.h instead * revert: remove framework file changes per review feedback * fix: remove unused variable 'value' in imxrt_pin_read * fix: remove trailing whitespace in pin_mux.c
author: shannon2000 <[email protected]> 2026-07-20 09:08:53 +0800
committer: GitHub <[email protected]> 2026-07-20 09:08:53 +0800
commit: 247f540f6bf5fd182f0426d719f3902bdd885fa5 (patch)
tree: 156727a07262a6cd62e9341829834e2ae7bfe532
parent: 23c05e48a1d61b72096b5e6f5ceb0c26b7da9b80 (diff)
13 files changed, 5099 insertions, 140 deletions
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config
index 9a55fe3218..d86bd16aed 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config
@@ -238,10 +238,11 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_USING_SERIAL_V1=y
-# CONFIG_RT_USING_SERIAL_V2 is not set
-# CONFIG_RT_SERIAL_USING_DMA is not set
-CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set
+CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_SERIAL_BYPASS is not set
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_CLOCK_TIME is not set
@@ -273,6 +274,7 @@ CONFIG_RT_USING_ADC=y
 # CONFIG_RT_USING_BLK is not set
 # CONFIG_RT_USING_REGULATOR is not set
 # CONFIG_RT_USING_POWER_SUPPLY is not set
+
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_CHERRYUSB is not set
 # end of Device Drivers
@@ -1469,15 +1471,18 @@ CONFIG_BSP_USING_DMA=y
 CONFIG_BSP_USING_LPADC=y
 CONFIG_BSP_USING_LPADC1=y
 CONFIG_BSP_LPADC1_USING_DMA=y
-# CONFIG_BSP_USING_GPIO is not set
+CONFIG_BSP_USING_GPIO=y
 # CONFIG_BSP_USING_RTC is not set
 # CONFIG_BSP_USING_USB is not set
 # CONFIG_BSP_USING_SDIO is not set
 CONFIG_BSP_USING_LPUART=y
 CONFIG_BSP_USING_LPUART1=y
-# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
-# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
-# CONFIG_BSP_USING_LPUART3 is not set
+CONFIG_BSP_LPUART1_RX_USING_DMA=y
+CONFIG_BSP_LPUART1_RX_DMA_CHANNEL=0
+CONFIG_BSP_LPUART1_TX_USING_DMA=y
+CONFIG_BSP_LPUART1_TX_DMA_CHANNEL=1
+# CONFIG_BSP_USING_LPUART10 is not set
+# CONFIG_BSP_USING_LPUART12 is not set
 # CONFIG_BSP_USING_CAN is not set
 # CONFIG_BSP_USING_FLEXSPI is not set
 # end of On-chip Peripheral Drivers
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c
index db33aa290d..1393d109b8 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c
@@ -12,14 +12,21 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <drv_gpio.h>
-#include <fsl_rgpio.h>
+
+#define LED_PIN GET_PIN(4, 27)
 
 int main(void)
 {
     rt_kprintf("MIMXRT1180_CM33 Hello_World\r\n");
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
 
     while (1)
     {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
 }
+
+
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig
index f3ca407aa7..6984824525 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig
@@ -118,34 +118,62 @@ menu "On-chip Peripheral Drivers"
                         int "Set LPUART1 TX DMA channel (0-32)"
                         default 1
 
-            config BSP_USING_LPUART3
-                bool "Enable LPUART3"
-                default n
+             config BSP_USING_LPUART10
+                 bool "Enable LPUART10"
+                 default n
 
-                config BSP_LPUART3_RX_USING_DMA
-                    bool "Enable LPUART3 RX DMA"
-                    depends on BSP_USING_LPUART3
-                    select BSP_USING_DMA
-                    select RT_SERIAL_USING_DMA
-                    default n
+                 config BSP_LPUART10_RX_USING_DMA
+                     bool "Enable LPUART10 RX DMA"
+                     depends on BSP_USING_LPUART10
+                     select BSP_USING_DMA
+                     select RT_SERIAL_USING_DMA
+                     default n
 
-                    config BSP_LPUART3_RX_DMA_CHANNEL
-                        depends on BSP_LPUART3_RX_USING_DMA
-                        int "Set LPUART3 RX DMA channel (0-32)"
-                        default 0
+                     config BSP_LPUART10_RX_DMA_CHANNEL
+                         depends on BSP_LPUART10_RX_USING_DMA
+                         int "Set LPUART10 RX DMA channel (0-32)"
+                         default 0
 
-                config BSP_LPUART3_TX_USING_DMA
-                    bool "Enable LPUART3 TX DMA"
-                    depends on BSP_USING_LPUART3
-                    select BSP_USING_DMA
-                    select RT_SERIAL_USING_DMA
-                    default n
+                 config BSP_LPUART10_TX_USING_DMA
+                     bool "Enable LPUART10 TX DMA"
+                     depends on BSP_USING_LPUART10
+                     select BSP_USING_DMA
+                     select RT_SERIAL_USING_DMA
+                     default n
 
-                    config BSP_LPUART3_TX_DMA_CHANNEL
-                        depends on BSP_LPUART3_TX_USING_DMA
-                        int "Set LPUART3 TX DMA channel (0-32)"
-                        default 1
-        endif
+                     config BSP_LPUART10_TX_DMA_CHANNEL
+                         depends on BSP_LPUART10_TX_USING_DMA
+                         int "Set LPUART10 TX DMA channel (0-32)"
+                         default 1
+
+             config BSP_USING_LPUART12
+                 bool "Enable LPUART12"
+                 default n
+
+                 config BSP_LPUART12_RX_USING_DMA
+                     bool "Enable LPUART12 RX DMA"
+                     depends on BSP_USING_LPUART12
+                     select BSP_USING_DMA
+                     select RT_SERIAL_USING_DMA
+                     default n
+
+                     config BSP_LPUART12_RX_DMA_CHANNEL
+                         depends on BSP_LPUART12_RX_USING_DMA
+                         int "Set LPUART12 RX DMA channel (0-32)"
+                         default 2
+
+                 config BSP_LPUART12_TX_USING_DMA
+                     bool "Enable LPUART12 TX DMA"
+                     depends on BSP_USING_LPUART12
+                     select BSP_USING_DMA
+                     select RT_SERIAL_USING_DMA
+                     default n
+
+                     config BSP_LPUART12_TX_DMA_CHANNEL
+                         depends on BSP_LPUART12_TX_USING_DMA
+                         int "Set LPUART12 TX DMA channel (0-32)"
+                         default 3
+         endif
 
         menuconfig BSP_USING_I2C
             bool "Enable I2C"
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c
index 9756b7a864..ccaa04f2bb 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c
@@ -26,10 +26,10 @@ processor_version: 0.15.9
 #include "pin_mux.h"
 
 /* FUNCTION ************************************************************************************************************
- * 
+ *
  * Function Name : BOARD_InitBootPins
  * Description   : Calls initialization functions.
- * 
+ *
  * END ****************************************************************************************************************/
 void BOARD_InitBootPins(void) {
     BOARD_InitPins();
@@ -57,75 +57,69 @@ void BOARD_InitPins(void) {
   CLOCK_EnableClock(kCLOCK_Iomuxc1);          /* Turn on LPCG: LPCG is ON. */
   CLOCK_EnableClock(kCLOCK_Iomuxc2);          /* Turn on LPCG: LPCG is ON. */
 
-//   /* GPIO configuration on GPIO_AD_27 (pin M16) */
-//   rgpio_pin_config_t gpio4_pinM16_config = {
-//       .pinDirection = kRGPIO_DigitalOutput,
-//       .outputLogic = 1U,
-//   };
-//   /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */
-//   RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config);
-
-//   IOMUXC_SetPinMux(
-//       IOMUXC_GPIO_AD_27_GPIO4_IO27,           /* GPIO_AD_27 is configured as GPIO4_IO27 */
-//       0U);      
   IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AON_08_LPUART1_TX,          /* GPIO_AON_08 is configured as LPUART1_TX */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+      IOMUXC_GPIO_AON_08_LPUART1_TX,
+      0U);
   IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AON_09_LPUART1_RX,          /* GPIO_AON_09 is configured as LPUART1_RX */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+      IOMUXC_GPIO_AON_09_LPUART1_RX,
+      0U);
   IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AON_08_LPUART1_TX,          /* GPIO_AON_08 PAD functional properties : */
-      0x02U);                                 /* Slew Rate Field: Fast Slew Rate
-                                                 Drive Strength Field: high driver
-                                                 Pull / Keep Select Field: Pull Disable, Highz
-                                                 Pull Up / Down Config. Field: Weak pull down
-                                                 Open Drain Field: Disabled */
+      IOMUXC_GPIO_AON_08_LPUART1_TX,
+      0x02U);
   IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AON_09_LPUART1_RX,          /* GPIO_AON_09 PAD functional properties : */
-      0x02U);                                 /* Slew Rate Field: Fast Slew Rate
-                                                 Drive Strength Field: high driver
-                                                 Pull / Keep Select Field: Pull Disable, Highz
-                                                 Pull Up / Down Config. Field: Weak pull down
-                                                 Open Drain Field: Disabled */
+      IOMUXC_GPIO_AON_09_LPUART1_RX,
+      0x02U);
 
   IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AON_16_LPI2C2_SCL,          /* GPIO_AON_16 is configured as LPI2C2_SCL */
-      1U);                                    /* Software Input On Field: Force input path of pad GPIO_AON_16 */
+      IOMUXC_GPIO_AD_32_LPUART10_TX,
+      0U);
   IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AON_15_LPI2C2_SDA,          /* GPIO_AON_15 is configured as LPI2C2_SDA */
-      1U);                                    /* Software Input On Field: Force input path of pad GPIO_AON_15 */
+      IOMUXC_GPIO_AD_33_LPUART10_RX,
+      0U);
   IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AON_16_LPI2C2_SCL,          /* GPIO_AON_16 PAD functional properties : */
-      0x1DU);                                 /* Slew Rate Field: Slow Slew Rate
-                                                 Pull Enable Field: Pull Enable
-                                                 Pull Up / Down Config. Field: Weak pull up
-                                                 Open Drain Field: Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AON_15_LPI2C2_SDA,          /* GPIO_AON_15 PAD functional properties : */
-      0x1DU);                                 /* Slew Rate Field: Slow Slew Rate
-                                                 Pull Enable Field: Pull Enable
-                                                 Pull Up / Down Config. Field: Weak pull up
-                                                 Open Drain Field: Enabled */
+      IOMUXC_GPIO_AD_32_LPUART10_TX,
+      0x02U);
+      IOMUXC_GPIO_AD_33_LPUART10_RX,
+      0x02U);
 
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_18_LPI2C3_SCL,           /* GPIO_AD_18 is configured as LPI2C3_SCL */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_19_LPI2C3_SDA,           /* GPIO_AD_19 is configured as LPI2C3_SDA */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AD_18_LPI2C3_SCL,           /* GPIO_AD_18 PAD functional properties : */
-      0x1DU);                                 /* Slew Rate Field: Slow Slew Rate
-                                                 Pull Enable Field: Pull Enable
-                                                 Pull Up / Down Config. Field: Weak pull up
-                                                 Open Drain Field: Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AD_19_LPI2C3_SDA,           /* GPIO_AD_19 PAD functional properties : */
-      0x1DU);                                 /* Slew Rate Field: Slow Slew Rate
-                                                 Pull Enable Field: Pull Enable
-                                                 Pull Up / Down Config. Field: Weak pull up
-                                                 Open Drain Field: Enabled */
+      IOMUXC_SetPinMux(
+          IOMUXC_GPIO_AON_19_LPUART12_TX,
+          0U);
+      IOMUXC_SetPinMux(
+          IOMUXC_GPIO_AON_20_LPUART12_RX,
+          0U);
+      IOMUXC_SetPinConfig(
+          IOMUXC_GPIO_AON_19_LPUART12_TX,
+          0x02U);
+      IOMUXC_SetPinConfig(
+          IOMUXC_GPIO_AON_20_LPUART12_RX,
+          0x02U);
+
+      IOMUXC_SetPinMux(
+          IOMUXC_GPIO_AON_16_LPI2C2_SCL,
+          1U);
+      IOMUXC_SetPinMux(
+          IOMUXC_GPIO_AON_15_LPI2C2_SDA,
+          1U);
+      IOMUXC_SetPinConfig(
+          IOMUXC_GPIO_AON_16_LPI2C2_SCL,
+          0x1DU);
+      IOMUXC_SetPinConfig(
+          IOMUXC_GPIO_AON_15_LPI2C2_SDA,
+          0x1DU);
+
+      IOMUXC_SetPinMux(
+          IOMUXC_GPIO_AD_18_LPI2C3_SCL,
+          0U);
+      IOMUXC_SetPinMux(
+          IOMUXC_GPIO_AD_19_LPI2C3_SDA,
+          0U);
+      IOMUXC_SetPinConfig(
+          IOMUXC_GPIO_AD_18_LPI2C3_SCL,
+          0x1DU);
+      IOMUXC_SetPinConfig(
+          IOMUXC_GPIO_AD_19_LPI2C3_SDA,
+          0x1DU);
 }
 
 void BOARD_InitLeds(void) {
@@ -142,7 +136,7 @@ void BOARD_InitLeds(void) {
 
   IOMUXC_SetPinMux(
       IOMUXC_GPIO_AD_27_GPIO4_IO27,           /* GPIO_AD_27 is configured as GPIO4_IO27 */
-      0U);      
+      0U);
 }
 
 
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c
index eab523dd08..c1b909fc8a 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c
@@ -1269,6 +1269,10 @@ void rt_hw_board_init()
     rt_components_board_init();
 #endif
 
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
@@ -1278,8 +1282,6 @@ void rt_hw_board_init()
     rt_kprintf("Heap: 0x%08x - 0x%08x (Size: %d bytes)\n",
                HEAP_BEGIN, HEAP_END,
                (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN);
-
-    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 
 }
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf
index 08a0efca76..5473f23127 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf
@@ -78,7 +78,7 @@
 #if defined(__heap_size__)
   #define heap_size                    __heap_size__
 #else
-  #define heap_size                    0x04000
+  #define heap_size                    0x20000
 #endif
 
 /* Target specific definition, code & data allocation */
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx
new file mode 100644
index 0000000000..2d4e331b3a
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx
@@ -0,0 +1,1204 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp; *.cc; *.cxx</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>33000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
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diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvprojx
new file mode 100644
index 0000000000..5e2b92bec9
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvprojx
@@ -0,0 +1,2221 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6220000::V6.22::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MIMXRT1189CVM8C:cm33</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>NXP.MIMXRT1189_DFP.26.03.00</PackID>
+          <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
+          <Cpu>CPUTYPE("Cortex-M33") FPU3(SFPU) TZ DSP ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:MIMXRT1189CVM8B$fsl_device_registers.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:MIMXRT1189CVM8B$MIMXRT1189_cm33.xml</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMV8M.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM33</SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
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+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
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+            <AdsLtoi>0</AdsLtoi>
+            <AdsLsun>0</AdsLsun>
+            <AdsLven>0</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M33"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>0</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <nBranchProt>0</nBranchProt>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>0</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
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+              </Ocm3>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x1000000</Size>
+              </OCR_RVCT1>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x20240000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x202c0000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
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+                <Type>0</Type>
+                <StartAddress>0x1ffe0000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>2</Optim>
+            <oTime>0</oTime>
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+            <wLevel>3</wLevel>
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+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
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+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>-fno-common  -fdata-sections  -fno-builtin  -mthumb</MiscControls>
+              <Define>ARM_MATH_CM33, NDEBUG, __RTTHREAD__, XIP_EXTERNAL_FLASH=1, RT_USING_ARMLIBC, CPU_MIMXRT1189CVM8C_cm33, XIP_BOOT_HEADER_ENABLE=1, MCUXPRESSO_SDK, MCUX_META_BUILD, RT_USING_LIBC, MIMXRT1189_cm33_SERIES, __CLK_TCK=RT_TICK_PER_SECOND, XIP_BOOT_HEADER_DCD_ENABLE=1, __STDC_LIMIT_MACROS</Define>
+              <Undefine></Undefine>
+              <IncludePath>board\ports;..\..\libraries\drivers;..\..\..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\..\..\components\drivers\include;packages\nxp-imxrt-sdk-latest\MIMXRT1180\CMSIS\Core\m-profile;..\..\..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\..\..\components\net\utest;..\..\..\..\..\..\components\libc\posix\io\poll;xip;..\..\..\..\..\..\components\drivers\include;..\..\..\..\..\..\components\drivers\include;..\..\..\..\..\..\libcpu\arm\cortex-m33;..\..\..\..\..\..\include;.;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\periph;board\MCUX_Config;..\..\..\..\..\..\components\drivers\include;..\..\..\..\..\..\components\drivers\smp_call;..\..\..\..\..\..\components\drivers\phy;..\..\..\..\..\..\components\drivers\include;..\..\..\..\..\..\components\libc\posix\ipc;applications;packages\nxp-imxrt-sdk-latest\MIMXRT1180\CMSIS\Core\Include;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers;..\..\..\..\..\..\components\drivers\include;board;..\..\..\..\..\..\components\libc\compilers\common\include;..\..\..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\..\..\components\finsh;..\..\..\..\..\..\libcpu\arm\common;..\..\..\..\..\..\components\libc\compilers\common\extension;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189;packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\cm33</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
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+            <Rwpi>0</Rwpi>
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+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>1</ClangAsOpt>
+            <VariousControls>
+              <MiscControls>-x assembler-with-cpp</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.scf</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc> --keep=*(.boot_hdr.container) --keep=*(.boot_hdr.conf) --entry=Reset_Handler  --predefine="-DXIP_BOOT_HEADER_ENABLE=1" --predefine="-DXIP_EXTERNAL_FLASH=1"</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings>6439,6314</DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CPU</GroupName>
+          <Files>
+            <File>
+              <FileName>atomic_arm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\..\libcpu\arm\common\atomic_arm.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
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+              <FilePath>..\..\..\..\..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
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+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\..\..\libcpu\arm\cortex-m33\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\..\libcpu\arm\cortex-m33\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>syscall_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>trustzone.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\..\libcpu\arm\cortex-m33\trustzone.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\..\components\drivers\core\device.c</FilePath>
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+                  <ComprImg>1</ComprImg>
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+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls> </MiscControls>
+                      <Define>__RT_IPC_SOURCE__</Define>
+                      <Undefine> </Undefine>
+                      <IncludePath> </IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>completion_comm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\..\..\components\drivers\ipc\completion_comm.c</FilePath>
+              <FileOption>
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+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
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+        <LayTarg>0</LayTarg>
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diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h
index 4c728b11f4..baecd2a65b 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h
@@ -147,8 +147,9 @@
 #define RT_USING_DEVICE_IPC
 #define RT_UNAMED_PIPE_NUMBER 64
 #define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_SERIAL_V2
+#define RT_SERIAL_BUF_STRATEGY_OVERWRITE
+#define RT_SERIAL_USING_DMA
 #define RT_USING_ADC
 #define RT_USING_PIN
 /* end of Device Drivers */
@@ -431,8 +432,13 @@
 #define BSP_USING_LPADC
 #define BSP_USING_LPADC1
 #define BSP_LPADC1_USING_DMA
+#define BSP_USING_GPIO
 #define BSP_USING_LPUART
 #define BSP_USING_LPUART1
+#define BSP_LPUART1_RX_USING_DMA
+#define BSP_LPUART1_RX_DMA_CHANNEL 0
+#define BSP_LPUART1_TX_USING_DMA
+#define BSP_LPUART1_TX_DMA_CHANNEL 1
 /* end of On-chip Peripheral Drivers */
 
 /* Onboard Peripheral Drivers */
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx
index cef821f2bc..d396836dbb 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx
@@ -1061,9 +1061,9 @@
               </FileOption>
             </File>
             <File>
-              <FileName>dev_serial.c</FileName>
+              <FileName>dev_serial_v2.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\..\..\components\drivers\serial\dev_serial.c</FilePath>
+              <FilePath>..\..\..\..\..\components\drivers\serial\dev_serial_v2.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -1142,9 +1142,9 @@
               <FilePath>..\libraries\drivers\drv_common.c</FilePath>
             </File>
             <File>
-              <FileName>drv_uart.c</FileName>
+              <FileName>drv_uart_v2.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\drivers\drv_uart.c</FilePath>
+              <FilePath>..\libraries\drivers\drv_uart_v2.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -2162,6 +2162,21 @@
               <FilePath>packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart.c</FilePath>
             </File>
             <File>
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+              <FileType>1</FileType>
+              <FilePath>packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart_edma.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_edma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_edma_soc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma_soc.c</FilePath>
+            </File>
+            <File>
               <FileName>fsl_dcdc.c</FileName>
               <FileType>1</FileType>
               <FilePath>packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_dcdc.c</FilePath>
diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript
index 9cc4b48ad6..797b0beed9 100644
--- a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript
+++ b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript
@@ -13,7 +13,10 @@ if GetDepend('BSP_USING_GPIO'):
     src += ['drv_gpio.c']
 
 if  GetDepend('BSP_USING_LPUART'):
-    src += ['drv_uart.c']
+    if GetDepend('RT_USING_SERIAL_V2'):
+        src += ['drv_uart_v2.c']
+    else:
+        src += ['drv_uart.c']
 
 if  GetDepend('BSP_USING_CLOCK_TIMER'):
     src += ['drv_timer.c']
diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c
index 018785b945..fbd075b39a 100644
--- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c
+++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c
@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018-4-30     misonyo     the first version.
  * 2022-6-22     solar       Implement api docking of rt_pin_get.
+ * 2026-6-9      shannon     support IMXRT1180 series.
  */
 
 #include <rtthread.h>
@@ -15,13 +16,21 @@
 #include <rthw.h>
 #include "drv_gpio.h"
 #include "board.h"
+#ifdef SOC_IMXRT1180_SERIES
+#include "fsl_rgpio.h"
+#else
 #include "fsl_gpio.h"
+#endif
 #include "fsl_iomuxc.h"
 
 #define LOG_TAG             "drv.gpio"
 #include <drv_log.h>
 
+#ifdef SOC_IMXRT1180_SERIES
+#define IMX_PIN_NUM(port, no) (((((port) & 0x7u) << 5) | ((no) & 0x1Fu)))
+#else
 #define IMX_PIN_NUM(port, no) (((((port) & 0x5u) << 5) | ((no) & 0x1Fu)))
+#endif
 
 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
 #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
@@ -29,8 +38,10 @@
 
 #define __IMXRT_HDR_DEFAULT                      {-1, 0, RT_NULL, RT_NULL}
 
-#ifdef SOC_IMXRT1170_SERIES
+#if defined(SOC_IMXRT1170_SERIES)
 #define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 7) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0)
+#elif defined(SOC_IMXRT1180_SERIES)
+#define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 5) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0)
 #else
 #define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 4) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0)
 #endif
@@ -44,6 +55,9 @@
 #elif defined(SOC_IMXRT1170_SERIES)
 #define MUX_BASE         0x400E8010
 #define CONFIG_BASE      0x400E8254
+#elif defined(SOC_IMXRT1180_SERIES)
+#define MUX_BASE    (IOMUXC_BASE + 0x10u)
+#define CONFIG_BASE (IOMUXC_BASE + 0x258u)
 #else /* 1050 & 1060 & 1064 series*/
 #define MUX_BASE         0x401f8014
 #define CONFIG_BASE      0x401f8204
@@ -56,43 +70,65 @@
 #define GPIO13_MUX_BASE      0x40C94000
 #define GPIO13_CONFIG_BASE   0x40C94040
 
+#if defined(SOC_IMXRT1180_SERIES)
+#define AON_MUX_BASE    (IOMUXC_AON_BASE)
+#define AON_CONFIG_BASE (IOMUXC_AON_BASE + 0x74u)
+#endif
+
 struct pin_mask
 {
+#if defined(SOC_IMXRT1180_SERIES)
+    RGPIO_Type *gpio;
+#else
     GPIO_Type    *gpio;
+#endif
     rt_int32_t    valid_mask;
 };
 
+#if defined(SOC_IMXRT1170_SERIES)
 const struct pin_mask mask_tab[7] =
-{
+#elif defined(SOC_IMXRT1180_SERIES)
+const struct pin_mask mask_tab[6] =
+#else
+const struct pin_mask mask_tab[5] =
+#endif
+    {
 #if defined(SOC_IMXRT1015_SERIES)
-    {GPIO1, 0xfc00ffff},     /* GPIO1,16~25 not supported */
-    {GPIO2, 0xffff03f8},     /* GPIO2,0~2,10~15 not supported */
-    {GPIO3, 0x7ff0000f},     /* GPIO3,4~19 not supported */
-    {GPIO4, 0x00000000},     /* GPIO4 not supported */
-    {GPIO5, 0x00000001}      /* GPIO5,0,2,3~31 not supported */
+        { GPIO1, 0xfc00ffff },     /* GPIO1,16~25 not supported */
+        { GPIO2, 0xffff03f8 },     /* GPIO2,0~2,10~15 not supported */
+        { GPIO3, 0x7ff0000f },     /* GPIO3,4~19 not supported */
+        { GPIO4, 0x00000000 },     /* GPIO4 not supported */
+        { GPIO5, 0x00000001 }      /* GPIO5,0,2,3~31 not supported */
 #elif defined(SOC_IMXRT1020_SERIES)
-    {GPIO1, 0xffffffff},     /* GPIO1 */
-    {GPIO2, 0xffffffff},     /* GPIO2 */
-    {GPIO3, 0xffffe3ff},     /* GPIO3,10~12 not supported */
-    {GPIO5, 0x00000000},     /* GPIO4 not supported */
-    {GPIO5, 0x00000007}      /* GPIO5,3~31 not supported */
+        { GPIO1, 0xffffffff },     /* GPIO1 */
+        { GPIO2, 0xffffffff },     /* GPIO2 */
+        { GPIO3, 0xffffe3ff },     /* GPIO3,10~12 not supported */
+        { GPIO5, 0x00000000 },     /* GPIO4 not supported */
+        { GPIO5, 0x00000007 }      /* GPIO5,3~31 not supported */
 #elif defined(SOC_IMXRT1170_SERIES)
-    {GPIO1, 0xffffffff},
-    {GPIO2, 0xffffffff},
-    {GPIO3, 0xffffffff},
-    {GPIO4, 0xffffffff},
-    {GPIO5, 0x0001ffff},
-    {GPIO6, 0x0000ffff},
-    {GPIO13, 0x00001fff},
+        { GPIO1, 0xffffffff },
+        { GPIO2, 0xffffffff },
+        { GPIO3, 0xffffffff },
+        { GPIO4, 0xffffffff },
+        { GPIO5, 0x0001ffff },
+        { GPIO6, 0x0000ffff },
+        { GPIO13, 0x00001fff },
+#elif defined(SOC_IMXRT1180_SERIES)
+    { RGPIO1, 0x0fffffff },   /* GPIO1, pins 28~31 not supported */
+    { RGPIO2, 0xffffffff },   /* GPIO2 */
+    { RGPIO3, 0x7fffffff },   /* GPIO3, pin 31 not supported */
+    { RGPIO4, 0xffffffff },   /* GPIO4 */
+    { RGPIO5, 0x007fffff },   /* GPIO5, pins 23~31 not supported */
+    { RGPIO6, 0x0fffffff },   /* GPIO6, pins 28~31 not supported */
 #else   /* 1050 & 1060 & 1064 series*/
-    {GPIO1, 0xffffffff},     /* GPIO1 */
-    {GPIO2, 0xffffffff},     /* GPIO2 */
-    {GPIO3, 0x0fffffff},     /* GPIO3,28~31 not supported */
-    {GPIO4, 0xffffffff},     /* GPIO4 */
-    {GPIO5, 0x00000007}      /* GPIO5,3~31 not supported */
+    { GPIO1, 0xffffffff },     /* GPIO1 */
+    { GPIO2, 0xffffffff },     /* GPIO2 */
+    { GPIO3, 0x0fffffff },     /* GPIO3,28~31 not supported */
+    { GPIO4, 0xffffffff },     /* GPIO4 */
+    { GPIO5, 0x00000007 }      /* GPIO5,3~31 not supported */
 #endif
 
-};
+    };
 
 const rt_int32_t reg_offset[] =
 {
@@ -110,6 +146,205 @@ const rt_int32_t reg_offset[] =
     64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
     96, 97, 98, 99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,
     128,129, 130,131,132,133,134,135,136,137,138,139,140,141,142,143,144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,  -1, -1, -1, -1,
+#elif defined(SOC_IMXRT1180_SERIES)
+    /* GPIO1 (AON domain) */
+    0,
+    1,
+    2,
+    3,
+    4,
+    5,
+    6,
+    7,
+    8,
+    9,
+    10,
+    11,
+    12,
+    13,
+    14,
+    15,
+    16,
+    17,
+    18,
+    19,
+    20,
+    21,
+    22,
+    23,
+    24,
+    25,
+    26,
+    27,
+    -1,
+    -1,
+    -1,
+    -1,
+    /* GPIO2 (main domain) */
+    0,
+    1,
+    2,
+    3,
+    4,
+    5,
+    6,
+    7,
+    8,
+    9,
+    10,
+    11,
+    12,
+    13,
+    14,
+    15,
+    16,
+    17,
+    18,
+    19,
+    20,
+    21,
+    22,
+    23,
+    24,
+    25,
+    26,
+    27,
+    28,
+    29,
+    30,
+    31,
+    /* GPIO3 (main domain) */
+    32,
+    33,
+    34,
+    35,
+    36,
+    37,
+    38,
+    39,
+    40,
+    41,
+    42,
+    43,
+    44,
+    45,
+    46,
+    47,
+    48,
+    49,
+    50,
+    51,
+    52,
+    53,
+    54,
+    55,
+    56,
+    57,
+    58,
+    59,
+    60,
+    61,
+    62,
+    -1,
+    /* GPIO4 (main domain) */
+    63,
+    64,
+    65,
+    66,
+    67,
+    68,
+    69,
+    70,
+    71,
+    72,
+    73,
+    74,
+    75,
+    76,
+    77,
+    78,
+    79,
+    80,
+    81,
+    82,
+    83,
+    84,
+    85,
+    86,
+    87,
+    88,
+    89,
+    90,
+    91,
+    92,
+    93,
+    94,
+    /* GPIO5 (main domain) */
+    95,
+    96,
+    97,
+    98,
+    99,
+    100,
+    101,
+    102,
+    103,
+    104,
+    105,
+    106,
+    107,
+    108,
+    109,
+    110,
+    111,
+    112,
+    113,
+    114,
+    115,
+    116,
+    117,
+    -1,
+    -1,
+    -1,
+    -1,
+    -1,
+    -1,
+    -1,
+    -1,
+    -1,
+    /* GPIO6 (main domain) */
+    118,
+    119,
+    120,
+    121,
+    122,
+    123,
+    124,
+    125,
+    126,
+    127,
+    128,
+    129,
+    130,
+    131,
+    132,
+    133,
+    134,
+    135,
+    136,
+    137,
+    138,
+    139,
+    140,
+    141,
+    142,
+    143,
+    144,
+    145,
+    -1,
+    -1,
+    -1,
+    -1,
 #else /* 1050 & 1060 & 1064 series*/
     42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
     74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
@@ -119,8 +354,21 @@ const rt_int32_t reg_offset[] =
 
 };
 
-static const IRQn_Type irq_tab[13] =
-{
+static const IRQn_Type irq_tab[] = {
+#if defined(SOC_IMXRT1180_SERIES)
+    GPIO1_0_IRQn,
+    GPIO1_1_IRQn,
+    GPIO2_0_IRQn,
+    GPIO2_1_IRQn,
+    GPIO3_0_IRQn,
+    GPIO3_1_IRQn,
+    GPIO4_IRQn,
+    GPIO4_IRQn,
+    GPIO5_IRQn,
+    GPIO5_IRQn,
+    GPIO6_IRQn,
+    GPIO6_IRQn,
+#else
     GPIO1_Combined_0_15_IRQn,
     GPIO1_Combined_16_31_IRQn,
     GPIO2_Combined_0_15_IRQn,
@@ -138,10 +386,210 @@ static const IRQn_Type irq_tab[13] =
     GPIO6_Combined_16_31_IRQn,
     GPIO13_Combined_0_31_IRQn
 #endif
+#endif
 };
 
-static struct rt_pin_irq_hdr hdr_tab[] =
-{
+static struct rt_pin_irq_hdr hdr_tab[] = {
+#if defined(SOC_IMXRT1180_SERIES)
+    /* GPIO1 */
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    /* GPIO2 */
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    /* GPIO3 */
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    /* GPIO4 */
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    /* GPIO5 */
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    /* GPIO6 */
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+    __IMXRT_HDR_DEFAULT,
+#else
     /* GPIO1 */
     __IMXRT_HDR_DEFAULT,
     __IMXRT_HDR_DEFAULT,
@@ -375,8 +823,32 @@ static struct rt_pin_irq_hdr hdr_tab[] =
     __IMXRT_HDR_DEFAULT,
     __IMXRT_HDR_DEFAULT,
 #endif
+#endif
 };
 
+#if defined(SOC_IMXRT1180_SERIES)
+static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, RGPIO_Type *base)
+{
+    rt_int32_t isr_status, index;
+    rt_int8_t i, pin_end;
+
+    pin_end = pin_start + 15;
+    isr_status = RGPIO_GetPinsInterruptFlags(base, 0);
+
+    for (i = pin_start; i <= pin_end; i++)
+    {
+        if (isr_status & (1 << i))
+        {
+            RGPIO_ClearPinsInterruptFlags(base, 0, (1 << i));
+            index = index_offset + i;
+            if (hdr_tab[index].hdr != RT_NULL)
+            {
+                hdr_tab[index].hdr(hdr_tab[index].args);
+            }
+        }
+    }
+}
+#else
 static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *base)
 {
     rt_int32_t isr_status, index;
@@ -398,7 +870,73 @@ static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *b
         }
     }
 }
+#endif
 
+#if defined(SOC_IMXRT1180_SERIES)
+/* GPIO1 index offset is 0 */
+void GPIO1_0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(0, 0, RGPIO1);
+    rt_interrupt_leave();
+}
+void GPIO1_1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(0, 16, RGPIO1);
+    rt_interrupt_leave();
+}
+/* GPIO2 index offset is 32 */
+void GPIO2_0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(32, 0, RGPIO2);
+    rt_interrupt_leave();
+}
+void GPIO2_1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(32, 16, RGPIO2);
+    rt_interrupt_leave();
+}
+/* GPIO3 index offset is 64 */
+void GPIO3_0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(64, 0, RGPIO3);
+    rt_interrupt_leave();
+}
+void GPIO3_1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(64, 16, RGPIO3);
+    rt_interrupt_leave();
+}
+/* GPIO4 index offset is 96 */
+void GPIO4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(96, 0, RGPIO4);
+    imxrt_isr(96, 16, RGPIO4);
+    rt_interrupt_leave();
+}
+/* GPIO5 index offset is 128 */
+void GPIO5_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(128, 0, RGPIO5);
+    imxrt_isr(128, 16, RGPIO5);
+    rt_interrupt_leave();
+}
+/* GPIO6 index offset is 160 */
+void GPIO6_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    imxrt_isr(160, 0, RGPIO6);
+    imxrt_isr(160, 16, RGPIO6);
+    rt_interrupt_leave();
+}
+#else
 /* GPIO1 index offset is 0 */
 void GPIO1_Combined_0_15_IRQHandler(void)
 {
@@ -519,12 +1057,18 @@ void GPIO13_Combined_0_31_IRQHandler(void)
     rt_interrupt_leave();
 }
 #endif
+#endif
 static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
-    gpio_pin_config_t gpio;
     rt_int8_t port, pin_num;
 
-#ifndef SOC_IMXRT1170_SERIES
+#if defined(SOC_IMXRT1180_SERIES)
+    rgpio_pin_config_t gpio;
+    rt_uint32_t config_value = 0;
+#elif defined(SOC_IMXRT1170_SERIES)
+    gpio_pin_config_t gpio;
+#else
+    gpio_pin_config_t gpio;
     rt_uint32_t config_value = 0;
 #endif
 
@@ -537,6 +1081,53 @@ static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
         return;
     }
 
+#if defined(SOC_IMXRT1180_SERIES)
+    gpio.outputLogic = 0;
+    gpio.pinDirection = kRGPIO_DigitalOutput;
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        gpio.pinDirection = kRGPIO_DigitalOutput;
+        config_value = 0x02U;   /* DSE=1 (high driver), ODE=0 (push-pull) */
+        break;
+    case PIN_MODE_INPUT:
+        gpio.pinDirection = kRGPIO_DigitalInput;
+        config_value = 0x00U;   /* no pull, input buffer on */
+        break;
+    case PIN_MODE_INPUT_PULLDOWN:
+        gpio.pinDirection = kRGPIO_DigitalInput;
+        config_value = 0x04U;   /* PUE=1, PUS=0 (weak pull down) */
+        break;
+    case PIN_MODE_INPUT_PULLUP:
+        gpio.pinDirection = kRGPIO_DigitalInput;
+        config_value = 0x0CU;   /* PUE=1, PUS=1 (weak pull up) */
+        break;
+    case PIN_MODE_OUTPUT_OD:
+        gpio.pinDirection = kRGPIO_DigitalOutput;
+        config_value = 0x12U;   /* ODE=1 (open drain), DSE=1 */
+        break;
+    }
+
+    CLOCK_EnableClock(kCLOCK_Iomuxc1);
+
+    if (mask_tab[port].gpio == RGPIO1)
+    {
+        /* AON domain GPIO1 */
+        CLOCK_EnableClock(kCLOCK_Iomuxc2);
+        IOMUXC_SetPinMux(AON_MUX_BASE + pin_num * 4, 0x0U, 0, 0, AON_CONFIG_BASE + pin_num * 4, 1);
+        IOMUXC_SetPinConfig(AON_MUX_BASE + pin_num * 4, 0x0U, 0, 0, AON_CONFIG_BASE + pin_num * 4, config_value);
+    }
+    else
+    {
+        /* Main domain GPIO2-6 */
+        IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
+        IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
+    }
+
+    RGPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio);
+
+#else /* other SOC series */
     gpio.outputLogic = 0;
     gpio.interruptMode = kGPIO_NoIntmode;
 
@@ -620,14 +1211,13 @@ static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 #endif
 
     GPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio);
+#endif
 }
 
 static rt_ssize_t imxrt_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    rt_ssize_t value;
     rt_int8_t port, pin_num;
 
-    value = PIN_LOW;
     port = pin >> 5;
     pin_num = pin & 31;
 
@@ -637,7 +1227,11 @@ static rt_ssize_t imxrt_pin_read(rt_device_t dev, rt_base_t pin)
         return -RT_EINVAL;
     }
 
+#if defined(SOC_IMXRT1180_SERIES)
+    return RGPIO_PinRead(mask_tab[port].gpio, pin_num);
+#else
     return GPIO_PinReadPadStatus(mask_tab[port].gpio, pin_num);
+#endif
 }
 
 static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
@@ -653,7 +1247,11 @@ static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
         return;
     }
 
+#if defined(SOC_IMXRT1180_SERIES)
+    RGPIO_PinWrite(mask_tab[port].gpio, pin_num, value);
+#else
     GPIO_PinWrite(mask_tab[port].gpio, pin_num, value);
+#endif
 }
 
 static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_base_t pin,
@@ -721,7 +1319,6 @@ static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 
 static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
-    gpio_interrupt_mode_t int_mode;
     rt_int8_t port, pin_num, irq_index;
 
     port = pin >> 5;
@@ -739,6 +1336,63 @@ static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt
         return -RT_ENOSYS;
     }
 
+#if defined(SOC_IMXRT1180_SERIES)
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        rgpio_interrupt_config_t int_mode;
+
+        switch (hdr_tab[pin].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            int_mode = kRGPIO_InterruptRisingEdge;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            int_mode = kRGPIO_InterruptFallingEdge;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            int_mode = kRGPIO_InterruptEitherEdge;
+            break;
+        case PIN_IRQ_MODE_HIGH_LEVEL:
+            int_mode = kRGPIO_InterruptLogicOne;
+            break;
+        case PIN_IRQ_MODE_LOW_LEVEL:
+            int_mode = kRGPIO_InterruptLogicZero;
+            break;
+        default:
+            int_mode = kRGPIO_InterruptRisingEdge;
+            break;
+        }
+        irq_index = (port << 1) + (pin_num >> 4);
+        RGPIO_SetPinInterruptConfig(mask_tab[port].gpio, pin_num, 0, int_mode);
+        if (pin_num < 16)
+        {
+            mask_tab[port].gpio->GICLR = (1U << pin_num);
+        }
+        else
+        {
+            mask_tab[port].gpio->GICHR = (1U << (pin_num - 16));
+        }
+        NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
+        EnableIRQ(irq_tab[irq_index]);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        if (pin_num < 16)
+        {
+            mask_tab[port].gpio->GICLR = (1U << (pin_num + 16));
+        }
+        else
+        {
+            mask_tab[port].gpio->GICHR = (1U << pin_num);
+        }
+    }
+    else
+    {
+        return -RT_EINVAL;
+    }
+#else
+    gpio_interrupt_mode_t int_mode;
+
     if (enabled == PIN_IRQ_ENABLE)
     {
         switch (hdr_tab[pin].mode)
@@ -776,6 +1430,7 @@ static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt
     {
         return -RT_EINVAL;
     }
+#endif
 
     return RT_EOK;
 }
@@ -798,7 +1453,11 @@ static rt_base_t imxrt_pin_get(const char *name)
         return -RT_EINVAL;
     }
 
+#if defined(SOC_IMXRT1180_SERIES)
+    if ((name[1] >= '1') && (name[1] <= '6'))
+#else
     if ((name[1] >= '1') && (name[1] <= '5'))
+#endif
     {
         hw_port_num = (int)(name[1] - '1');
     }
diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c
new file mode 100644
index 0000000000..51d041b123
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart_v2.c
@@ -0,0 +1,815 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-10-10     Tanek        the first version
+ * 2019-5-10      misonyo      add DMA TX and RX function
+ * 2026-4-29      Ran          add RT1180 support
+ * 2026-6-4       shannon      add LPUART10/12, Serial V2, DMA (V2)
+ * 2026-6-16      shannon      extract Serial V2 as standalone driver
+ */
+#include <rtthread.h>
+#ifdef RT_USING_SERIAL_V2
+#ifdef BSP_USING_LPUART
+
+#include "rthw.h"
+#include <rtdevice.h>
+#include "drv_uart.h"
+#include "board.h"
+#include "fsl_lpuart.h"
+#include "fsl_lpuart_edma.h"
+#ifndef SOC_IMXRT1180_SERIES
+#include "fsl_dmamux.h"
+#endif
+
+#define LOG_TAG "drv.usart.v2"
+#include <drv_log.h>
+
+#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#endif
+
+enum
+{
+#ifdef BSP_USING_LPUART1
+    LPUART1_INDEX,
+#endif
+#ifdef BSP_USING_LPUART2
+    LPUART2_INDEX,
+#endif
+#ifdef BSP_USING_LPUART3
+    LPUART3_INDEX,
+#endif
+#ifdef BSP_USING_LPUART4
+    LPUART4_INDEX,
+#endif
+#ifdef BSP_USING_LPUART5
+    LPUART5_INDEX,
+#endif
+#ifdef BSP_USING_LPUART6
+    LPUART6_INDEX,
+#endif
+#ifdef BSP_USING_LPUART7
+    LPUART7_INDEX,
+#endif
+#ifdef BSP_USING_LPUART8
+    LPUART8_INDEX,
+#endif
+#ifdef BSP_USING_LPUART10
+    LPUART10_INDEX,
+#endif
+#ifdef BSP_USING_LPUART12
+    LPUART12_INDEX,
+#endif
+};
+
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+struct dma_rx_config
+{
+    edma_handle_t edma;
+    dma_request_source_t request;
+    rt_uint8_t channel;
+    rt_uint32_t last_index;
+    EDMA_Type *edma_base;
+};
+
+struct dma_tx_config
+{
+    edma_handle_t edma;
+    lpuart_edma_handle_t uart_edma;
+    dma_request_source_t request;
+    rt_uint8_t channel;
+    EDMA_Type *edma_base;
+};
+
+#endif
+
+struct imxrt_uart
+{
+    char *name;
+    LPUART_Type *uart_base;
+    IRQn_Type irqn;
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+    struct dma_rx_config *dma_rx;
+    struct dma_tx_config *dma_tx;
+#endif
+    rt_uint16_t dma_flag;
+    struct rt_serial_device serial;
+};
+
+static struct imxrt_uart uarts[] = {
+#ifdef BSP_USING_LPUART1
+    {
+        .name = "uart1",
+        .uart_base = LPUART1,
+        .irqn = LPUART1_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART2
+    {
+        .name = "uart2",
+        .uart_base = LPUART2,
+        .irqn = LPUART2_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART3
+    {
+        .name = "uart3",
+        .uart_base = LPUART3,
+        .irqn = LPUART3_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART4
+    {
+        .name = "uart4",
+        .uart_base = LPUART4,
+        .irqn = LPUART4_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART5
+    {
+        .name = "uart5",
+        .uart_base = LPUART5,
+        .irqn = LPUART5_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART6
+    {
+        .name = "uart6",
+        .uart_base = LPUART6,
+        .irqn = LPUART6_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART7
+    {
+        .name = "uart7",
+        .uart_base = LPUART7,
+        .irqn = LPUART7_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART8
+    {
+        .name = "uart8",
+        .uart_base = LPUART8,
+        .irqn = LPUART8_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART10
+    {
+        .name = "uart10",
+        .uart_base = LPUART10,
+        .irqn = LPUART10_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+#ifdef BSP_USING_LPUART12
+    {
+        .name = "uart12",
+        .uart_base = LPUART12,
+        .irqn = LPUART12_IRQn,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        .dma_rx = RT_NULL,
+        .dma_tx = RT_NULL,
+#endif
+        .dma_flag = 0,
+    },
+#endif
+};
+
+static void uart_get_dma_config(void)
+{
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+#ifdef SOC_IMXRT1180_SERIES
+#ifdef BSP_LPUART1_RX_USING_DMA
+    static struct dma_rx_config uart1_dma_rx = { .request = kDma3RequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 };
+    uarts[LPUART1_INDEX].dma_rx = &uart1_dma_rx;
+    uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+#endif
+#ifdef BSP_LPUART1_TX_USING_DMA
+    static struct dma_tx_config uart1_dma_tx = { .request = kDma3RequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 };
+    uarts[LPUART1_INDEX].dma_tx = &uart1_dma_tx;
+    uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+#endif
+#endif
+
+#ifdef BSP_LPUART10_RX_USING_DMA
+    static struct dma_rx_config uart10_dma_rx = { .request = kDma4RequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA4 };
+    uarts[LPUART10_INDEX].dma_rx = &uart10_dma_rx;
+    uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+#endif
+#ifdef BSP_LPUART10_TX_USING_DMA
+    static struct dma_tx_config uart10_dma_tx = { .request = kDma4RequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA4 };
+    uarts[LPUART10_INDEX].dma_tx = &uart10_dma_tx;
+    uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+#endif
+
+#ifdef BSP_LPUART12_RX_USING_DMA
+    static struct dma_rx_config uart12_dma_rx = { .request = kDma3RequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3 };
+    uarts[LPUART12_INDEX].dma_rx = &uart12_dma_rx;
+    uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+#endif
+#ifdef BSP_LPUART12_TX_USING_DMA
+    static struct dma_tx_config uart12_dma_tx = { .request = kDma3RequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3 };
+    uarts[LPUART12_INDEX].dma_tx = &uart12_dma_tx;
+    uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+#endif
+#endif
+}
+
+static void uart_isr(struct imxrt_uart *uart);
+
+#if defined(BSP_USING_LPUART1)
+void LPUART1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART1_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART2)
+void LPUART2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART2_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART3)
+void LPUART3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART3_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART4)
+void LPUART4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART4_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART5)
+void LPUART5_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART5_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART6)
+void LPUART6_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART6_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART7)
+void LPUART7_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART7_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART8)
+void LPUART8_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART8_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART10)
+void LPUART10_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART10_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_LPUART12)
+void LPUART12_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    uart_isr(&uarts[LPUART12_INDEX]);
+    rt_interrupt_leave();
+}
+#endif
+
+static void uart_isr(struct imxrt_uart *uart)
+{
+    RT_ASSERT(uart != RT_NULL);
+
+    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
+    {
+        uint8_t ch = LPUART_ReadByte(uart->uart_base);
+        rt_hw_serial_control_isr(&uart->serial, RT_HW_SERIAL_CTRL_PUTC, &ch);
+        rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxOverrunFlag)
+    {
+        LPUART_ClearStatusFlags(uart->uart_base, kLPUART_RxOverrunFlag);
+    }
+
+    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)
+    {
+        LPUART_DisableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable);
+        rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE);
+    }
+
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+    if ((LPUART_GetStatusFlags(uart->uart_base) & kLPUART_IdleLineFlag) && (uart->dma_rx != RT_NULL))
+    {
+        LPUART_ClearStatusFlags(uart->uart_base, kLPUART_IdleLineFlag);
+        rt_size_t recv_len;
+        rt_base_t level;
+        level = rt_hw_interrupt_disable();
+        {
+            edma_handle_t *edma_h = &uart->dma_rx->edma;
+            rt_size_t total_index = EDMA_TCD_CITER(&edma_h->tcdBase[edma_h->channel], EDMA_TCD_TYPE(edma_h->base)) & 0x7FFFU;
+            total_index = uart->serial.config.dma_ping_bufsz - total_index;
+            if (total_index > uart->dma_rx->last_index)
+                recv_len = total_index - uart->dma_rx->last_index;
+            else if (total_index < uart->dma_rx->last_index)
+                recv_len = total_index + (uart->serial.config.dma_ping_bufsz - uart->dma_rx->last_index);
+            else
+                recv_len = 0;
+            uart->dma_rx->last_index = total_index;
+        }
+        rt_hw_interrupt_enable(level);
+
+        if (recv_len > 0)
+        {
+            if (recv_len > uart->serial.config.dma_ping_bufsz)
+                recv_len = uart->serial.config.dma_ping_bufsz;
+            rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+        }
+    }
+#endif
+}
+
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)
+{
+    rt_size_t recv_len = 0;
+    rt_base_t level;
+    struct imxrt_uart *uart = (struct imxrt_uart *)userData;
+    RT_ASSERT(uart != RT_NULL);
+
+    if (transferDone)
+    {
+        level = rt_hw_interrupt_disable();
+        if ((EDMA_GetChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel) & kEDMA_DoneFlag) != 0U)
+        {
+            EDMA_ClearChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel, kEDMA_DoneFlag);
+            recv_len = uart->serial.config.dma_ping_bufsz - uart->dma_rx->last_index;
+            uart->dma_rx->last_index = 0;
+        }
+        else
+        {
+            EDMA_ClearChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel, kEDMA_InterruptFlag);
+            rt_size_t total_index = EDMA_TCD_CITER(&handle->tcdBase[handle->channel], EDMA_TCD_TYPE(handle->base)) & 0x7FFFU;
+            total_index = uart->serial.config.dma_ping_bufsz - total_index;
+            if (total_index > uart->dma_rx->last_index)
+                recv_len = total_index - uart->dma_rx->last_index;
+            else
+                recv_len = total_index + (uart->serial.config.dma_ping_bufsz - uart->dma_rx->last_index);
+            uart->dma_rx->last_index = total_index;
+        }
+        rt_hw_interrupt_enable(level);
+
+        if (recv_len)
+        {
+            if (recv_len > uart->serial.config.dma_ping_bufsz)
+                recv_len = uart->serial.config.dma_ping_bufsz;
+            rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+        }
+    }
+}
+
+void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)
+{
+    struct imxrt_uart *uart = (struct imxrt_uart *)userData;
+    RT_ASSERT(uart != RT_NULL);
+
+    if (kStatus_LPUART_TxIdle == status)
+    {
+        rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
+    }
+}
+
+#ifdef SOC_IMXRT1180_SERIES
+static void imxrt_edma_mux_setup(EDMA_Type *base, rt_uint8_t channel, dma_request_source_t request)
+{
+    EDMA_SetChannelMux(base, channel, request);
+}
+#else
+static void imxrt_edma_mux_setup(EDMA_Type *base, rt_uint8_t channel, dma_request_source_t request)
+{
+    (void)base;
+    DMAMUX_SetSource(DMAMUX, channel, request);
+    DMAMUX_EnableChannel(DMAMUX, channel);
+}
+#endif
+
+static void imxrt_dma_rx_config(struct imxrt_uart *uart)
+{
+    RT_ASSERT(uart != RT_NULL);
+    edma_transfer_config_t xferConfig;
+    EDMA_Type *base = uart->dma_rx->edma_base;
+
+    imxrt_edma_mux_setup(base, uart->dma_rx->channel, uart->dma_rx->request);
+
+    EDMA_CreateHandle(&uart->dma_rx->edma, base, uart->dma_rx->channel);
+    EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart);
+
+    rt_uint8_t *ping_buf;
+    rt_hw_serial_control_isr(&uart->serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, (void *)&ping_buf);
+
+    EDMA_PrepareTransfer(&xferConfig,
+                         (void *)LPUART_GetDataRegisterAddress(uart->uart_base),
+                         sizeof(uint8_t),
+                         ping_buf,
+                         sizeof(uint8_t),
+                         sizeof(uint8_t),
+                         uart->serial.config.dma_ping_bufsz,
+                         kEDMA_PeripheralToMemory);
+
+    EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig);
+    EDMA_EnableChannelInterrupts(base, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable);
+    EDMA_EnableAutoStopRequest(base, uart->dma_rx->channel, false);
+    EDMA_TCD_DLAST_SGA(&uart->dma_rx->edma.tcdBase[uart->dma_rx->edma.channel], EDMA_TCD_TYPE(uart->dma_rx->edma.base)) = -(int32_t)uart->serial.config.dma_ping_bufsz;
+    EDMA_StartTransfer(&uart->dma_rx->edma);
+    LPUART_EnableRxDMA(uart->uart_base, true);
+
+    LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable);
+    NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
+    EnableIRQ(uart->irqn);
+
+    LOG_D("%s dma rx config done\n", uart->name);
+}
+
+static void imxrt_dma_tx_config(struct imxrt_uart *uart)
+{
+    RT_ASSERT(uart != RT_NULL);
+    EDMA_Type *base = uart->dma_tx->edma_base;
+
+    imxrt_edma_mux_setup(base, uart->dma_tx->channel, uart->dma_tx->request);
+
+    EDMA_CreateHandle(&uart->dma_tx->edma, base, uart->dma_tx->channel);
+
+    LPUART_TransferCreateHandleEDMA(uart->uart_base,
+                                    &uart->dma_tx->uart_edma,
+                                    edma_tx_callback,
+                                    uart,
+                                    &uart->dma_tx->edma,
+                                    RT_NULL);
+
+    LOG_D("%s dma tx config done\n", uart->name);
+}
+#endif
+
+uint32_t GetUartSrcFreq(LPUART_Type *uart_base)
+{
+    uint32_t freq;
+#if defined(SOC_IMXRT1170_SERIES)
+    uint32_t base = (uint32_t)uart_base;
+    switch (base)
+    {
+    case LPUART1_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1);
+        break;
+    case LPUART12_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12);
+        break;
+    default:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2);
+        break;
+    }
+#elif defined(SOC_IMXRT1180_SERIES)
+    uint32_t base = (uint32_t)uart_base;
+    switch (base)
+    {
+    case LPUART1_BASE:
+    case LPUART2_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102);
+        break;
+    case LPUART3_BASE:
+    case LPUART4_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304);
+        break;
+    case LPUART5_BASE:
+    case LPUART6_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506);
+        break;
+    case LPUART7_BASE:
+    case LPUART8_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708);
+        break;
+    case LPUART9_BASE:
+    case LPUART10_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910);
+        break;
+    case LPUART11_BASE:
+    case LPUART12_BASE:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112);
+        break;
+    default:
+        freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102);
+        break;
+    }
+#else
+    if (CLOCK_GetMux(kCLOCK_UartMux) == 0)
+    {
+        freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+    }
+    else
+    {
+        freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+    }
+#endif
+    return freq;
+}
+
+static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct imxrt_uart *uart;
+    lpuart_config_t config;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = rt_container_of(serial, struct imxrt_uart, serial);
+
+    LPUART_GetDefaultConfig(&config);
+    config.baudRate_Bps = cfg->baud_rate;
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_7:
+        config.dataBitsCount = kLPUART_SevenDataBits;
+        break;
+    default:
+        config.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_2:
+        config.stopBitCount = kLPUART_TwoStopBit;
+        break;
+    default:
+        config.stopBitCount = kLPUART_OneStopBit;
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_ODD:
+        config.parityMode = kLPUART_ParityOdd;
+        break;
+    case PARITY_EVEN:
+        config.parityMode = kLPUART_ParityEven;
+        break;
+    default:
+        config.parityMode = kLPUART_ParityDisabled;
+        break;
+    }
+
+    config.enableTx = true;
+    config.enableRx = true;
+
+    LPUART_Init(uart->uart_base, &config, GetUartSrcFreq(uart->uart_base));
+
+    return RT_EOK;
+}
+
+static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct imxrt_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct imxrt_uart, serial);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        DisableIRQ(uart->irqn);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
+        NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
+        EnableIRQ(uart->irqn);
+        break;
+
+    case RT_DEVICE_CTRL_CONFIG:
+    {
+        rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+        if (RT_DEVICE_FLAG_DMA_RX == ctrl_arg)
+        {
+            imxrt_dma_rx_config(uart);
+            break;
+        }
+        if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg)
+        {
+            imxrt_dma_tx_config(uart);
+            break;
+        }
+#endif
+
+        if (RT_DEVICE_FLAG_RX_BLOCKING == ctrl_arg || RT_DEVICE_FLAG_RX_NON_BLOCKING == ctrl_arg)
+        {
+            LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
+            NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
+            EnableIRQ(uart->irqn);
+            break;
+        }
+        if (RT_DEVICE_FLAG_TX_BLOCKING == ctrl_arg || RT_DEVICE_FLAG_TX_NON_BLOCKING == ctrl_arg)
+        {
+            LPUART_EnableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable);
+            NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
+            EnableIRQ(uart->irqn);
+            break;
+        }
+        break;
+    }
+
+    case RT_DEVICE_CHECK_OPTMODE:
+        if (uart->dma_flag & RT_DEVICE_FLAG_DMA_TX)
+            return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
+        return RT_SERIAL_TX_BLOCKING_BUFFER;
+    }
+
+    return RT_EOK;
+}
+
+static int imxrt_putc(struct rt_serial_device *serial, char ch)
+{
+    struct imxrt_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct imxrt_uart, serial);
+
+    LPUART_WriteByte(uart->uart_base, ch);
+    while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag))
+        ;
+
+    return 1;
+}
+
+static int imxrt_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct imxrt_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct imxrt_uart, serial);
+
+    ch = -1;
+    if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
+    {
+        ch = LPUART_ReadByte(uart->uart_base);
+    }
+
+    return ch;
+}
+
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+static rt_ssize_t imxrt_transmit(struct rt_serial_device *serial,
+                                 rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag)
+{
+    struct imxrt_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct imxrt_uart, serial);
+
+    if (uart->dma_flag & RT_DEVICE_FLAG_DMA_TX)
+    {
+        lpuart_transfer_t xfer;
+        RT_ASSERT(buf != RT_NULL);
+        xfer.data = buf;
+        xfer.dataSize = size;
+        if (LPUART_SendEDMA(uart->uart_base, &uart->dma_tx->uart_edma, &xfer) == kStatus_Success)
+            return (rt_ssize_t)size;
+        return -RT_EIO;
+    }
+
+    if (size == 0)
+    {
+        LPUART_EnableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable);
+        return 0;
+    }
+
+    {
+        rt_uint8_t *ptr = buf;
+        while (size--)
+        {
+            LPUART_WriteByte(uart->uart_base, *ptr++);
+            while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag))
+                ;
+        }
+        return (rt_ssize_t)(ptr - buf);
+    }
+}
+
+#endif
+
+static const struct rt_uart_ops imxrt_uart_ops = {
+    imxrt_configure,
+    imxrt_control,
+    imxrt_putc,
+    imxrt_getc,
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA)
+    imxrt_transmit,
+#else
+    RT_NULL
+#endif
+};
+
+int rt_hw_uart_init(void)
+{
+    int i;
+    rt_err_t ret = RT_EOK;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart_get_dma_config();
+
+    for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
+    {
+        uarts[i].serial.ops = &imxrt_uart_ops;
+        uarts[i].serial.config = config;
+
+        ret = rt_hw_serial_register(&uarts[i].serial, uarts[i].name,
+                                    RT_DEVICE_FLAG_RDWR, NULL);
+    }
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif /* BSP_USING_LPUART */
+#endif /* RT_USING_SERIAL_V2 */
author	shannon2000 <[email protected]>	2026-07-20 09:08:53 +0800
committer	GitHub <[email protected]>	2026-07-20 09:08:53 +0800
commit	247f540f6bf5fd182f0426d719f3902bdd885fa5 (patch)
tree	156727a07262a6cd62e9341829834e2ae7bfe532
parent	23c05e48a1d61b72096b5e6f5ceb0c26b7da9b80 (diff)