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authorShell <[email protected]>2024-05-26 22:00:17 +0800
committerGitHub <[email protected]>2024-05-26 22:00:17 +0800
commit397cdcd1320d096d41523cbbe0bf743e872d5e70 (patch)
tree2403a47fc109405e73269fe590bdc706e1730b55
parent1a1514640a7bb1af107e400b4e27d07f7a7c444f (diff)
[libcpu] discard rt_current_thread (#8976)
* [libcpu] rv64: discard rt_current_thread * arm: using rt_thread_self to fetch current TCB
-rw-r--r--components/lwp/arch/risc-v/rv64/lwp_gcc.S9
-rw-r--r--libcpu/arm/cortex-m33/context_gcc.S3
-rw-r--r--libcpu/arm/cortex-m7/context_gcc.S3
-rw-r--r--libcpu/risc-v/t-head/c906/context_gcc.S10
-rw-r--r--libcpu/risc-v/virt64/context_gcc.S10
5 files changed, 14 insertions, 21 deletions
diff --git a/components/lwp/arch/risc-v/rv64/lwp_gcc.S b/components/lwp/arch/risc-v/rv64/lwp_gcc.S
index ab0f722bf1..0f97b4ab78 100644
--- a/components/lwp/arch/risc-v/rv64/lwp_gcc.S
+++ b/components/lwp/arch/risc-v/rv64/lwp_gcc.S
@@ -35,7 +35,7 @@ arch_start_umode:
// load kstack for user process
csrw sscratch, a3
li t0, SSTATUS_SPP | SSTATUS_SIE // set as user mode, close interrupt
- csrc sstatus, t0
+ csrc sstatus, t0
li t0, SSTATUS_SPIE // enable interrupt when return to user mode
csrs sstatus, t0
@@ -112,7 +112,7 @@ arch_signal_quit:
mv sp, a0
/* restore user sp before enter trap */
- addi a0, sp, CTX_REG_NR * REGBYTES
+ addi a0, sp, CTX_REG_NR * REGBYTES
csrw sscratch, a0
@@ -234,8 +234,7 @@ __restore_sp_from_sscratch: // from kernel
j __move_stack_context
__restore_sp_from_tcb: // from user
- la a0, rt_current_thread
- LOAD a0, 0(a0)
+ jal rt_thread_self
jal get_thread_kernel_stack_top
mv t0, a0
@@ -272,7 +271,7 @@ copy_context_loop:
call syscall_handler
j arch_syscall_exit
START_POINT_END(syscall_entry)
-
+
.global arch_syscall_exit
arch_syscall_exit:
CLOSE_INTERRUPT
diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S
index c0bc32222e..adf162f2d3 100644
--- a/libcpu/arm/cortex-m33/context_gcc.S
+++ b/libcpu/arm/cortex-m33/context_gcc.S
@@ -196,8 +196,7 @@ contex_ns_load:
#if defined (RT_USING_MEM_PROTECTION)
PUSH {r0-r3, r12, lr}
- LDR r1, =rt_current_thread
- LDR r0, [r1]
+ BL rt_thread_self
BL rt_hw_mpu_table_switch
POP {r0-r3, r12, lr}
#endif
diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S
index 14fd3711b3..cbc03e0553 100644
--- a/libcpu/arm/cortex-m7/context_gcc.S
+++ b/libcpu/arm/cortex-m7/context_gcc.S
@@ -156,8 +156,7 @@ switch_to_thread:
#if defined (RT_USING_MEM_PROTECTION)
PUSH {r0-r3, r12, lr}
- LDR r1, =rt_current_thread
- LDR r0, [r1]
+ BL rt_thread_self
BL rt_hw_mpu_table_switch
POP {r0-r3, r12, lr}
#endif
diff --git a/libcpu/risc-v/t-head/c906/context_gcc.S b/libcpu/risc-v/t-head/c906/context_gcc.S
index f91a0bf3db..7368e01ea1 100644
--- a/libcpu/risc-v/t-head/c906/context_gcc.S
+++ b/libcpu/risc-v/t-head/c906/context_gcc.S
@@ -17,11 +17,10 @@
rt_hw_context_switch_to:
LOAD sp, (a0)
- la s0, rt_current_thread
- LOAD s1, (s0)
+ jal rt_thread_self
+ mv s1, a0
#ifdef RT_USING_SMART
- mv a0, s1
jal lwp_aspace_switch
#endif
@@ -50,11 +49,10 @@ rt_hw_context_switch:
//restore to thread context
LOAD sp, (a1)
- la s0, rt_current_thread
- LOAD s1, (s0)
+ jal rt_thread_self
+ mv s1, a0
#ifdef RT_USING_SMART
- mv a0, s1
jal lwp_aspace_switch
#endif
diff --git a/libcpu/risc-v/virt64/context_gcc.S b/libcpu/risc-v/virt64/context_gcc.S
index 0f3f2e08a5..733d15890c 100644
--- a/libcpu/risc-v/virt64/context_gcc.S
+++ b/libcpu/risc-v/virt64/context_gcc.S
@@ -75,11 +75,10 @@
rt_hw_context_switch_to:
LOAD sp, (a0)
- la s0, rt_current_thread
- LOAD s1, (s0)
+ jal rt_thread_self
+ mv s1, a0
#ifdef RT_USING_SMART
- mv a0, s1
jal lwp_aspace_switch
#endif
@@ -103,11 +102,10 @@ rt_hw_context_switch:
LOAD sp, (a1)
// restore Address Space
- la s0, rt_current_thread
- LOAD s1, (s0)
+ jal rt_thread_self
+ mv s1, a0
#ifdef RT_USING_SMART
- mv a0, s1
jal lwp_aspace_switch
#endif